FreeBSD kernel usb device Code
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ehcireg.h File Reference
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Macros

#define PCI_CBMEM   0x10 /* configuration base MEM */
 
#define PCI_INTERFACE_EHCI   0x20
 
#define PCI_USBREV   0x60 /* RO USB protocol revision */
 
#define PCI_USB_REV_MASK   0xff
 
#define PCI_USB_REV_PRE_1_0   0x00
 
#define PCI_USB_REV_1_0   0x10
 
#define PCI_USB_REV_1_1   0x11
 
#define PCI_USB_REV_2_0   0x20
 
#define PCI_EHCI_FLADJ   0x61 /* RW Frame len adj, SOF=59488+6*fladj */
 
#define PCI_EHCI_PORTWAKECAP   0x62 /* RW Port wake caps (opt) */
 
#define EHCI_EC_LEGSUP   0x01
 
#define EHCI_EECP_NEXT(x)   (((x) >> 8) & 0xff)
 
#define EHCI_EECP_ID(x)   ((x) & 0xff)
 
#define EHCI_LEGSUP_BIOS_SEM   0x02
 
#define EHCI_LEGSUP_OS_SEM   0x03
 
#define EHCI_LEGSUP_USBLEGCTLSTS   0x04
 
#define EHCI_CAPLEN_HCIVERSION
 
#define EHCI_CAPLENGTH(x)   ((x) & 0xff)
 
#define EHCI_HCIVERSION(x)   (((x) >> 16) & 0xffff)
 
#define EHCI_HCSPARAMS   0x04 /* RO Structural parameters */
 
#define EHCI_HCS_DEBUGPORT(x)   (((x) >> 20) & 0xf)
 
#define EHCI_HCS_P_INDICATOR(x)   ((x) & 0x10000)
 
#define EHCI_HCS_N_CC(x)   (((x) >> 12) & 0xf) /* # of companion ctlrs */
 
#define EHCI_HCS_N_PCC(x)   (((x) >> 8) & 0xf) /* # of ports per comp. */
 
#define EHCI_HCS_PPC(x)   ((x) & 0x10) /* port power control */
 
#define EHCI_HCS_N_PORTS(x)   ((x) & 0xf) /* # of ports */
 
#define EHCI_HCCPARAMS   0x08 /* RO Capability parameters */
 
#define EHCI_HCC_EECP(x)   (((x) >> 8) & 0xff) /* extended ports caps */
 
#define EHCI_HCC_IST(x)   (((x) >> 4) & 0xf) /* isoc sched threshold */
 
#define EHCI_HCC_ASPC(x)   ((x) & 0x4) /* async sched park cap */
 
#define EHCI_HCC_PFLF(x)   ((x) & 0x2) /* prog frame list flag */
 
#define EHCI_HCC_64BIT(x)   ((x) & 0x1) /* 64 bit address cap */
 
#define EHCI_HCSP_PORTROUTE   0x0c /* RO Companion port route description */
 
#define EHCI_USBCMD   0x00 /* RO, RW, WO Command register */
 
#define EHCI_CMD_ITC_M   0x00ff0000 /* RW interrupt threshold ctrl */
 
#define EHCI_CMD_ITC_1   0x00010000
 
#define EHCI_CMD_ITC_2   0x00020000
 
#define EHCI_CMD_ITC_4   0x00040000
 
#define EHCI_CMD_ITC_8   0x00080000
 
#define EHCI_CMD_ITC_16   0x00100000
 
#define EHCI_CMD_ITC_32   0x00200000
 
#define EHCI_CMD_ITC_64   0x00400000
 
#define EHCI_CMD_ASPME   0x00000800 /* RW/RO async park enable */
 
#define EHCI_CMD_ASPMC   0x00000300 /* RW/RO async park count */
 
#define EHCI_CMD_LHCR   0x00000080 /* RW light host ctrl reset */
 
#define EHCI_CMD_IAAD
 
#define EHCI_CMD_ASE   0x00000020 /* RW async sched enable */
 
#define EHCI_CMD_PSE   0x00000010 /* RW periodic sched enable */
 
#define EHCI_CMD_FLS_M   0x0000000c /* RW/RO frame list size */
 
#define EHCI_CMD_FLS(x)   (((x) >> 2) & 3) /* RW/RO frame list size */
 
#define EHCI_CMD_HCRESET   0x00000002 /* RW reset */
 
#define EHCI_CMD_RS   0x00000001 /* RW run/stop */
 
#define EHCI_USBSTS   0x04 /* RO, RW, RWC Status register */
 
#define EHCI_STS_ASS   0x00008000 /* RO async sched status */
 
#define EHCI_STS_PSS   0x00004000 /* RO periodic sched status */
 
#define EHCI_STS_REC   0x00002000 /* RO reclamation */
 
#define EHCI_STS_HCH   0x00001000 /* RO host controller halted */
 
#define EHCI_STS_IAA   0x00000020 /* RWC interrupt on async adv */
 
#define EHCI_STS_HSE   0x00000010 /* RWC host system error */
 
#define EHCI_STS_FLR   0x00000008 /* RWC frame list rollover */
 
#define EHCI_STS_PCD   0x00000004 /* RWC port change detect */
 
#define EHCI_STS_ERRINT   0x00000002 /* RWC error interrupt */
 
#define EHCI_STS_INT   0x00000001 /* RWC interrupt */
 
#define EHCI_STS_INTRS(x)   ((x) & 0x3f)
 
#define EHCI_NORMAL_INTRS
 
#define EHCI_USBINTR   0x08 /* RW Interrupt register */
 
#define EHCI_INTR_IAAE
 
#define EHCI_INTR_HSEE   0x00000010 /* host system error ena */
 
#define EHCI_INTR_FLRE   0x00000008 /* frame list rollover ena */
 
#define EHCI_INTR_PCIE   0x00000004 /* port change ena */
 
#define EHCI_INTR_UEIE   0x00000002 /* USB error intr ena */
 
#define EHCI_INTR_UIE   0x00000001 /* USB intr ena */
 
#define EHCI_FRINDEX   0x0c /* RW Frame Index register */
 
#define EHCI_CTRLDSSEGMENT   0x10 /* RW Control Data Structure Segment */
 
#define EHCI_PERIODICLISTBASE   0x14 /* RW Periodic List Base */
 
#define EHCI_ASYNCLISTADDR   0x18 /* RW Async List Base */
 
#define EHCI_CONFIGFLAG   0x40 /* RW Configure Flag register */
 
#define EHCI_CONF_CF   0x00000001 /* RW configure flag */
 
#define EHCI_PORTSC(n)   (0x40+(4*(n))) /* RO, RW, RWC Port Status reg */
 
#define EHCI_PS_WKOC_E   0x00400000 /* RW wake on over current ena */
 
#define EHCI_PS_WKDSCNNT_E   0x00200000 /* RW wake on disconnect ena */
 
#define EHCI_PS_WKCNNT_E   0x00100000 /* RW wake on connect ena */
 
#define EHCI_PS_PTC   0x000f0000 /* RW port test control */
 
#define EHCI_PS_PIC   0x0000c000 /* RW port indicator control */
 
#define EHCI_PS_PO   0x00002000 /* RW port owner */
 
#define EHCI_PS_PP   0x00001000 /* RW,RO port power */
 
#define EHCI_PS_LS   0x00000c00 /* RO line status */
 
#define EHCI_PS_IS_LOWSPEED(x)   (((x) & EHCI_PS_LS) == 0x00000400)
 
#define EHCI_PS_PR   0x00000100 /* RW port reset */
 
#define EHCI_PS_SUSP   0x00000080 /* RW suspend */
 
#define EHCI_PS_FPR   0x00000040 /* RW force port resume */
 
#define EHCI_PS_OCC   0x00000020 /* RWC over current change */
 
#define EHCI_PS_OCA   0x00000010 /* RO over current active */
 
#define EHCI_PS_PEC   0x00000008 /* RWC port enable change */
 
#define EHCI_PS_PE   0x00000004 /* RW port enable */
 
#define EHCI_PS_CSC   0x00000002 /* RWC connect status change */
 
#define EHCI_PS_CS   0x00000001 /* RO connect status */
 
#define EHCI_PS_CLEAR   (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
 
#define EHCI_PORT_RESET_COMPLETE   2 /* ms */
 
#define EHCI_USBMODE_NOLPM   0x68 /* RW USB Device mode reg (no LPM) */
 
#define EHCI_USBMODE_LPM   0xC8 /* RW USB Device mode reg (LPM) */
 
#define EHCI_UM_CM   0x00000003 /* R/WO Controller Mode */
 
#define EHCI_UM_CM_IDLE   0x0 /* Idle */
 
#define EHCI_UM_CM_HOST   0x3 /* Host Controller */
 
#define EHCI_UM_ES   0x00000004 /* R/WO Endian Select */
 
#define EHCI_UM_ES_LE   0x0 /* Little-endian byte alignment */
 
#define EHCI_UM_ES_BE   0x4 /* Big-endian byte alignment */
 
#define EHCI_UM_SDIS   0x00000010 /* R/WO Stream Disable Mode */
 
#define EHCI_HOSTC(n)   (0x80+(4*(n))) /* RO, RW Host mode control reg */
 
#define EHCI_HOSTC_PSPD_SHIFT   25
 
#define EHCI_HOSTC_PSPD_MASK   0x3
 
#define EHCI_PORTSC_PSPD_SHIFT   26
 
#define EHCI_PORTSC_PSPD_MASK   0x3
 
#define EHCI_PORT_SPEED_FULL   0
 
#define EHCI_PORT_SPEED_LOW   1
 
#define EHCI_PORT_SPEED_HIGH   2
 

Macro Definition Documentation

◆ EHCI_ASYNCLISTADDR

#define EHCI_ASYNCLISTADDR   0x18 /* RW Async List Base */

Definition at line 130 of file ehcireg.h.

◆ EHCI_CAPLEN_HCIVERSION

#define EHCI_CAPLEN_HCIVERSION
Value:
0x00 /* RO Capability register length
* (least-significant byte) and
* interface version number (two
* most significant)
*/

Definition at line 59 of file ehcireg.h.

◆ EHCI_CAPLENGTH

#define EHCI_CAPLENGTH (   x)    ((x) & 0xff)

Definition at line 60 of file ehcireg.h.

◆ EHCI_CMD_ASE

#define EHCI_CMD_ASE   0x00000020 /* RW async sched enable */

Definition at line 91 of file ehcireg.h.

◆ EHCI_CMD_ASPMC

#define EHCI_CMD_ASPMC   0x00000300 /* RW/RO async park count */

Definition at line 88 of file ehcireg.h.

◆ EHCI_CMD_ASPME

#define EHCI_CMD_ASPME   0x00000800 /* RW/RO async park enable */

Definition at line 87 of file ehcireg.h.

◆ EHCI_CMD_FLS

#define EHCI_CMD_FLS (   x)    (((x) >> 2) & 3) /* RW/RO frame list size */

Definition at line 94 of file ehcireg.h.

◆ EHCI_CMD_FLS_M

#define EHCI_CMD_FLS_M   0x0000000c /* RW/RO frame list size */

Definition at line 93 of file ehcireg.h.

◆ EHCI_CMD_HCRESET

#define EHCI_CMD_HCRESET   0x00000002 /* RW reset */

Definition at line 95 of file ehcireg.h.

◆ EHCI_CMD_IAAD

#define EHCI_CMD_IAAD
Value:
0x00000040 /* RW intr on async adv door
* bell */

Definition at line 90 of file ehcireg.h.

◆ EHCI_CMD_ITC_1

#define EHCI_CMD_ITC_1   0x00010000

Definition at line 80 of file ehcireg.h.

◆ EHCI_CMD_ITC_16

#define EHCI_CMD_ITC_16   0x00100000

Definition at line 84 of file ehcireg.h.

◆ EHCI_CMD_ITC_2

#define EHCI_CMD_ITC_2   0x00020000

Definition at line 81 of file ehcireg.h.

◆ EHCI_CMD_ITC_32

#define EHCI_CMD_ITC_32   0x00200000

Definition at line 85 of file ehcireg.h.

◆ EHCI_CMD_ITC_4

#define EHCI_CMD_ITC_4   0x00040000

Definition at line 82 of file ehcireg.h.

◆ EHCI_CMD_ITC_64

#define EHCI_CMD_ITC_64   0x00400000

Definition at line 86 of file ehcireg.h.

◆ EHCI_CMD_ITC_8

#define EHCI_CMD_ITC_8   0x00080000

Definition at line 83 of file ehcireg.h.

◆ EHCI_CMD_ITC_M

#define EHCI_CMD_ITC_M   0x00ff0000 /* RW interrupt threshold ctrl */

Definition at line 79 of file ehcireg.h.

◆ EHCI_CMD_LHCR

#define EHCI_CMD_LHCR   0x00000080 /* RW light host ctrl reset */

Definition at line 89 of file ehcireg.h.

◆ EHCI_CMD_PSE

#define EHCI_CMD_PSE   0x00000010 /* RW periodic sched enable */

Definition at line 92 of file ehcireg.h.

◆ EHCI_CMD_RS

#define EHCI_CMD_RS   0x00000001 /* RW run/stop */

Definition at line 96 of file ehcireg.h.

◆ EHCI_CONF_CF

#define EHCI_CONF_CF   0x00000001 /* RW configure flag */

Definition at line 133 of file ehcireg.h.

◆ EHCI_CONFIGFLAG

#define EHCI_CONFIGFLAG   0x40 /* RW Configure Flag register */

Definition at line 132 of file ehcireg.h.

◆ EHCI_CTRLDSSEGMENT

#define EHCI_CTRLDSSEGMENT   0x10 /* RW Control Data Structure Segment */

Definition at line 127 of file ehcireg.h.

◆ EHCI_EC_LEGSUP

#define EHCI_EC_LEGSUP   0x01

Definition at line 49 of file ehcireg.h.

◆ EHCI_EECP_ID

#define EHCI_EECP_ID (   x)    ((x) & 0xff)

Definition at line 51 of file ehcireg.h.

◆ EHCI_EECP_NEXT

#define EHCI_EECP_NEXT (   x)    (((x) >> 8) & 0xff)

Definition at line 50 of file ehcireg.h.

◆ EHCI_FRINDEX

#define EHCI_FRINDEX   0x0c /* RW Frame Index register */

Definition at line 125 of file ehcireg.h.

◆ EHCI_HCC_64BIT

#define EHCI_HCC_64BIT (   x)    ((x) & 0x1) /* 64 bit address cap */

Definition at line 74 of file ehcireg.h.

◆ EHCI_HCC_ASPC

#define EHCI_HCC_ASPC (   x)    ((x) & 0x4) /* async sched park cap */

Definition at line 72 of file ehcireg.h.

◆ EHCI_HCC_EECP

#define EHCI_HCC_EECP (   x)    (((x) >> 8) & 0xff) /* extended ports caps */

Definition at line 70 of file ehcireg.h.

◆ EHCI_HCC_IST

#define EHCI_HCC_IST (   x)    (((x) >> 4) & 0xf) /* isoc sched threshold */

Definition at line 71 of file ehcireg.h.

◆ EHCI_HCC_PFLF

#define EHCI_HCC_PFLF (   x)    ((x) & 0x2) /* prog frame list flag */

Definition at line 73 of file ehcireg.h.

◆ EHCI_HCCPARAMS

#define EHCI_HCCPARAMS   0x08 /* RO Capability parameters */

Definition at line 69 of file ehcireg.h.

◆ EHCI_HCIVERSION

#define EHCI_HCIVERSION (   x)    (((x) >> 16) & 0xffff)

Definition at line 61 of file ehcireg.h.

◆ EHCI_HCS_DEBUGPORT

#define EHCI_HCS_DEBUGPORT (   x)    (((x) >> 20) & 0xf)

Definition at line 63 of file ehcireg.h.

◆ EHCI_HCS_N_CC

#define EHCI_HCS_N_CC (   x)    (((x) >> 12) & 0xf) /* # of companion ctlrs */

Definition at line 65 of file ehcireg.h.

◆ EHCI_HCS_N_PCC

#define EHCI_HCS_N_PCC (   x)    (((x) >> 8) & 0xf) /* # of ports per comp. */

Definition at line 66 of file ehcireg.h.

◆ EHCI_HCS_N_PORTS

#define EHCI_HCS_N_PORTS (   x)    ((x) & 0xf) /* # of ports */

Definition at line 68 of file ehcireg.h.

◆ EHCI_HCS_P_INDICATOR

#define EHCI_HCS_P_INDICATOR (   x)    ((x) & 0x10000)

Definition at line 64 of file ehcireg.h.

◆ EHCI_HCS_PPC

#define EHCI_HCS_PPC (   x)    ((x) & 0x10) /* port power control */

Definition at line 67 of file ehcireg.h.

◆ EHCI_HCSP_PORTROUTE

#define EHCI_HCSP_PORTROUTE   0x0c /* RO Companion port route description */

Definition at line 75 of file ehcireg.h.

◆ EHCI_HCSPARAMS

#define EHCI_HCSPARAMS   0x04 /* RO Structural parameters */

Definition at line 62 of file ehcireg.h.

◆ EHCI_HOSTC

#define EHCI_HOSTC (   n)    (0x80+(4*(n))) /* RO, RW Host mode control reg */

Definition at line 179 of file ehcireg.h.

◆ EHCI_HOSTC_PSPD_MASK

#define EHCI_HOSTC_PSPD_MASK   0x3

Definition at line 181 of file ehcireg.h.

◆ EHCI_HOSTC_PSPD_SHIFT

#define EHCI_HOSTC_PSPD_SHIFT   25

Definition at line 180 of file ehcireg.h.

◆ EHCI_INTR_FLRE

#define EHCI_INTR_FLRE   0x00000008 /* frame list rollover ena */

Definition at line 120 of file ehcireg.h.

◆ EHCI_INTR_HSEE

#define EHCI_INTR_HSEE   0x00000010 /* host system error ena */

Definition at line 119 of file ehcireg.h.

◆ EHCI_INTR_IAAE

#define EHCI_INTR_IAAE
Value:
0x00000020 /* interrupt on async advance
* ena */

Definition at line 118 of file ehcireg.h.

◆ EHCI_INTR_PCIE

#define EHCI_INTR_PCIE   0x00000004 /* port change ena */

Definition at line 121 of file ehcireg.h.

◆ EHCI_INTR_UEIE

#define EHCI_INTR_UEIE   0x00000002 /* USB error intr ena */

Definition at line 122 of file ehcireg.h.

◆ EHCI_INTR_UIE

#define EHCI_INTR_UIE   0x00000001 /* USB intr ena */

Definition at line 123 of file ehcireg.h.

◆ EHCI_LEGSUP_BIOS_SEM

#define EHCI_LEGSUP_BIOS_SEM   0x02

Definition at line 54 of file ehcireg.h.

◆ EHCI_LEGSUP_OS_SEM

#define EHCI_LEGSUP_OS_SEM   0x03

Definition at line 55 of file ehcireg.h.

◆ EHCI_LEGSUP_USBLEGCTLSTS

#define EHCI_LEGSUP_USBLEGCTLSTS   0x04

Definition at line 56 of file ehcireg.h.

◆ EHCI_NORMAL_INTRS

#define EHCI_NORMAL_INTRS
Value:
(EHCI_STS_IAA | EHCI_STS_HSE | \
EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
EHCI_STS_INT
#define EHCI_STS_INT
Definition: ehcireg.h:107
EHCI_STS_IAA
#define EHCI_STS_IAA
Definition: ehcireg.h:102
EHCI_STS_HSE
#define EHCI_STS_HSE
Definition: ehcireg.h:103
EHCI_STS_ERRINT
#define EHCI_STS_ERRINT
Definition: ehcireg.h:106

Definition at line 114 of file ehcireg.h.

◆ EHCI_PERIODICLISTBASE

#define EHCI_PERIODICLISTBASE   0x14 /* RW Periodic List Base */

Definition at line 129 of file ehcireg.h.

◆ EHCI_PORT_RESET_COMPLETE

#define EHCI_PORT_RESET_COMPLETE   2 /* ms */

Definition at line 156 of file ehcireg.h.

◆ EHCI_PORT_SPEED_FULL

#define EHCI_PORT_SPEED_FULL   0

Definition at line 186 of file ehcireg.h.

◆ EHCI_PORT_SPEED_HIGH

#define EHCI_PORT_SPEED_HIGH   2

Definition at line 188 of file ehcireg.h.

◆ EHCI_PORT_SPEED_LOW

#define EHCI_PORT_SPEED_LOW   1

Definition at line 187 of file ehcireg.h.

◆ EHCI_PORTSC

#define EHCI_PORTSC (   n)    (0x40+(4*(n))) /* RO, RW, RWC Port Status reg */

Definition at line 135 of file ehcireg.h.

◆ EHCI_PORTSC_PSPD_MASK

#define EHCI_PORTSC_PSPD_MASK   0x3

Definition at line 184 of file ehcireg.h.

◆ EHCI_PORTSC_PSPD_SHIFT

#define EHCI_PORTSC_PSPD_SHIFT   26

Definition at line 183 of file ehcireg.h.

◆ EHCI_PS_CLEAR

#define EHCI_PS_CLEAR   (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)

Definition at line 154 of file ehcireg.h.

◆ EHCI_PS_CS

#define EHCI_PS_CS   0x00000001 /* RO connect status */

Definition at line 153 of file ehcireg.h.

◆ EHCI_PS_CSC

#define EHCI_PS_CSC   0x00000002 /* RWC connect status change */

Definition at line 152 of file ehcireg.h.

◆ EHCI_PS_FPR

#define EHCI_PS_FPR   0x00000040 /* RW force port resume */

Definition at line 147 of file ehcireg.h.

◆ EHCI_PS_IS_LOWSPEED

#define EHCI_PS_IS_LOWSPEED (   x)    (((x) & EHCI_PS_LS) == 0x00000400)

Definition at line 144 of file ehcireg.h.

◆ EHCI_PS_LS

#define EHCI_PS_LS   0x00000c00 /* RO line status */

Definition at line 143 of file ehcireg.h.

◆ EHCI_PS_OCA

#define EHCI_PS_OCA   0x00000010 /* RO over current active */

Definition at line 149 of file ehcireg.h.

◆ EHCI_PS_OCC

#define EHCI_PS_OCC   0x00000020 /* RWC over current change */

Definition at line 148 of file ehcireg.h.

◆ EHCI_PS_PE

#define EHCI_PS_PE   0x00000004 /* RW port enable */

Definition at line 151 of file ehcireg.h.

◆ EHCI_PS_PEC

#define EHCI_PS_PEC   0x00000008 /* RWC port enable change */

Definition at line 150 of file ehcireg.h.

◆ EHCI_PS_PIC

#define EHCI_PS_PIC   0x0000c000 /* RW port indicator control */

Definition at line 140 of file ehcireg.h.

◆ EHCI_PS_PO

#define EHCI_PS_PO   0x00002000 /* RW port owner */

Definition at line 141 of file ehcireg.h.

◆ EHCI_PS_PP

#define EHCI_PS_PP   0x00001000 /* RW,RO port power */

Definition at line 142 of file ehcireg.h.

◆ EHCI_PS_PR

#define EHCI_PS_PR   0x00000100 /* RW port reset */

Definition at line 145 of file ehcireg.h.

◆ EHCI_PS_PTC

#define EHCI_PS_PTC   0x000f0000 /* RW port test control */

Definition at line 139 of file ehcireg.h.

◆ EHCI_PS_SUSP

#define EHCI_PS_SUSP   0x00000080 /* RW suspend */

Definition at line 146 of file ehcireg.h.

◆ EHCI_PS_WKCNNT_E

#define EHCI_PS_WKCNNT_E   0x00100000 /* RW wake on connect ena */

Definition at line 138 of file ehcireg.h.

◆ EHCI_PS_WKDSCNNT_E

#define EHCI_PS_WKDSCNNT_E   0x00200000 /* RW wake on disconnect ena */

Definition at line 137 of file ehcireg.h.

◆ EHCI_PS_WKOC_E

#define EHCI_PS_WKOC_E   0x00400000 /* RW wake on over current ena */

Definition at line 136 of file ehcireg.h.

◆ EHCI_STS_ASS

#define EHCI_STS_ASS   0x00008000 /* RO async sched status */

Definition at line 98 of file ehcireg.h.

◆ EHCI_STS_ERRINT

#define EHCI_STS_ERRINT   0x00000002 /* RWC error interrupt */

Definition at line 106 of file ehcireg.h.

◆ EHCI_STS_FLR

#define EHCI_STS_FLR   0x00000008 /* RWC frame list rollover */

Definition at line 104 of file ehcireg.h.

◆ EHCI_STS_HCH

#define EHCI_STS_HCH   0x00001000 /* RO host controller halted */

Definition at line 101 of file ehcireg.h.

◆ EHCI_STS_HSE

#define EHCI_STS_HSE   0x00000010 /* RWC host system error */

Definition at line 103 of file ehcireg.h.

◆ EHCI_STS_IAA

#define EHCI_STS_IAA   0x00000020 /* RWC interrupt on async adv */

Definition at line 102 of file ehcireg.h.

◆ EHCI_STS_INT

#define EHCI_STS_INT   0x00000001 /* RWC interrupt */

Definition at line 107 of file ehcireg.h.

◆ EHCI_STS_INTRS

#define EHCI_STS_INTRS (   x)    ((x) & 0x3f)

Definition at line 108 of file ehcireg.h.

◆ EHCI_STS_PCD

#define EHCI_STS_PCD   0x00000004 /* RWC port change detect */

Definition at line 105 of file ehcireg.h.

◆ EHCI_STS_PSS

#define EHCI_STS_PSS   0x00004000 /* RO periodic sched status */

Definition at line 99 of file ehcireg.h.

◆ EHCI_STS_REC

#define EHCI_STS_REC   0x00002000 /* RO reclamation */

Definition at line 100 of file ehcireg.h.

◆ EHCI_UM_CM

#define EHCI_UM_CM   0x00000003 /* R/WO Controller Mode */

Definition at line 167 of file ehcireg.h.

◆ EHCI_UM_CM_HOST

#define EHCI_UM_CM_HOST   0x3 /* Host Controller */

Definition at line 169 of file ehcireg.h.

◆ EHCI_UM_CM_IDLE

#define EHCI_UM_CM_IDLE   0x0 /* Idle */

Definition at line 168 of file ehcireg.h.

◆ EHCI_UM_ES

#define EHCI_UM_ES   0x00000004 /* R/WO Endian Select */

Definition at line 170 of file ehcireg.h.

◆ EHCI_UM_ES_BE

#define EHCI_UM_ES_BE   0x4 /* Big-endian byte alignment */

Definition at line 172 of file ehcireg.h.

◆ EHCI_UM_ES_LE

#define EHCI_UM_ES_LE   0x0 /* Little-endian byte alignment */

Definition at line 171 of file ehcireg.h.

◆ EHCI_UM_SDIS

#define EHCI_UM_SDIS   0x00000010 /* R/WO Stream Disable Mode */

Definition at line 173 of file ehcireg.h.

◆ EHCI_USBCMD

#define EHCI_USBCMD   0x00 /* RO, RW, WO Command register */

Definition at line 78 of file ehcireg.h.

◆ EHCI_USBINTR

#define EHCI_USBINTR   0x08 /* RW Interrupt register */

Definition at line 117 of file ehcireg.h.

◆ EHCI_USBMODE_LPM

#define EHCI_USBMODE_LPM   0xC8 /* RW USB Device mode reg (LPM) */

Definition at line 166 of file ehcireg.h.

◆ EHCI_USBMODE_NOLPM

#define EHCI_USBMODE_NOLPM   0x68 /* RW USB Device mode reg (no LPM) */

Definition at line 165 of file ehcireg.h.

◆ EHCI_USBSTS

#define EHCI_USBSTS   0x04 /* RO, RW, RWC Status register */

Definition at line 97 of file ehcireg.h.

◆ PCI_CBMEM

#define PCI_CBMEM   0x10 /* configuration base MEM */

Definition at line 37 of file ehcireg.h.

◆ PCI_EHCI_FLADJ

#define PCI_EHCI_FLADJ   0x61 /* RW Frame len adj, SOF=59488+6*fladj */

Definition at line 45 of file ehcireg.h.

◆ PCI_EHCI_PORTWAKECAP

#define PCI_EHCI_PORTWAKECAP   0x62 /* RW Port wake caps (opt) */

Definition at line 46 of file ehcireg.h.

◆ PCI_INTERFACE_EHCI

#define PCI_INTERFACE_EHCI   0x20

Definition at line 38 of file ehcireg.h.

◆ PCI_USB_REV_1_0

#define PCI_USB_REV_1_0   0x10

Definition at line 42 of file ehcireg.h.

◆ PCI_USB_REV_1_1

#define PCI_USB_REV_1_1   0x11

Definition at line 43 of file ehcireg.h.

◆ PCI_USB_REV_2_0

#define PCI_USB_REV_2_0   0x20

Definition at line 44 of file ehcireg.h.

◆ PCI_USB_REV_MASK

#define PCI_USB_REV_MASK   0xff

Definition at line 40 of file ehcireg.h.

◆ PCI_USB_REV_PRE_1_0

#define PCI_USB_REV_PRE_1_0   0x00

Definition at line 41 of file ehcireg.h.

◆ PCI_USBREV

#define PCI_USBREV   0x60 /* RO USB protocol revision */

Definition at line 39 of file ehcireg.h.