65#define SMSC_TX_CTRL_0_OFFSET(x) (((x) & 0x1FUL) << 16)
66#define SMSC_TX_CTRL_0_FIRST_SEG (0x1UL << 13)
67#define SMSC_TX_CTRL_0_LAST_SEG (0x1UL << 12)
68#define SMSC_TX_CTRL_0_BUF_SIZE(x) ((x) & 0x000007FFUL)
70#define SMSC_TX_CTRL_1_CSUM_ENABLE (0x1UL << 14)
71#define SMSC_TX_CTRL_1_CRC_DISABLE (0x1UL << 13)
72#define SMSC_TX_CTRL_1_PADDING_DISABLE (0x1UL << 12)
73#define SMSC_TX_CTRL_1_PKT_LENGTH(x) ((x) & 0x000007FFUL)
104#define SMSC_RX_STAT_FILTER_FAIL (0x1UL << 30)
105#define SMSC_RX_STAT_FRM_LENGTH(x) (((x) >> 16) & 0x3FFFUL)
106#define SMSC_RX_STAT_ERROR (0x1UL << 15)
107#define SMSC_RX_STAT_BROADCAST (0x1UL << 13)
108#define SMSC_RX_STAT_LENGTH_ERROR (0x1UL << 12)
109#define SMSC_RX_STAT_RUNT (0x1UL << 11)
110#define SMSC_RX_STAT_MULTICAST (0x1UL << 10)
111#define SMSC_RX_STAT_FRM_TO_LONG (0x1UL << 7)
112#define SMSC_RX_STAT_COLLISION (0x1UL << 6)
113#define SMSC_RX_STAT_FRM_TYPE (0x1UL << 5)
114#define SMSC_RX_STAT_WATCHDOG (0x1UL << 4)
115#define SMSC_RX_STAT_MII_ERROR (0x1UL << 3)
116#define SMSC_RX_STAT_DRIBBLING (0x1UL << 2)
117#define SMSC_RX_STAT_CRC_ERROR (0x1UL << 1)
123#define SMSC_ID_REV 0x000
124#define SMSC_INTR_STATUS 0x008
125#define SMSC_RX_CFG 0x00C
126#define SMSC_TX_CFG 0x010
127#define SMSC_HW_CFG 0x014
128#define SMSC_PM_CTRL 0x020
129#define SMSC_LED_GPIO_CFG 0x024
130#define SMSC_GPIO_CFG 0x028
131#define SMSC_AFC_CFG 0x02C
132#define SMSC_EEPROM_CMD 0x030
133#define SMSC_EEPROM_DATA 0x034
134#define SMSC_BURST_CAP 0x038
135#define SMSC_GPIO_WAKE 0x064
136#define SMSC_INTR_CFG 0x068
137#define SMSC_BULK_IN_DLY 0x06C
138#define SMSC_MAC_CSR 0x100
139#define SMSC_MAC_ADDRH 0x104
140#define SMSC_MAC_ADDRL 0x108
141#define SMSC_HASHH 0x10C
142#define SMSC_HASHL 0x110
143#define SMSC_MII_ADDR 0x114
144#define SMSC_MII_DATA 0x118
145#define SMSC_FLOW 0x11C
146#define SMSC_VLAN1 0x120
147#define SMSC_VLAN2 0x124
148#define SMSC_WUFF 0x128
149#define SMSC_WUCSR 0x12C
150#define SMSC_COE_CTRL 0x130
153#define SMSC_ID_REV_CHIP_ID_MASK 0xFFFF0000UL
154#define SMSC_ID_REV_CHIP_REV_MASK 0x0000FFFFUL
156#define SMSC_RX_FIFO_FLUSH (0x1UL << 0)
158#define SMSC_TX_CFG_ON (0x1UL << 2)
159#define SMSC_TX_CFG_STOP (0x1UL << 1)
160#define SMSC_TX_CFG_FIFO_FLUSH (0x1UL << 0)
162#define SMSC_HW_CFG_BIR (0x1UL << 12)
163#define SMSC_HW_CFG_LEDB (0x1UL << 11)
164#define SMSC_HW_CFG_RXDOFF (0x3UL << 9)
165#define SMSC_HW_CFG_DRP (0x1UL << 6)
166#define SMSC_HW_CFG_MEF (0x1UL << 5)
167#define SMSC_HW_CFG_LRST (0x1UL << 3)
168#define SMSC_HW_CFG_PSEL (0x1UL << 2)
169#define SMSC_HW_CFG_BCE (0x1UL << 1)
170#define SMSC_HW_CFG_SRST (0x1UL << 0)
172#define SMSC_PM_CTRL_PHY_RST (0x1UL << 4)
174#define SMSC_LED_GPIO_CFG_SPD_LED (0x1UL << 24)
175#define SMSC_LED_GPIO_CFG_LNK_LED (0x1UL << 20)
176#define SMSC_LED_GPIO_CFG_FDX_LED (0x1UL << 16)
182#define AFC_CFG_DEFAULT (0x00F830A1)
184#define SMSC_EEPROM_CMD_BUSY (0x1UL << 31)
185#define SMSC_EEPROM_CMD_MASK (0x7UL << 28)
186#define SMSC_EEPROM_CMD_READ (0x0UL << 28)
187#define SMSC_EEPROM_CMD_WRITE (0x3UL << 28)
188#define SMSC_EEPROM_CMD_ERASE (0x5UL << 28)
189#define SMSC_EEPROM_CMD_RELOAD (0x7UL << 28)
190#define SMSC_EEPROM_CMD_TIMEOUT (0x1UL << 10)
191#define SMSC_EEPROM_CMD_ADDR_MASK 0x000001FFUL
194#define SMSC_MAC_CSR_RCVOWN (0x1UL << 23)
195#define SMSC_MAC_CSR_LOOPBK (0x1UL << 21)
196#define SMSC_MAC_CSR_FDPX (0x1UL << 20)
197#define SMSC_MAC_CSR_MCPAS (0x1UL << 19)
198#define SMSC_MAC_CSR_PRMS (0x1UL << 18)
199#define SMSC_MAC_CSR_INVFILT (0x1UL << 17)
200#define SMSC_MAC_CSR_PASSBAD (0x1UL << 16)
201#define SMSC_MAC_CSR_HPFILT (0x1UL << 13)
202#define SMSC_MAC_CSR_BCAST (0x1UL << 11)
203#define SMSC_MAC_CSR_TXEN (0x1UL << 3)
204#define SMSC_MAC_CSR_RXEN (0x1UL << 2)
207#define SMSC_INTR_NTEP (0x1UL << 31)
208#define SMSC_INTR_MACRTO (0x1UL << 19)
209#define SMSC_INTR_TX_STOP (0x1UL << 17)
210#define SMSC_INTR_RX_STOP (0x1UL << 16)
211#define SMSC_INTR_PHY_INT (0x1UL << 15)
212#define SMSC_INTR_TXE (0x1UL << 14)
213#define SMSC_INTR_TDFU (0x1UL << 13)
214#define SMSC_INTR_TDFO (0x1UL << 12)
215#define SMSC_INTR_RXDF (0x1UL << 11)
216#define SMSC_INTR_GPIOS 0x000007FFUL
219#define SMSC_MII_WRITE (0x1UL << 1)
220#define SMSC_MII_READ (0x0UL << 1)
221#define SMSC_MII_BUSY (0x1UL << 0)
224#define SMSC_COE_CTRL_TX_EN (0x1UL << 16)
225#define SMSC_COE_CTRL_RX_MODE (0x1UL << 1)
226#define SMSC_COE_CTRL_RX_EN (0x1UL << 0)
229#define SMSC_PHY_INTR_STAT (29)
230#define SMSC_PHY_INTR_MASK (30)
232#define SMSC_PHY_INTR_ENERGY_ON (0x1U << 7)
233#define SMSC_PHY_INTR_ANEG_COMP (0x1U << 6)
234#define SMSC_PHY_INTR_REMOTE_FAULT (0x1U << 5)
235#define SMSC_PHY_INTR_LINK_DOWN (0x1U << 4)
238#define SMSC_UR_WRITE_REG 0xA0
239#define SMSC_UR_READ_REG 0xA1
240#define SMSC_UR_GET_STATS 0xA2
242#define SMSC_CONFIG_INDEX 0
243#define SMSC_IFACE_IDX 0
271#define SMSC_FLAG_LINK 0x0001
272#define SMSC_FLAG_LAN9514 0x1000
275#define SMSC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
276#define SMSC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
277#define SMSC_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)
struct usb_xfer * sc_xfer[SMSC_N_TRANSFER]