mss.h File Reference
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Data Structures | |
| struct | mixer_def |
Macros | |
| #define | MIX_ENT(name, reg_l, pol_l, pos_l, len_l, reg_r, pol_r, pos_r, len_r) {{reg_l, pol_l, pos_l, len_l}, {reg_r, pol_r, pos_r, len_r}} |
| #define | PMIX_ENT(name, reg_l, pos_l, len_l, reg_r, pos_r, len_r) {{reg_l, 0, pos_l, len_l}, {reg_r, 0, pos_r, len_r}} |
| #define | MIX_NONE(name) MIX_ENT(name, 0,0,0,0, 0,0,0,0) |
| #define | MSS_INDEX (0 + 4) |
| #define | MSS_IDXBUSY 0x80 /* readonly, set when busy */ |
| #define | MSS_MCE 0x40 /* the MCE bit. */ |
| #define | MSS_TRD 0x20 /* Transfer request disable */ |
| #define | MSS_IDXMASK 0x1f /* mask for indirect address */ |
| #define | MSS_IDATA (1 + 4) |
| #define | MSS_STATUS (2 + 4) |
| #define | IS_CUL 0x80 /* capture upper/lower */ |
| #define | IS_CLR 0x40 /* capture left/right */ |
| #define | IS_CRDY 0x20 /* capture ready for programmed i/o */ |
| #define | IS_SER 0x10 /* sample error (overrun/underrun) */ |
| #define | IS_PUL 0x08 /* playback upper/lower */ |
| #define | IS_PLR 0x04 /* playback left/right */ |
| #define | IS_PRDY 0x02 /* playback ready for programmed i/o */ |
| #define | IS_INT 0x01 /* int status (1 = active) */ |
| #define | I6_MUTE 0x80 |
| #define | I9_PEN 0x01 /* playback enable */ |
| #define | I9_CEN 0x02 /* capture enable */ |
| #define | BD_F_MCE_BIT 0x0001 |
| #define | BD_F_IRQ_OK 0x0002 |
| #define | BD_F_TMR_RUN 0x0004 |
| #define | BD_F_MSS_OFFSET 0x0008 /* offset mss writes by -4 */ |
| #define | BD_F_DUPLEX 0x0010 |
| #define | BD_F_924PNP 0x0020 /* OPTi924 is in PNP mode */ |
| #define | MSS_REC_DEVICES (SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD|SOUND_MASK_IMIX) |
| #define | MODE2_MIXER_DEVICES |
| #define | MODE1_MIXER_DEVICES |
| #define | OPTI930_MIXER_DEVICES |
| #define | OPTI931_MIXER_DEVICES |
| #define | OPL3SAx_POWER 0x01 /* Power Management (R/W) */ |
| #define | OPL3SAx_POWER_PDX 0x01 /* Set to 1 to halt oscillator */ |
| #define | OPL3SAx_POWER_PDN 0x02 /* Set to 1 to power down */ |
| #define | OPL3SAx_POWER_PSV 0x04 /* Set to 1 to power save */ |
| #define | OPL3SAx_POWER_ADOWN 0x20 /* Analog power (?) */ |
| #define | OPL3SAx_SYSTEM 0x02 /* System control (R/W) */ |
| #define | OPL3SAx_SYSTEM_VZE 0x01 /* I2S audio routing */ |
| #define | OPL3SAx_SYSTEM_IDSEL 0x03 /* SB compat version select */ |
| #define | OPL3SAx_SYSTEM_SBHE 0x80 /* 0 for AT bus, 1 for XT bus */ |
| #define | OPL3SAx_IRQCONF 0x03 /* Interrupt configuration (R/W */ |
| #define | OPL3SAx_IRQCONF_WSSA 0x01 /* WSS interrupts through IRQA */ |
| #define | OPL3SAx_IRQCONF_SBA 0x02 /* WSS interrupts through IRQA */ |
| #define | OPL3SAx_IRQCONF_MPUA 0x04 /* WSS interrupts through IRQA */ |
| #define | OPL3SAx_IRQCONF_OPL3A 0x08 /* WSS interrupts through IRQA */ |
| #define | OPL3SAx_IRQCONF_WSSB 0x10 /* WSS interrupts through IRQB */ |
| #define | OPL3SAx_IRQCONF_SBB 0x20 /* WSS interrupts through IRQB */ |
| #define | OPL3SAx_IRQCONF_MPUB 0x40 /* WSS interrupts through IRQB */ |
| #define | OPL3SAx_IRQCONF_OPL3B 0x80 /* WSS interrupts through IRQB */ |
| #define | OPL3SAx_IRQSTATUSA 0x04 /* Interrupt (IRQ-A) Status (RO) */ |
| #define | OPL3SAx_IRQSTATUSB 0x05 /* Interrupt (IRQ-B) Status (RO) */ |
| #define | OPL3SAx_IRQSTATUS_PI 0x01 /* Playback Flag of CODEC */ |
| #define | OPL3SAx_IRQSTATUS_CI 0x02 /* Recording Flag of CODEC */ |
| #define | OPL3SAx_IRQSTATUS_TI 0x04 /* Timer Flag of CODEC */ |
| #define | OPL3SAx_IRQSTATUS_SB 0x08 /* SB compat Playback Interrupt Flag */ |
| #define | OPL3SAx_IRQSTATUS_MPU 0x10 /* MPU401 Interrupt Flag */ |
| #define | OPL3SAx_IRQSTATUS_OPL3 0x20 /* Internal FM Timer Flag */ |
| #define | OPL3SAx_IRQSTATUS_MV 0x40 /* HW Volume Interrupt Flag */ |
| #define | OPL3SAx_IRQSTATUS_PI 0x01 /* Playback Flag of CODEC */ |
| #define | OPL3SAx_IRQSTATUS_CI 0x02 /* Recording Flag of CODEC */ |
| #define | OPL3SAx_IRQSTATUS_TI 0x04 /* Timer Flag of CODEC */ |
| #define | OPL3SAx_IRQSTATUS_SB 0x08 /* SB compat Playback Interrupt Flag */ |
| #define | OPL3SAx_IRQSTATUS_MPU 0x10 /* MPU401 Interrupt Flag */ |
| #define | OPL3SAx_IRQSTATUS_OPL3 0x20 /* Internal FM Timer Flag */ |
| #define | OPL3SAx_IRQSTATUS_MV 0x40 /* HW Volume Interrupt Flag */ |
| #define | OPL3SAx_DMACONF 0x06 /* DMA configuration (R/W) */ |
| #define | OPL3SAx_DMACONF_WSSPA 0x01 /* WSS Playback on DMA-A */ |
| #define | OPL3SAx_DMACONF_WSSRA 0x02 /* WSS Recording on DMA-A */ |
| #define | OPL3SAx_DMACONF_SBA 0x02 /* SB Playback on DMA-A */ |
| #define | OPL3SAx_DMACONF_WSSPB 0x10 /* WSS Playback on DMA-A */ |
| #define | OPL3SAx_DMACONF_WSSRB 0x20 /* WSS Recording on DMA-A */ |
| #define | OPL3SAx_DMACONF_SBB 0x20 /* SB Playback on DMA-A */ |
| #define | OPL3SAx_VOLUMEL 0x07 /* Master Volume Left (R/W) */ |
| #define | OPL3SAx_VOLUMEL_MVL 0x0f /* Attenuation level */ |
| #define | OPL3SAx_VOLUMEL_MVLM 0x80 /* Mute */ |
| #define | OPL3SAx_VOLUMER 0x08 /* Master Volume Right (R/W) */ |
| #define | OPL3SAx_VOLUMER_MVR 0x0f /* Attenuation level */ |
| #define | OPL3SAx_VOLUMER_MVRM 0x80 /* Mute */ |
| #define | OPL3SAx_MIC 0x09 /* MIC Volume (R/W) */ |
| #define | OPL3SAx_VOLUMER_MCV 0x1f /* Attenuation level */ |
| #define | OPL3SAx_VOLUMER_MICM 0x80 /* Mute */ |
| #define | OPL3SAx_MISC 0x0a /* Miscellaneous */ |
| #define | OPL3SAx_MISC_VER 0x07 /* Version */ |
| #define | OPL3SAx_MISC_MODE 0x08 /* SB or WSS mode */ |
| #define | OPL3SAx_MISC_MCSW 0x10 /* */ |
| #define | OPL3SAx_MISC_VEN 0x80 /* Enable hardware volume control */ |
| #define | OPL3SAx_WSSDMA 0x0b /* WSS DMA Counter (RW) (4 regs) */ |
| #define | OPL3SAx_WSSIRQSCAN 0x0f /* WSS Interrupt Scan out/in (R/W) */ |
| #define | OPL3SAx_WSSIRQSCAN_SPI 0x01 |
| #define | OPL3SAx_WSSIRQSCAN_SCI 0x02 |
| #define | OPL3SAx_WSSIRQSCAN_STI 0x04 |
| #define | OPL3SAx_SBSTATE 0x10 /* SB compat Internal State (R/W) */ |
| #define | OPL3SAx_SBSTATE_SBPDR 0x01 /* SB Power Down Request */ |
| #define | OPL3SAx_SBSTATE_SE 0x02 /* Scan Enable */ |
| #define | OPL3SAx_SBSTATE_SM 0x04 /* Scan Mode */ |
| #define | OPL3SAx_SBSTATE_SS 0x08 /* Scan Select */ |
| #define | OPL3SAx_SBSTATE_SBPDA 0x80 /* SB Power Down Acknowledge */ |
| #define | OPL3SAx_SBDATA 0x11 /* SB compat State Scan Data (R/W) */ |
| #define | OPL3SAx_DIGITALPOWER 0x12 /* Digital Partial Power Down (R/W) */ |
| #define | OPL3SAx_DIGITALPOWER_PnP 0x01 |
| #define | OPL3SAx_DIGITALPOWER_SB 0x02 |
| #define | OPL3SAx_DIGITALPOWER_WSSP 0x04 |
| #define | OPL3SAx_DIGITALPOWER_WSSR 0x08 |
| #define | OPL3SAx_DIGITALPOWER_FM 0x10 |
| #define | OPL3SAx_DIGITALPOWER_MCLK0 0x20 |
| #define | OPL3SAx_DIGITALPOWER_MPU 0x40 |
| #define | OPL3SAx_DIGITALPOWER_JOY 0x80 |
| #define | OPL3SAx_ANALOGPOWER 0x13 /* Analog Partial Power Down (R/W) */ |
| #define | OPL3SAx_ANALOGPOWER_WIDE 0x01 |
| #define | OPL3SAx_ANALOGPOWER_SBDAC 0x02 |
| #define | OPL3SAx_ANALOGPOWER_DA 0x04 |
| #define | OPL3SAx_ANALOGPOWER_AD 0x08 |
| #define | OPL3SAx_ANALOGPOWER_FMDAC 0x10 |
| #define | OPL3SAx_WIDE 0x14 /* Enhanced control(WIDE) (R/W) */ |
| #define | OPL3SAx_WIDE_WIDEL 0x07 /* Wide level on Left Channel */ |
| #define | OPL3SAx_WIDE_WIDER 0x70 /* Wide level on Right Channel */ |
| #define | OPL3SAx_BASS 0x15 /* Enhanced control(BASS) (R/W) */ |
| #define | OPL3SAx_BASS_BASSL 0x07 /* Bass level on Left Channel */ |
| #define | OPL3SAx_BASS_BASSR 0x70 /* Bass level on Right Channel */ |
| #define | OPL3SAx_TREBLE 0x16 /* Enhanced control(TREBLE) (R/W) */ |
| #define | OPL3SAx_TREBLE_TREBLEL 0x07 /* Treble level on Left Channel */ |
| #define | OPL3SAx_TREBLE_TREBLER 0x70 /* Treble level on Right Channel */ |
| #define | OPL3SAx_HWVOL 0x17 /* HW Volume IRQ Configuration (R/W) */ |
| #define | OPL3SAx_HWVOL_IRQA 0x10 /* HW Volume IRQ on IRQ-A */ |
| #define | OPL3SAx_HWVOL_IRQB 0x20 /* HW Volume IRQ on IRQ-B */ |
Typedefs | |
| typedef struct mixer_def | mixer_ent |
| typedef struct mixer_def | mixer_tab[32][2] |
Variables | |
| mixer_ent | mix_devices [32][2] |
| mixer_ent | opti930_devices [32][2] |
| mixer_ent | opti931_devices [32][2] |
Macro Definition Documentation
◆ BD_F_924PNP
◆ BD_F_DUPLEX
◆ BD_F_IRQ_OK
◆ BD_F_MCE_BIT
◆ BD_F_MSS_OFFSET
◆ BD_F_TMR_RUN
◆ I6_MUTE
◆ I9_CEN
◆ I9_PEN
◆ IS_CLR
◆ IS_CRDY
◆ IS_CUL
◆ IS_INT
◆ IS_PLR
◆ IS_PRDY
◆ IS_PUL
◆ IS_SER
◆ MIX_ENT
| #define MIX_ENT | ( | name, | |
| reg_l, | |||
| pol_l, | |||
| pos_l, | |||
| len_l, | |||
| reg_r, | |||
| pol_r, | |||
| pos_r, | |||
| len_r | |||
| ) | {{reg_l, pol_l, pos_l, len_l}, {reg_r, pol_r, pos_r, len_r}} |
◆ MIX_NONE
◆ MODE1_MIXER_DEVICES
| #define MODE1_MIXER_DEVICES |
◆ MODE2_MIXER_DEVICES
| #define MODE2_MIXER_DEVICES |
◆ MSS_IDATA
◆ MSS_IDXBUSY
◆ MSS_IDXMASK
◆ MSS_INDEX
◆ MSS_MCE
◆ MSS_REC_DEVICES
| #define MSS_REC_DEVICES (SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD|SOUND_MASK_IMIX) |
◆ MSS_STATUS
◆ MSS_TRD
◆ OPL3SAx_ANALOGPOWER
| #define OPL3SAx_ANALOGPOWER 0x13 /* Analog Partial Power Down (R/W) */ |
◆ OPL3SAx_ANALOGPOWER_AD
◆ OPL3SAx_ANALOGPOWER_DA
◆ OPL3SAx_ANALOGPOWER_FMDAC
◆ OPL3SAx_ANALOGPOWER_SBDAC
◆ OPL3SAx_ANALOGPOWER_WIDE
◆ OPL3SAx_BASS
◆ OPL3SAx_BASS_BASSL
| #define OPL3SAx_BASS_BASSL 0x07 /* Bass level on Left Channel */ |
◆ OPL3SAx_BASS_BASSR
| #define OPL3SAx_BASS_BASSR 0x70 /* Bass level on Right Channel */ |
◆ OPL3SAx_DIGITALPOWER
| #define OPL3SAx_DIGITALPOWER 0x12 /* Digital Partial Power Down (R/W) */ |
◆ OPL3SAx_DIGITALPOWER_FM
◆ OPL3SAx_DIGITALPOWER_JOY
◆ OPL3SAx_DIGITALPOWER_MCLK0
◆ OPL3SAx_DIGITALPOWER_MPU
◆ OPL3SAx_DIGITALPOWER_PnP
◆ OPL3SAx_DIGITALPOWER_SB
◆ OPL3SAx_DIGITALPOWER_WSSP
◆ OPL3SAx_DIGITALPOWER_WSSR
◆ OPL3SAx_DMACONF
◆ OPL3SAx_DMACONF_SBA
◆ OPL3SAx_DMACONF_SBB
◆ OPL3SAx_DMACONF_WSSPA
| #define OPL3SAx_DMACONF_WSSPA 0x01 /* WSS Playback on DMA-A */ |
◆ OPL3SAx_DMACONF_WSSPB
| #define OPL3SAx_DMACONF_WSSPB 0x10 /* WSS Playback on DMA-A */ |
◆ OPL3SAx_DMACONF_WSSRA
| #define OPL3SAx_DMACONF_WSSRA 0x02 /* WSS Recording on DMA-A */ |
◆ OPL3SAx_DMACONF_WSSRB
| #define OPL3SAx_DMACONF_WSSRB 0x20 /* WSS Recording on DMA-A */ |
◆ OPL3SAx_HWVOL
| #define OPL3SAx_HWVOL 0x17 /* HW Volume IRQ Configuration (R/W) */ |
◆ OPL3SAx_HWVOL_IRQA
◆ OPL3SAx_HWVOL_IRQB
◆ OPL3SAx_IRQCONF
| #define OPL3SAx_IRQCONF 0x03 /* Interrupt configuration (R/W */ |
◆ OPL3SAx_IRQCONF_MPUA
| #define OPL3SAx_IRQCONF_MPUA 0x04 /* WSS interrupts through IRQA */ |
◆ OPL3SAx_IRQCONF_MPUB
| #define OPL3SAx_IRQCONF_MPUB 0x40 /* WSS interrupts through IRQB */ |
◆ OPL3SAx_IRQCONF_OPL3A
| #define OPL3SAx_IRQCONF_OPL3A 0x08 /* WSS interrupts through IRQA */ |
◆ OPL3SAx_IRQCONF_OPL3B
| #define OPL3SAx_IRQCONF_OPL3B 0x80 /* WSS interrupts through IRQB */ |
◆ OPL3SAx_IRQCONF_SBA
| #define OPL3SAx_IRQCONF_SBA 0x02 /* WSS interrupts through IRQA */ |
◆ OPL3SAx_IRQCONF_SBB
| #define OPL3SAx_IRQCONF_SBB 0x20 /* WSS interrupts through IRQB */ |
◆ OPL3SAx_IRQCONF_WSSA
| #define OPL3SAx_IRQCONF_WSSA 0x01 /* WSS interrupts through IRQA */ |
◆ OPL3SAx_IRQCONF_WSSB
| #define OPL3SAx_IRQCONF_WSSB 0x10 /* WSS interrupts through IRQB */ |
◆ OPL3SAx_IRQSTATUS_CI [1/2]
| #define OPL3SAx_IRQSTATUS_CI 0x02 /* Recording Flag of CODEC */ |
◆ OPL3SAx_IRQSTATUS_CI [2/2]
| #define OPL3SAx_IRQSTATUS_CI 0x02 /* Recording Flag of CODEC */ |
◆ OPL3SAx_IRQSTATUS_MPU [1/2]
| #define OPL3SAx_IRQSTATUS_MPU 0x10 /* MPU401 Interrupt Flag */ |
◆ OPL3SAx_IRQSTATUS_MPU [2/2]
| #define OPL3SAx_IRQSTATUS_MPU 0x10 /* MPU401 Interrupt Flag */ |
◆ OPL3SAx_IRQSTATUS_MV [1/2]
| #define OPL3SAx_IRQSTATUS_MV 0x40 /* HW Volume Interrupt Flag */ |
◆ OPL3SAx_IRQSTATUS_MV [2/2]
| #define OPL3SAx_IRQSTATUS_MV 0x40 /* HW Volume Interrupt Flag */ |
◆ OPL3SAx_IRQSTATUS_OPL3 [1/2]
| #define OPL3SAx_IRQSTATUS_OPL3 0x20 /* Internal FM Timer Flag */ |
◆ OPL3SAx_IRQSTATUS_OPL3 [2/2]
| #define OPL3SAx_IRQSTATUS_OPL3 0x20 /* Internal FM Timer Flag */ |
◆ OPL3SAx_IRQSTATUS_PI [1/2]
| #define OPL3SAx_IRQSTATUS_PI 0x01 /* Playback Flag of CODEC */ |
◆ OPL3SAx_IRQSTATUS_PI [2/2]
| #define OPL3SAx_IRQSTATUS_PI 0x01 /* Playback Flag of CODEC */ |
◆ OPL3SAx_IRQSTATUS_SB [1/2]
| #define OPL3SAx_IRQSTATUS_SB 0x08 /* SB compat Playback Interrupt Flag */ |
◆ OPL3SAx_IRQSTATUS_SB [2/2]
| #define OPL3SAx_IRQSTATUS_SB 0x08 /* SB compat Playback Interrupt Flag */ |
◆ OPL3SAx_IRQSTATUS_TI [1/2]
◆ OPL3SAx_IRQSTATUS_TI [2/2]
◆ OPL3SAx_IRQSTATUSA
| #define OPL3SAx_IRQSTATUSA 0x04 /* Interrupt (IRQ-A) Status (RO) */ |
◆ OPL3SAx_IRQSTATUSB
| #define OPL3SAx_IRQSTATUSB 0x05 /* Interrupt (IRQ-B) Status (RO) */ |
◆ OPL3SAx_MIC
◆ OPL3SAx_MISC
◆ OPL3SAx_MISC_MCSW
◆ OPL3SAx_MISC_MODE
◆ OPL3SAx_MISC_VEN
| #define OPL3SAx_MISC_VEN 0x80 /* Enable hardware volume control */ |
◆ OPL3SAx_MISC_VER
◆ OPL3SAx_POWER
◆ OPL3SAx_POWER_ADOWN
◆ OPL3SAx_POWER_PDN
◆ OPL3SAx_POWER_PDX
| #define OPL3SAx_POWER_PDX 0x01 /* Set to 1 to halt oscillator */ |
◆ OPL3SAx_POWER_PSV
◆ OPL3SAx_SBDATA
| #define OPL3SAx_SBDATA 0x11 /* SB compat State Scan Data (R/W) */ |
◆ OPL3SAx_SBSTATE
| #define OPL3SAx_SBSTATE 0x10 /* SB compat Internal State (R/W) */ |
◆ OPL3SAx_SBSTATE_SBPDA
| #define OPL3SAx_SBSTATE_SBPDA 0x80 /* SB Power Down Acknowledge */ |
◆ OPL3SAx_SBSTATE_SBPDR
| #define OPL3SAx_SBSTATE_SBPDR 0x01 /* SB Power Down Request */ |
◆ OPL3SAx_SBSTATE_SE
◆ OPL3SAx_SBSTATE_SM
◆ OPL3SAx_SBSTATE_SS
◆ OPL3SAx_SYSTEM
◆ OPL3SAx_SYSTEM_IDSEL
| #define OPL3SAx_SYSTEM_IDSEL 0x03 /* SB compat version select */ |
◆ OPL3SAx_SYSTEM_SBHE
◆ OPL3SAx_SYSTEM_VZE
◆ OPL3SAx_TREBLE
| #define OPL3SAx_TREBLE 0x16 /* Enhanced control(TREBLE) (R/W) */ |
◆ OPL3SAx_TREBLE_TREBLEL
| #define OPL3SAx_TREBLE_TREBLEL 0x07 /* Treble level on Left Channel */ |
◆ OPL3SAx_TREBLE_TREBLER
| #define OPL3SAx_TREBLE_TREBLER 0x70 /* Treble level on Right Channel */ |
◆ OPL3SAx_VOLUMEL
◆ OPL3SAx_VOLUMEL_MVL
◆ OPL3SAx_VOLUMEL_MVLM
◆ OPL3SAx_VOLUMER
◆ OPL3SAx_VOLUMER_MCV
◆ OPL3SAx_VOLUMER_MICM
◆ OPL3SAx_VOLUMER_MVR
◆ OPL3SAx_VOLUMER_MVRM
◆ OPL3SAx_WIDE
◆ OPL3SAx_WIDE_WIDEL
| #define OPL3SAx_WIDE_WIDEL 0x07 /* Wide level on Left Channel */ |
◆ OPL3SAx_WIDE_WIDER
| #define OPL3SAx_WIDE_WIDER 0x70 /* Wide level on Right Channel */ |
◆ OPL3SAx_WSSDMA
| #define OPL3SAx_WSSDMA 0x0b /* WSS DMA Counter (RW) (4 regs) */ |
◆ OPL3SAx_WSSIRQSCAN
| #define OPL3SAx_WSSIRQSCAN 0x0f /* WSS Interrupt Scan out/in (R/W) */ |
◆ OPL3SAx_WSSIRQSCAN_SCI
◆ OPL3SAx_WSSIRQSCAN_SPI
◆ OPL3SAx_WSSIRQSCAN_STI
◆ OPTI930_MIXER_DEVICES
| #define OPTI930_MIXER_DEVICES |
◆ OPTI931_MIXER_DEVICES
| #define OPTI931_MIXER_DEVICES |
◆ PMIX_ENT
| #define PMIX_ENT | ( | name, | |
| reg_l, | |||
| pos_l, | |||
| len_l, | |||
| reg_r, | |||
| pos_r, | |||
| len_r | |||
| ) | {{reg_l, 0, pos_l, len_l}, {reg_r, 0, pos_r, len_r}} |
Typedef Documentation
◆ mixer_ent
◆ mixer_tab
Variable Documentation
◆ mix_devices
| mixer_ent mix_devices[32][2] |
Initial value:
= {
MIX_NONE(SOUND_MIXER_VOLUME),
MIX_NONE(SOUND_MIXER_BASS),
MIX_NONE(SOUND_MIXER_TREBLE),
MIX_ENT(SOUND_MIXER_SYNTH, 2, 1, 0, 5, 3, 1, 0, 5),
MIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 6, 7, 1, 0, 6),
MIX_ENT(SOUND_MIXER_SPEAKER, 26, 1, 0, 4, 0, 0, 0, 0),
MIX_ENT(SOUND_MIXER_LINE, 18, 1, 0, 5, 19, 1, 0, 5),
MIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1),
MIX_ENT(SOUND_MIXER_CD, 4, 1, 0, 5, 5, 1, 0, 5),
MIX_ENT(SOUND_MIXER_IMIX, 13, 1, 2, 6, 0, 0, 0, 0),
MIX_NONE(SOUND_MIXER_ALTPCM),
MIX_NONE(SOUND_MIXER_RECLEV),
MIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4),
MIX_NONE(SOUND_MIXER_OGAIN),
MIX_NONE(SOUND_MIXER_LINE1),
MIX_NONE(SOUND_MIXER_LINE2),
MIX_NONE(SOUND_MIXER_LINE3),
}
Definition at line 215 of file mss.h.
Referenced by mss_mixer_set().
◆ opti930_devices
| mixer_ent opti930_devices[32][2] |
Initial value:
= {
MIX_ENT(SOUND_MIXER_VOLUME, 22, 1, 0, 4, 23, 1, 0, 4),
MIX_NONE(SOUND_MIXER_BASS),
MIX_NONE(SOUND_MIXER_TREBLE),
MIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 0, 4, 5, 1, 0, 4),
MIX_ENT(SOUND_MIXER_PCM, 6, 1, 1, 5, 7, 1, 1, 5),
MIX_ENT(SOUND_MIXER_LINE, 18, 1, 1, 4, 19, 1, 1, 4),
MIX_NONE(SOUND_MIXER_SPEAKER),
MIX_ENT(SOUND_MIXER_MIC, 21, 1, 0, 4, 22, 1, 0, 4),
MIX_ENT(SOUND_MIXER_CD, 2, 1, 1, 4, 3, 1, 1, 4),
MIX_NONE(SOUND_MIXER_IMIX),
MIX_NONE(SOUND_MIXER_ALTPCM),
MIX_NONE(SOUND_MIXER_RECLEV),
MIX_NONE(SOUND_MIXER_IGAIN),
MIX_NONE(SOUND_MIXER_OGAIN),
MIX_NONE(SOUND_MIXER_LINE1),
MIX_NONE(SOUND_MIXER_LINE2),
MIX_NONE(SOUND_MIXER_LINE3),
}
Definition at line 244 of file mss.h.
Referenced by mss_mixer_set().
◆ opti931_devices
| mixer_ent opti931_devices[32][2] |
Initial value:
= {
MIX_ENT(SOUND_MIXER_VOLUME, 22, 1, 1, 5, 23, 1, 1, 5),
MIX_NONE(SOUND_MIXER_BASS),
MIX_NONE(SOUND_MIXER_TREBLE),
MIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 1, 4, 5, 1, 1, 4),
MIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 5, 7, 1, 0, 5),
MIX_NONE(SOUND_MIXER_SPEAKER),
MIX_ENT(SOUND_MIXER_LINE, 18, 1, 1, 4, 19, 1, 1, 4),
MIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1),
MIX_ENT(SOUND_MIXER_CD, 2, 1, 1, 4, 3, 1, 1, 4),
MIX_NONE(SOUND_MIXER_IMIX),
MIX_NONE(SOUND_MIXER_ALTPCM),
MIX_NONE(SOUND_MIXER_RECLEV),
MIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4),
MIX_NONE(SOUND_MIXER_OGAIN),
MIX_ENT(SOUND_MIXER_LINE1, 16, 1, 1, 4, 17, 1, 1, 4),
MIX_NONE(SOUND_MIXER_LINE2),
MIX_NONE(SOUND_MIXER_LINE3),
}
Definition at line 272 of file mss.h.
Referenced by mss_mixer_set().
