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Macros
#define	PCIV_ENVY24 0x1412

#define	PCID_ENVY24 0x1712

#define	PCIR_CCS 0x10 /* Controller I/O Base Address */

#define	PCIR_DDMA 0x14 /* DDMA I/O Base Address */

#define	PCIR_DS 0x18 /* DMA Path Registers I/O Base Address */

#define	PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */

#define	PCIR_LAC 0x40 /* Legacy Audio Control */

#define	PCIM_LAC_DISABLE 0x8000 /* Legacy Audio Hardware disabled */

#define	PCIM_LAC_SBDMA0 0x0000 /* SB DMA Channel Select: 0 */

#define	PCIM_LAC_SBDMA1 0x0040 /* SB DMA Channel Select: 1 */

#define	PCIM_LAC_SBDMA3 0x00c0 /* SB DMA Channel Select: 3 */

#define	PCIM_LAC_IOADDR10 0x0020 /* I/O Address Alias Control */

#define	PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */

#define	PCIM_LAC_GAME 0x0004 /* Game Port enable (200h) */

#define	PCIM_LAC_FM 0x0002 /* FM I/O enable (AdLib 388h base) */

#define	PCIM_LAC_SB 0x0001 /* SB I/O enable */

#define	PCIR_LCC 0x42 /* Legacy Configuration Control */

#define	PCIM_LCC_VINT 0xff00 /* Interrupt vector to be snooped */

#define	PCIM_LCC_SVIDRW 0x0080 /* SVID read/write enable */

#define	PCIM_LCC_SNPSB 0x0040 /* snoop SB 22C/24Ch I/O write cycle */

#define	PCIM_LCC_SNPPIC 0x0020 /* snoop PIC I/O R/W cycle */

#define	PCIM_LCC_SNPPCI 0x0010 /* snoop PCI bus interrupt acknowledge cycle */

#define	PCIM_LCC_SBBASE 0x0008 /* SB base 240h(1)/220h(0) */

#define	PCIM_LCC_MPUBASE 0x0006 /* MPU-401 base 300h-330h */

#define	PCIM_LCC_LDMA 0x0001 /* Legacy DMA enable */

#define	PCIR_SCFG 0x60 /* System Configuration Register */

#define	PCIM_SCFG_XIN2 0xc0 /* XIN2 Clock Source Configuration */

#define	PCIM_SCFG_MPU 0x20 /* 1(0)/2(1) MPU-401 UART(s) */

#define	PCIM_SCFG_AC97 0x10 /* 0: AC'97 codec exist */

#define	PCIM_SCFG_ADC 0x0c /* 1-4 stereo ADC connected */

#define	PCIM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */

#define	PCIR_ACL 0x61 /* AC-Link Configuration Register */

#define	PCIM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */

#define	PCIM_ACL_OMODE 0x02 /* AC 97 codec SDATA_OUT 0:split 1:packed */

#define	PCIM_ACL_IMODE 0x01 /* AC 97 codec SDATA_IN 0:split 1:packed */

#define	PCIR_I2S 0x62 /* I2S Converters Features Register */

#define	PCIM_I2S_VOL 0x80 /* I2S codec Volume and mute */

#define	PCIM_I2S_96KHZ 0x40 /* I2S converter 96kHz sampling rate support */

#define	PCIM_I2S_RES 0x30 /* Converter resolution */

#define	PCIM_I2S_16BIT 0x00 /* 16bit */

#define	PCIM_I2S_18BIT 0x10 /* 18bit */

#define	PCIM_I2S_20BIT 0x20 /* 20bit */

#define	PCIM_I2S_24BIT 0x30 /* 24bit */

#define	PCIM_I2S_ID 0x0f /* Other I2S IDs */

#define	PCIR_SPDIF 0x63 /* S/PDIF Configuration Register */

#define	PCIM_SPDIF_ID 0xfc /* S/PDIF chip ID */

#define	PCIM_SPDIF_IN 0x02 /* S/PDIF Stereo In is present */

#define	PCIM_SPDIF_OUT 0x01 /* S/PDIF Stereo Out is present */

#define	PCIR_POWER_STAT 0x84 /* Power Management Control and Status */

#define	ENVY24_CCS_CTL 0x00 /* Control/Status Register */

#define	ENVY24_CCS_CTL_RESET 0x80 /* Entire Chip soft reset */

#define	ENVY24_CCS_CTL_DMAINT 0x40 /* DS DMA Channel-C interrupt */

#define	ENVY24_CCS_CTL_DOSVOL 0x10 /* set the DOS WT volume control */

#define	ENVY24_CCS_CTL_EDGE 0x08 /* SERR# edge (only one PCI clock width) */

#define	ENVY24_CCS_CTL_SBINT 0x02 /* SERR# assertion for SB interrupt */

#define	ENVY24_CCS_CTL_NATIVE 0x01 /* Mode select: 0:SB mode 1:native mode */

#define	ENVY24_CCS_IMASK 0x01 /* Interrupt Mask Register */

#define	ENVY24_CCS_IMASK_PMIDI 0x80 /* Primary MIDI */

#define	ENVY24_CCS_IMASK_TIMER 0x40 /* Timer */

#define	ENVY24_CCS_IMASK_SMIDI 0x20 /* Secondary MIDI */

#define	ENVY24_CCS_IMASK_PMT 0x10 /* Professional Multi-track */

#define	ENVY24_CCS_IMASK_FM 0x08 /* FM/MIDI trapping */

#define	ENVY24_CCS_IMASK_PDMA 0x04 /* Playback DS DMA */

#define	ENVY24_CCS_IMASK_RDMA 0x02 /* Consumer record DMA */

#define	ENVY24_CCS_IMASK_SB 0x01 /* Consumer/SB mode playback */

#define	ENVY24_CCS_ISTAT 0x02 /* Interrupt Status Register */

#define	ENVY24_CCS_ISTAT_PMIDI 0x80 /* Primary MIDI */

#define	ENVY24_CCS_ISTAT_TIMER 0x40 /* Timer */

#define	ENVY24_CCS_ISTAT_SMIDI 0x20 /* Secondary MIDI */

#define	ENVY24_CCS_ISTAT_PMT 0x10 /* Professional Multi-track */

#define	ENVY24_CCS_ISTAT_FM 0x08 /* FM/MIDI trapping */

#define	ENVY24_CCS_ISTAT_PDMA 0x04 /* Playback DS DMA */

#define	ENVY24_CCS_ISTAT_RDMA 0x02 /* Consumer record DMA */

#define	ENVY24_CCS_ISTAT_SB 0x01 /* Consumer/SB mode playback */

#define	ENVY24_CCS_INDEX 0x03 /* Envy24 Index Register */

#define	ENVY24_CCS_DATA 0x04 /* Envy24 Data Register */

#define	ENVY24_CCS_NMI1 0x05 /* NMI Status Register 1 */

#define	ENVY24_CCS_NMI1_PCI 0x80 /* PCI I/O read/write cycle */

#define	ENVY24_CCS_NMI1_SB 0x40 /* SB 22C/24C write */

#define	ENVY24_CCS_NMI1_SBDMA 0x10 /* SB interrupt (SB DMA/SB F2 command) */

#define	ENVY24_CCS_NMI1_DSDMA 0x08 /* DS channel C DMA interrupt */

#define	ENVY24_CCS_NMI1_MIDI 0x04 /* MIDI 330h or [PCI_10]h+Ch write */

#define	ENVY24_CCS_NMI1_FM 0x01 /* FM data register write */

#define	ENVY24_CCS_NMIDAT 0x06 /* NMI Data Register */

#define	ENVY24_CCS_NMIIDX 0x07 /* NMI Index Register */

#define	ENVY24_CCS_AC97IDX 0x08 /* Consumer AC'97 Index Register */

#define	ENVY24_CCS_AC97CMD 0x09 /* Consumer AC'97 Command/Status Register */

#define	ENVY24_CCS_AC97CMD_COLD 0x80 /* Cold reset */

#define	ENVY24_CCS_AC97CMD_WARM 0x40 /* Warm reset */

#define	ENVY24_CCS_AC97CMD_WRCODEC 0x20 /* Write to AC'97 codec registers */

#define	ENVY24_CCS_AC97CMD_RDCODEC 0x10 /* Read from AC'97 codec registers */

#define	ENVY24_CCS_AC97CMD_READY 0x08 /* AC'97 codec ready status bit */

#define	ENVY24_CCS_AC97CMD_PVSR 0x02 /* VSR for Playback */

#define	ENVY24_CCS_AC97CMD_RVSR 0x01 /* VSR for Record */

#define	ENVY24_CCS_AC97DAT 0x0a /* Consumer AC'97 Data Port Register */

#define	ENVY24_CCS_PMIDIDAT 0x0c /* Primary MIDI UART Data Register */

#define	ENVY24_CCS_PMIDICMD 0x0d /* Primary MIDI UART Command/Status Register */

#define	ENVY24_CCS_NMI2 0x0e /* NMI Status Register 2 */

#define	ENVY24_CCS_NMI2_FMBANK 0x30 /* FM bank indicator */

#define	ENVY24_CCS_NMI2_FM0 0x10 /* FM bank 0 (388h/220h/228h) */

#define	ENVY24_CCS_NMI2_FM1 0x20 /* FM bank 1 (38ah/222h) */

#define	ENVY24_CCS_NMI2_PICIO 0x0f /* PIC I/O cycle */

#define	ENVY24_CCS_NMI2_PIC20W 0x01 /* 20h write */

#define	ENVY24_CCS_NMI2_PICA0W 0x02 /* a0h write */

#define	ENVY24_CCS_NMI2_PIC21W 0x05 /* 21h write */

#define	ENVY24_CCS_NMI2_PICA1W 0x06 /* a1h write */

#define	ENVY24_CCS_NMI2_PIC20R 0x09 /* 20h read */

#define	ENVY24_CCS_NMI2_PICA0R 0x0a /* a0h read */

#define	ENVY24_CCS_NMI2_PIC21R 0x0d /* 21h read */

#define	ENVY24_CCS_NMI2_PICA1R 0x0e /* a1h read */

#define	ENVY24_CCS_JOY 0x0f /* Game port register */

#define	ENVY24_CCS_I2CDEV 0x10 /* I2C Port Device Address Register */

#define	ENVY24_CCS_I2CDEV_ADDR 0xfe /* I2C device address */

#define	ENVY24_CCS_I2CDEV_ROM 0xa0 /* reserved for the external I2C E2PROM */

#define	ENVY24_CCS_I2CDEV_WR 0x01 /* write */

#define	ENVY24_CCS_I2CDEV_RD 0x00 /* read */

#define	ENVY24_CCS_I2CADDR 0x11 /* I2C Port Byte Address Register */

#define	ENVY24_CCS_I2CDATA 0x12 /* I2C Port Read/Write Data Register */

#define	ENVY24_CCS_I2CSTAT 0x13 /* I2C Port Control and Status Register */

#define	ENVY24_CCS_I2CSTAT_ROM 0x80 /* external E2PROM exists */

#define	ENVY24_CCS_I2CSTAT_BSY 0x01 /* I2C port read/write status busy */

#define	ENVY24_CCS_CDMABASE 0x14 /* Consumer Record DMA Current/Base Address Register */

#define	ENVY24_CCS_CDMACNT 0x18 /* Consumer Record DMA Current/Base Count Register */

#define	ENVY24_CCS_SERR 0x1b /* PCI Configuration SERR# Shadow Register */

#define	ENVY24_CCS_SMIDIDAT 0x1c /* Secondary MIDI UART Data Register */

#define	ENVY24_CCS_SMIDICMD 0x1d /* Secondary MIDI UART Command/Status Register */

#define	ENVY24_CCS_TIMER 0x1e /* Timer Register */

#define	ENVY24_CCS_TIMER_EN 0x8000 /* Timer count enable */

#define	ENVY24_CCS_TIMER_MASK 0x7fff /* Timer counter mask */

#define	ENVY24_CCI_PTCHIGH 0x00 /* Playback Terminal Count Register (High Byte) */

#define	ENVY24_CCI_PTCLOW 0x01 /* Playback Terminal Count Register (Low Byte) */

#define	ENVY24_CCI_PCTL 0x02 /* Playback Control Register */

#define	ENVY24_CCI_PCTL_TURBO 0x80 /* 4x up sampling in the host by software */

#define	ENVY24_CCI_PCTL_U8 0x10 /* 8 bits unsigned */

#define	ENVY24_CCI_PCTL_S16 0x00 /* 16 bits signed */

#define	ENVY24_CCI_PCTL_STEREO 0x08 /* stereo */

#define	ENVY24_CCI_PCTL_MONO 0x00 /* mono */

#define	ENVY24_CCI_PCTL_FLUSH 0x04 /* FIFO flush (sticky bit. Requires toggling) */

#define	ENVY24_CCI_PCTL_PAUSE 0x02 /* Pause */

#define	ENVY24_CCI_PCTL_ENABLE 0x01 /* Playback enable */

#define	ENVY24_CCI_PLVOL 0x03 /* Playback Left Volume/Pan Register */

#define	ENVY24_CCI_PRVOL 0x04 /* Playback Right Volume/Pan Register */

#define	ENVY24_CCI_VOL_MASK 0x3f /* Volume value mask */

#define	ENVY24_CCI_SOFTVOL 0x05 /* Soft Volume/Mute Control Register */

#define	ENVY24_CCI_PSRLOW 0x06 /* Playback Sampling Rate Register (Low Byte) */

#define	ENVY24_CCI_PSRMID 0x07 /* Playback Sampling Rate Register (Middle Byte) */

#define	ENVY24_CCI_PSRHIGH 0x08 /* Playback Sampling Rate Register (High Byte) */

#define	ENVY24_CCI_RTCHIGH 0x10 /* Record Terminal Count Register (High Byte) */

#define	ENVY24_CCI_RTCLOW 0x11 /* Record Terminal Count Register (Low Byte) */

#define	ENVY24_CCI_RCTL 0x12 /* Record Control Register */

#define	ENVY24_CCI_RCTL_DRTN 0x80 /* Digital return enable */

#define	ENVY24_CCI_RCTL_U8 0x04 /* 8 bits unsigned */

#define	ENVY24_CCI_RCTL_S16 0x00 /* 16 bits signed */

#define	ENVY24_CCI_RCTL_STEREO 0x00 /* stereo */

#define	ENVY24_CCI_RCTL_MONO 0x02 /* mono */

#define	ENVY24_CCI_RCTL_ENABLE 0x01 /* Record enable */

#define	ENVY24_CCI_GPIODAT 0x20 /* GPIO Data Register */

#define	ENVY24_CCI_GPIOMASK 0x21 /* GPIO Write Mask Register */

#define	ENVY24_CCI_GPIOCTL 0x22 /* GPIO Direction Control Register */

#define	ENVY24_CCI_GPIO_OUT 1 /* output */

#define	ENVY24_CCI_GPIO_IN 0 /* input */

#define	ENVY24_CCI_CPDWN 0x30 /* Consumer Section Power Down Register */

#define	ENVY24_CCI_CPDWN_XTAL 0x80 /* Crystal clock generation power down for XTAL_1 */

#define	ENVY24_CCI_CPDWN_GAME 0x40 /* Game port analog power down */

#define	ENVY24_CCI_CPDWN_I2C 0x10 /* I2C port clock */

#define	ENVY24_CCI_CPDWN_MIDI 0x08 /* MIDI clock */

#define	ENVY24_CCI_CPDWN_AC97 0x04 /* AC'97 clock */

#define	ENVY24_CCI_CPDWN_DS 0x02 /* DS Block clock */

#define	ENVY24_CCI_CPDWN_PCI 0x01 /* PCI clock for SB, DMA controller */

#define	ENVY24_CCI_MTPDWN 0x31 /* Multi-Track Section Power Down Register */

#define	ENVY24_CCI_MTPDWN_XTAL 0x80 /* Crystal clock generation power down for XTAL_2 */

#define	ENVY24_CCI_MTPDWN_SPDIF 0x04 /* S/PDIF clock */

#define	ENVY24_CCI_MTPDWN_MIX 0x02 /* Professional digital mixer clock */

#define	ENVY24_CCI_MTPDWN_I2S 0x01 /* Multi-track I2S serial interface clock */

#define	ENVY24_DDMA_ADDR0 0x00 /* DMA Base and Current Address bit 0-7 */

#define	ENVY24_DDMA_ADDR8 0x01 /* DMA Base and Current Address bit 8-15 */

#define	ENVY24_DDMA_ADDR16 0x02 /* DMA Base and Current Address bit 16-23 */

#define	ENVY24_DDMA_ADDR24 0x03 /* DMA Base and Current Address bit 24-31 */

#define	ENVY24_DDMA_CNT0 0x04 /* DMA Base and Current Count 0-7 */

#define	ENVY24_DDMA_CNT8 0x05 /* DMA Base and Current Count 8-15 */

#define	ENVY24_DDMA_CNT16 0x06 /* (not supported) */

#define	ENVY24_DDMA_CMD 0x08 /* Status and Command */

#define	ENVY24_DDMA_MODE 0x0b /* Mode */

#define	ENVY24_DDMA_RESET 0x0c /* Master reset */

#define	ENVY24_DDMA_CHAN 0x0f /* Channel Mask */

#define	ENVY24_CS_INTMASK 0x00 /* DirectSound DMA Interrupt Mask Register */

#define	ENVY24_CS_INTSTAT 0x02 /* DirectSound DMA Interrupt Status Register */

#define	ENVY24_CS_CHDAT 0x04 /* Channel Data register */

#define	ENVY24_CS_CHIDX 0x08 /* Channel Index Register */

#define	ENVY24_CS_CHIDX_NUM 0xf0 /* Channel number */

#define	ENVY24_CS_CHIDX_ADDR0 0x00 /* Buffer_0 DMA base address */

#define	ENVY24_CS_CHIDX_CNT0 0x01 /* Buffer_0 DMA base count */

#define	ENVY24_CS_CHIDX_ADDR1 0x02 /* Buffer_1 DMA base address */

#define	ENVY24_CS_CHIDX_CNT1 0x03 /* Buffer_1 DMA base count */

#define	ENVY24_CS_CHIDX_CTL 0x04 /* Channel Control and Status register */

#define	ENVY24_CS_CHIDX_RATE 0x05 /* Channel Sampling Rate */

#define	ENVY24_CS_CHIDX_VOL 0x06 /* Channel left and right volume/pan control */

#define	ENVY24_CS_CTL_BUF 0x80 /* indicating that the current active buffer */

#define	ENVY24_CS_CTL_AUTO1 0x40 /* Buffer_1 auto init. enable */

#define	ENVY24_CS_CTL_AUTO0 0x20 /* Buffer_0 auto init. enable */

#define	ENVY24_CS_CTL_FLUSH 0x10 /* Flush FIFO */

#define	ENVY24_CS_CTL_STEREO 0x08 /* stereo(or mono) */

#define	ENVY24_CS_CTL_U8 0x04 /* 8-bit unsigned(or 16-bit signed) */

#define	ENVY24_CS_CTL_PAUSE 0x02 /* DMA request 1:pause */

#define	ENVY24_CS_CTL_START 0x01 /* DMA request 1: start, 0:stop */

#define	ENVY24_CS_VOL_RIGHT 0x3f00

#define	ENVY24_CS_VOL_LEFT 0x003f

#define	ENVY24_MT_INT 0x00 /* DMA Interrupt Mask and Status Register */

#define	ENVY24_MT_INT_RMASK 0x80 /* Multi-track record interrupt mask */

#define	ENVY24_MT_INT_PMASK 0x40 /* Multi-track playback interrupt mask */

#define	ENVY24_MT_INT_RSTAT 0x02 /* Multi-track record interrupt status */

#define	ENVY24_MT_INT_PSTAT 0x01 /* Multi-track playback interrupt status */

#define	ENVY24_MT_RATE 0x01 /* Sampling Rate Select Register */

#define	ENVY24_MT_RATE_SPDIF 0x10 /* S/PDIF input clock as the master */

#define	ENVY24_MT_RATE_48000 0x00

#define	ENVY24_MT_RATE_24000 0x01

#define	ENVY24_MT_RATE_12000 0x02

#define	ENVY24_MT_RATE_9600 0x03

#define	ENVY24_MT_RATE_32000 0x04

#define	ENVY24_MT_RATE_16000 0x05

#define	ENVY24_MT_RATE_8000 0x06

#define	ENVY24_MT_RATE_96000 0x07

#define	ENVY24_MT_RATE_64000 0x0f

#define	ENVY24_MT_RATE_44100 0x08

#define	ENVY24_MT_RATE_22050 0x09

#define	ENVY24_MT_RATE_11025 0x0a

#define	ENVY24_MT_RATE_88200 0x0b

#define	ENVY24_MT_RATE_MASK 0x0f

#define	ENVY24_MT_I2S 0x02 /* I2S Data Format Register */

#define	ENVY24_MT_I2S_MLR128 0x08 /* MCLK/LRCLK ratio 128x(or 256x) */

#define	ENVY24_MT_I2S_SLR48 0x04 /* SCLK/LRCLK ratio 48bpf(or 64bpf) */

#define	ENVY24_MT_I2S_FORM 0x00 /* I2S data format */

#define	ENVY24_MT_AC97IDX 0x04 /* Index Register for AC'97 Codecs */

#define	ENVY24_MT_AC97CMD 0x05 /* Command and Status Register for AC'97 Codecs */

#define	ENVY24_MT_AC97CMD_CLD 0x80 /* Cold reset */

#define	ENVY24_MT_AC97CMD_WRM 0x40 /* Warm reset */

#define	ENVY24_MT_AC97CMD_WR 0x20 /* write to AC'97 codec register */

#define	ENVY24_MT_AC97CMD_RD 0x10 /* read AC'97 CODEC register */

#define	ENVY24_MT_AC97CMD_RDY 0x08 /* AC'97 codec ready status bit */

#define	ENVY24_MT_AC97CMD_ID 0x03 /* ID(0-3) for external AC 97 registers */

#define	ENVY24_MT_AC97DLO 0x06 /* AC'97 codec register data low byte */

#define	ENVY24_MT_AC97DHI 0x07 /* AC'97 codec register data high byte */

#define	ENVY24_MT_PADDR 0x10 /* Playback DMA Current/Base Address Register */

#define	ENVY24_MT_PCNT 0x14 /* Playback DMA Current/Base Count Register */

#define	ENVY24_MT_PTERM 0x16 /* Playback Current/Base Terminal Count Register */

#define	ENVY24_MT_PCTL 0x18 /* Playback and Record Control Register */

#define	ENVY24_MT_PCTL_RSTART 0x04 /* 1: Record start; 0: Record stop */

#define	ENVY24_MT_PCTL_PAUSE 0x02 /* 1: Pause; 0: Resume */

#define	ENVY24_MT_PCTL_PSTART 0x01 /* 1: Playback start; 0: Playback stop */

#define	ENVY24_MT_RADDR 0x20 /* Record DMA Current/Base Address Register */

#define	ENVY24_MT_RCNT 0x24 /* Record DMA Current/Base Count Register */

#define	ENVY24_MT_RTERM 0x26 /* Record Current/Base Terminal Count Register */

#define	ENVY24_MT_RCTL 0x28 /* Record Control Register */

#define	ENVY24_MT_RCTL_RSTART 0x01 /* 1: Record start; 0: Record stop */

#define	ENVY24_MT_PSDOUT 0x30 /* Routing Control Register for Data to PSDOUT[0:3] */

#define	ENVY24_MT_SPDOUT 0x32 /* Routing Control Register for SPDOUT */

#define	ENVY24_MT_RECORD 0x34 /* Captured (Recorded) data Routing Selection Register */

#define	BUS_SPACE_MAXADDR_ENVY24 0x0fffffff /* Address space beyond 256MB is not supported */

#define	BUS_SPACE_MAXSIZE_ENVY24 0x3fffc /* 64k x 4byte(1dword) */

#define	ENVY24_MT_VOLUME 0x38 /* Left/Right Volume Control Data Register */

#define	ENVY24_MT_VOLUME_L 0x007f /* Left Volume Mask */

#define	ENVY24_MT_VOLUME_R 0x7f00 /* Right Volume Mask */

#define	ENVY24_MT_VOLIDX 0x3a /* Volume Control Stream Index Register */

#define	ENVY24_MT_VOLRATE 0x3b /* Volume Control Rate Register */

#define	ENVY24_MT_MONAC97 0x3c /* Digital Mixer Monitor Routing Control Register */

#define	ENVY24_MT_PEAKIDX 0x3e /* Peak Meter Index Register */

#define	ENVY24_MT_PEAKDAT 0x3f /* Peak Meter Data Register */

#define	ENVY24_CHAN_NUM 11 /* Play * 5 + Record * 5 + Mix * 1 */

#define	ENVY24_CHAN_PLAY_DAC1 0

#define	ENVY24_CHAN_PLAY_DAC2 1

#define	ENVY24_CHAN_PLAY_DAC3 2

#define	ENVY24_CHAN_PLAY_DAC4 3

#define	ENVY24_CHAN_PLAY_SPDIF 4

#define	ENVY24_CHAN_REC_ADC1 5

#define	ENVY24_CHAN_REC_ADC2 6

#define	ENVY24_CHAN_REC_ADC3 7

#define	ENVY24_CHAN_REC_ADC4 8

#define	ENVY24_CHAN_REC_SPDIF 9

#define	ENVY24_CHAN_REC_MIX 10

#define	ENVY24_MIX_MASK 0x3ff

#define	ENVY24_MIX_REC_MASK 0x3e0

#define	ENVY24_VOL_MAX 0 /* 0db(negate) */

#define	ENVY24_VOL_MIN 96 /* -144db(negate) */

#define	ENVY24_VOL_MUTE 127 /* mute */

#define	ENVY24_ROUTE_DAC_1 0

#define	ENVY24_ROUTE_DAC_2 1

#define	ENVY24_ROUTE_DAC_3 2

#define	ENVY24_ROUTE_DAC_4 3

#define	ENVY24_ROUTE_DAC_SPDIF 4

#define	ENVY24_ROUTE_CLASS_DMA 0

#define	ENVY24_ROUTE_CLASS_MIX 1

#define	ENVY24_ROUTE_CLASS_ADC 2

#define	ENVY24_ROUTE_CLASS_SPDIF 3

#define	ENVY24_ROUTE_ADC_1 0

#define	ENVY24_ROUTE_ADC_2 1

#define	ENVY24_ROUTE_ADC_3 2

#define	ENVY24_ROUTE_ADC_4 3

#define	ENVY24_ROUTE_NORMAL 0

#define	ENVY24_ROUTE_REVERSE 1

#define	ENVY24_ROUTE_LEFT 0

#define	ENVY24_ROUTE_RIGHT 1

#define	ENVY24_E2PROM_SUBVENDOR 0x00

#define	ENVY24_E2PROM_SUBDEVICE 0x02

#define	ENVY24_E2PROM_SIZE 0x04

#define	ENVY24_E2PROM_VERSION 0x05

#define	ENVY24_E2PROM_SCFG 0x06

#define	ENVY24_E2PROM_ACL 0x07

#define	ENVY24_E2PROM_I2S 0x08

#define	ENVY24_E2PROM_SPDIF 0x09

#define	ENVY24_E2PROM_GPIOMASK 0x0a

#define	ENVY24_E2PROM_GPIOSTATE 0x0b

#define	ENVY24_E2PROM_GPIODIR 0x0c

#define	ENVY24_E2PROM_AC97MAIN 0x0d

#define	ENVY24_E2PROM_AC97PCM 0x0f

#define	ENVY24_E2PROM_AC97REC 0x11

#define	ENVY24_E2PROM_AC97RECSRC 0x13

#define	ENVY24_E2PROM_DACID 0x14

#define	ENVY24_E2PROM_ADCID 0x18

#define	ENVY24_E2PROM_EXTRA 0x1c

#define	ENVY24_GPIO_CS84X4_PRO 0x01

#define	ENVY24_GPIO_CS8414_STATUS 0x02

#define	ENVY24_GPIO_CS84X4_CLK 0x04

#define	ENVY24_GPIO_CS84X4_DATA 0x08

#define	ENVY24_GPIO_AK4524_CDTI 0x10 /* this value is duplicated to input select */

#define	ENVY24_GPIO_AK4524_CCLK 0x20

#define	ENVY24_GPIO_AK4524_CS0 0x40

#define	ENVY24_GPIO_AK4524_CS1 0x80

#define	ENVY24_CS8404_PRO_RATE 0x18

#define	ENVY24_CS8404_PRO_RATE32 0x00

#define	ENVY24_CS8404_PRO_RATE441 0x10

#define	ENVY24_CS8404_PRO_RATE48 0x08

#define	ENVY24_DELTA_AK4524_CIF 0

#define	I2C_DELAY 1000

#define	PCA9554_I2CDEV 0x40 /* I2C device address */

#define	PCA9554_IN 0x00 /* input port */

#define	PCA9554_OUT 0x01 /* output port */

#define	PCA9554_INVERT 0x02 /* polarity invert */

#define	PCA9554_DIR 0x03 /* port directions */

#define	PCF8574_I2CDEV_DAC 0x48

#define	PCF8574_SENSE_MASK 0x40

Macro Definition Documentation

◆ BUS_SPACE_MAXADDR_ENVY24

#define BUS_SPACE_MAXADDR_ENVY24 0x0fffffff /* Address space beyond 256MB is not supported */

Definition at line 353 of file envy24.h.

◆ BUS_SPACE_MAXSIZE_ENVY24

#define BUS_SPACE_MAXSIZE_ENVY24 0x3fffc /* 64k x 4byte(1dword) */

Definition at line 354 of file envy24.h.

◆ ENVY24_CCI_CPDWN

#define ENVY24_CCI_CPDWN 0x30 /* Consumer Section Power Down Register */

Definition at line 236 of file envy24.h.

◆ ENVY24_CCI_CPDWN_AC97

#define ENVY24_CCI_CPDWN_AC97 0x04 /* AC'97 clock */

Definition at line 241 of file envy24.h.

◆ ENVY24_CCI_CPDWN_DS

#define ENVY24_CCI_CPDWN_DS 0x02 /* DS Block clock */

Definition at line 242 of file envy24.h.

◆ ENVY24_CCI_CPDWN_GAME

#define ENVY24_CCI_CPDWN_GAME 0x40 /* Game port analog power down */

Definition at line 238 of file envy24.h.

◆ ENVY24_CCI_CPDWN_I2C

#define ENVY24_CCI_CPDWN_I2C 0x10 /* I2C port clock */

Definition at line 239 of file envy24.h.

◆ ENVY24_CCI_CPDWN_MIDI

#define ENVY24_CCI_CPDWN_MIDI 0x08 /* MIDI clock */

Definition at line 240 of file envy24.h.

◆ ENVY24_CCI_CPDWN_PCI

#define ENVY24_CCI_CPDWN_PCI 0x01 /* PCI clock for SB, DMA controller */

Definition at line 243 of file envy24.h.

◆ ENVY24_CCI_CPDWN_XTAL

#define ENVY24_CCI_CPDWN_XTAL 0x80 /* Crystal clock generation power down for XTAL_1 */

Definition at line 237 of file envy24.h.

◆ ENVY24_CCI_GPIO_IN

#define ENVY24_CCI_GPIO_IN 0 /* input */

Definition at line 234 of file envy24.h.

◆ ENVY24_CCI_GPIO_OUT

#define ENVY24_CCI_GPIO_OUT 1 /* output */

Definition at line 233 of file envy24.h.

◆ ENVY24_CCI_GPIOCTL

#define ENVY24_CCI_GPIOCTL 0x22 /* GPIO Direction Control Register */

Definition at line 232 of file envy24.h.

◆ ENVY24_CCI_GPIODAT

#define ENVY24_CCI_GPIODAT 0x20 /* GPIO Data Register */

Definition at line 229 of file envy24.h.

◆ ENVY24_CCI_GPIOMASK

#define ENVY24_CCI_GPIOMASK 0x21 /* GPIO Write Mask Register */

Definition at line 230 of file envy24.h.

◆ ENVY24_CCI_MTPDWN

#define ENVY24_CCI_MTPDWN 0x31 /* Multi-Track Section Power Down Register */

Definition at line 245 of file envy24.h.

◆ ENVY24_CCI_MTPDWN_I2S

#define ENVY24_CCI_MTPDWN_I2S 0x01 /* Multi-track I2S serial interface clock */

Definition at line 249 of file envy24.h.

◆ ENVY24_CCI_MTPDWN_MIX

#define ENVY24_CCI_MTPDWN_MIX 0x02 /* Professional digital mixer clock */

Definition at line 248 of file envy24.h.

◆ ENVY24_CCI_MTPDWN_SPDIF

#define ENVY24_CCI_MTPDWN_SPDIF 0x04 /* S/PDIF clock */

Definition at line 247 of file envy24.h.

◆ ENVY24_CCI_MTPDWN_XTAL

#define ENVY24_CCI_MTPDWN_XTAL 0x80 /* Crystal clock generation power down for XTAL_2 */

Definition at line 246 of file envy24.h.

◆ ENVY24_CCI_PCTL

#define ENVY24_CCI_PCTL 0x02 /* Playback Control Register */

Definition at line 200 of file envy24.h.

◆ ENVY24_CCI_PCTL_ENABLE

#define ENVY24_CCI_PCTL_ENABLE 0x01 /* Playback enable */

Definition at line 208 of file envy24.h.

◆ ENVY24_CCI_PCTL_FLUSH

#define ENVY24_CCI_PCTL_FLUSH 0x04 /* FIFO flush (sticky bit. Requires toggling) */

Definition at line 206 of file envy24.h.

◆ ENVY24_CCI_PCTL_MONO

#define ENVY24_CCI_PCTL_MONO 0x00 /* mono */

Definition at line 205 of file envy24.h.

◆ ENVY24_CCI_PCTL_PAUSE

#define ENVY24_CCI_PCTL_PAUSE 0x02 /* Pause */

Definition at line 207 of file envy24.h.

◆ ENVY24_CCI_PCTL_S16

#define ENVY24_CCI_PCTL_S16 0x00 /* 16 bits signed */

Definition at line 203 of file envy24.h.

◆ ENVY24_CCI_PCTL_STEREO

#define ENVY24_CCI_PCTL_STEREO 0x08 /* stereo */

Definition at line 204 of file envy24.h.

◆ ENVY24_CCI_PCTL_TURBO

#define ENVY24_CCI_PCTL_TURBO 0x80 /* 4x up sampling in the host by software */

Definition at line 201 of file envy24.h.

◆ ENVY24_CCI_PCTL_U8

#define ENVY24_CCI_PCTL_U8 0x10 /* 8 bits unsigned */

Definition at line 202 of file envy24.h.

◆ ENVY24_CCI_PLVOL

#define ENVY24_CCI_PLVOL 0x03 /* Playback Left Volume/Pan Register */

Definition at line 210 of file envy24.h.

◆ ENVY24_CCI_PRVOL

#define ENVY24_CCI_PRVOL 0x04 /* Playback Right Volume/Pan Register */

Definition at line 211 of file envy24.h.

◆ ENVY24_CCI_PSRHIGH

#define ENVY24_CCI_PSRHIGH 0x08 /* Playback Sampling Rate Register (High Byte) */

Definition at line 217 of file envy24.h.

◆ ENVY24_CCI_PSRLOW

#define ENVY24_CCI_PSRLOW 0x06 /* Playback Sampling Rate Register (Low Byte) */

Definition at line 215 of file envy24.h.

◆ ENVY24_CCI_PSRMID

#define ENVY24_CCI_PSRMID 0x07 /* Playback Sampling Rate Register (Middle Byte) */

Definition at line 216 of file envy24.h.

◆ ENVY24_CCI_PTCHIGH

#define ENVY24_CCI_PTCHIGH 0x00 /* Playback Terminal Count Register (High Byte) */

Definition at line 197 of file envy24.h.

◆ ENVY24_CCI_PTCLOW

#define ENVY24_CCI_PTCLOW 0x01 /* Playback Terminal Count Register (Low Byte) */

Definition at line 198 of file envy24.h.

◆ ENVY24_CCI_RCTL

#define ENVY24_CCI_RCTL 0x12 /* Record Control Register */

Definition at line 221 of file envy24.h.

◆ ENVY24_CCI_RCTL_DRTN

#define ENVY24_CCI_RCTL_DRTN 0x80 /* Digital return enable */

Definition at line 222 of file envy24.h.

◆ ENVY24_CCI_RCTL_ENABLE

#define ENVY24_CCI_RCTL_ENABLE 0x01 /* Record enable */

Definition at line 227 of file envy24.h.

◆ ENVY24_CCI_RCTL_MONO

#define ENVY24_CCI_RCTL_MONO 0x02 /* mono */

Definition at line 226 of file envy24.h.

◆ ENVY24_CCI_RCTL_S16

#define ENVY24_CCI_RCTL_S16 0x00 /* 16 bits signed */

Definition at line 224 of file envy24.h.

◆ ENVY24_CCI_RCTL_STEREO

#define ENVY24_CCI_RCTL_STEREO 0x00 /* stereo */

Definition at line 225 of file envy24.h.

◆ ENVY24_CCI_RCTL_U8

#define ENVY24_CCI_RCTL_U8 0x04 /* 8 bits unsigned */

Definition at line 223 of file envy24.h.

◆ ENVY24_CCI_RTCHIGH

#define ENVY24_CCI_RTCHIGH 0x10 /* Record Terminal Count Register (High Byte) */

Definition at line 218 of file envy24.h.

◆ ENVY24_CCI_RTCLOW

#define ENVY24_CCI_RTCLOW 0x11 /* Record Terminal Count Register (Low Byte) */

Definition at line 219 of file envy24.h.

◆ ENVY24_CCI_SOFTVOL

#define ENVY24_CCI_SOFTVOL 0x05 /* Soft Volume/Mute Control Register */

Definition at line 214 of file envy24.h.

◆ ENVY24_CCI_VOL_MASK

#define ENVY24_CCI_VOL_MASK 0x3f /* Volume value mask */

Definition at line 212 of file envy24.h.

◆ ENVY24_CCS_AC97CMD

#define ENVY24_CCS_AC97CMD 0x09 /* Consumer AC'97 Command/Status Register */

Definition at line 143 of file envy24.h.

◆ ENVY24_CCS_AC97CMD_COLD

#define ENVY24_CCS_AC97CMD_COLD 0x80 /* Cold reset */

Definition at line 144 of file envy24.h.

◆ ENVY24_CCS_AC97CMD_PVSR

#define ENVY24_CCS_AC97CMD_PVSR 0x02 /* VSR for Playback */

Definition at line 149 of file envy24.h.

◆ ENVY24_CCS_AC97CMD_RDCODEC

#define ENVY24_CCS_AC97CMD_RDCODEC 0x10 /* Read from AC'97 codec registers */

Definition at line 147 of file envy24.h.

◆ ENVY24_CCS_AC97CMD_READY

#define ENVY24_CCS_AC97CMD_READY 0x08 /* AC'97 codec ready status bit */

Definition at line 148 of file envy24.h.

◆ ENVY24_CCS_AC97CMD_RVSR

#define ENVY24_CCS_AC97CMD_RVSR 0x01 /* VSR for Record */

Definition at line 150 of file envy24.h.

◆ ENVY24_CCS_AC97CMD_WARM

#define ENVY24_CCS_AC97CMD_WARM 0x40 /* Warm reset */

Definition at line 145 of file envy24.h.

◆ ENVY24_CCS_AC97CMD_WRCODEC

#define ENVY24_CCS_AC97CMD_WRCODEC 0x20 /* Write to AC'97 codec registers */

Definition at line 146 of file envy24.h.

◆ ENVY24_CCS_AC97DAT

#define ENVY24_CCS_AC97DAT 0x0a /* Consumer AC'97 Data Port Register */

Definition at line 152 of file envy24.h.

◆ ENVY24_CCS_AC97IDX

#define ENVY24_CCS_AC97IDX 0x08 /* Consumer AC'97 Index Register */

Definition at line 141 of file envy24.h.

◆ ENVY24_CCS_CDMABASE

#define ENVY24_CCS_CDMABASE 0x14 /* Consumer Record DMA Current/Base Address Register */

Definition at line 185 of file envy24.h.

◆ ENVY24_CCS_CDMACNT

#define ENVY24_CCS_CDMACNT 0x18 /* Consumer Record DMA Current/Base Count Register */

Definition at line 186 of file envy24.h.

◆ ENVY24_CCS_CTL

#define ENVY24_CCS_CTL 0x00 /* Control/Status Register */

Definition at line 100 of file envy24.h.

◆ ENVY24_CCS_CTL_DMAINT

#define ENVY24_CCS_CTL_DMAINT 0x40 /* DS DMA Channel-C interrupt */

Definition at line 102 of file envy24.h.

◆ ENVY24_CCS_CTL_DOSVOL

#define ENVY24_CCS_CTL_DOSVOL 0x10 /* set the DOS WT volume control */

Definition at line 103 of file envy24.h.

◆ ENVY24_CCS_CTL_EDGE

#define ENVY24_CCS_CTL_EDGE 0x08 /* SERR# edge (only one PCI clock width) */

Definition at line 104 of file envy24.h.

◆ ENVY24_CCS_CTL_NATIVE

#define ENVY24_CCS_CTL_NATIVE 0x01 /* Mode select: 0:SB mode 1:native mode */

Definition at line 106 of file envy24.h.

◆ ENVY24_CCS_CTL_RESET

#define ENVY24_CCS_CTL_RESET 0x80 /* Entire Chip soft reset */

Definition at line 101 of file envy24.h.

◆ ENVY24_CCS_CTL_SBINT

#define ENVY24_CCS_CTL_SBINT 0x02 /* SERR# assertion for SB interrupt */

Definition at line 105 of file envy24.h.

◆ ENVY24_CCS_DATA

#define ENVY24_CCS_DATA 0x04 /* Envy24 Data Register */

Definition at line 129 of file envy24.h.

◆ ENVY24_CCS_I2CADDR

#define ENVY24_CCS_I2CADDR 0x11 /* I2C Port Byte Address Register */

Definition at line 178 of file envy24.h.

◆ ENVY24_CCS_I2CDATA

#define ENVY24_CCS_I2CDATA 0x12 /* I2C Port Read/Write Data Register */

Definition at line 179 of file envy24.h.

◆ ENVY24_CCS_I2CDEV

#define ENVY24_CCS_I2CDEV 0x10 /* I2C Port Device Address Register */

Definition at line 172 of file envy24.h.

◆ ENVY24_CCS_I2CDEV_ADDR

#define ENVY24_CCS_I2CDEV_ADDR 0xfe /* I2C device address */

Definition at line 173 of file envy24.h.

◆ ENVY24_CCS_I2CDEV_RD

#define ENVY24_CCS_I2CDEV_RD 0x00 /* read */

Definition at line 176 of file envy24.h.

◆ ENVY24_CCS_I2CDEV_ROM

#define ENVY24_CCS_I2CDEV_ROM 0xa0 /* reserved for the external I2C E2PROM */

Definition at line 174 of file envy24.h.

◆ ENVY24_CCS_I2CDEV_WR

#define ENVY24_CCS_I2CDEV_WR 0x01 /* write */

Definition at line 175 of file envy24.h.

◆ ENVY24_CCS_I2CSTAT

#define ENVY24_CCS_I2CSTAT 0x13 /* I2C Port Control and Status Register */

Definition at line 181 of file envy24.h.

◆ ENVY24_CCS_I2CSTAT_BSY

#define ENVY24_CCS_I2CSTAT_BSY 0x01 /* I2C port read/write status busy */

Definition at line 183 of file envy24.h.

◆ ENVY24_CCS_I2CSTAT_ROM

#define ENVY24_CCS_I2CSTAT_ROM 0x80 /* external E2PROM exists */

Definition at line 182 of file envy24.h.

◆ ENVY24_CCS_IMASK

#define ENVY24_CCS_IMASK 0x01 /* Interrupt Mask Register */

Definition at line 108 of file envy24.h.

◆ ENVY24_CCS_IMASK_FM

#define ENVY24_CCS_IMASK_FM 0x08 /* FM/MIDI trapping */

Definition at line 113 of file envy24.h.

◆ ENVY24_CCS_IMASK_PDMA

#define ENVY24_CCS_IMASK_PDMA 0x04 /* Playback DS DMA */

Definition at line 114 of file envy24.h.

◆ ENVY24_CCS_IMASK_PMIDI

#define ENVY24_CCS_IMASK_PMIDI 0x80 /* Primary MIDI */

Definition at line 109 of file envy24.h.

◆ ENVY24_CCS_IMASK_PMT

#define ENVY24_CCS_IMASK_PMT 0x10 /* Professional Multi-track */

Definition at line 112 of file envy24.h.

◆ ENVY24_CCS_IMASK_RDMA

#define ENVY24_CCS_IMASK_RDMA 0x02 /* Consumer record DMA */

Definition at line 115 of file envy24.h.

◆ ENVY24_CCS_IMASK_SB

#define ENVY24_CCS_IMASK_SB 0x01 /* Consumer/SB mode playback */

Definition at line 116 of file envy24.h.

◆ ENVY24_CCS_IMASK_SMIDI

#define ENVY24_CCS_IMASK_SMIDI 0x20 /* Secondary MIDI */

Definition at line 111 of file envy24.h.

◆ ENVY24_CCS_IMASK_TIMER

#define ENVY24_CCS_IMASK_TIMER 0x40 /* Timer */

Definition at line 110 of file envy24.h.

◆ ENVY24_CCS_INDEX

#define ENVY24_CCS_INDEX 0x03 /* Envy24 Index Register */

Definition at line 128 of file envy24.h.

◆ ENVY24_CCS_ISTAT

#define ENVY24_CCS_ISTAT 0x02 /* Interrupt Status Register */

Definition at line 118 of file envy24.h.

◆ ENVY24_CCS_ISTAT_FM

#define ENVY24_CCS_ISTAT_FM 0x08 /* FM/MIDI trapping */

Definition at line 123 of file envy24.h.

◆ ENVY24_CCS_ISTAT_PDMA

#define ENVY24_CCS_ISTAT_PDMA 0x04 /* Playback DS DMA */

Definition at line 124 of file envy24.h.

◆ ENVY24_CCS_ISTAT_PMIDI

#define ENVY24_CCS_ISTAT_PMIDI 0x80 /* Primary MIDI */

Definition at line 119 of file envy24.h.

◆ ENVY24_CCS_ISTAT_PMT

#define ENVY24_CCS_ISTAT_PMT 0x10 /* Professional Multi-track */

Definition at line 122 of file envy24.h.

◆ ENVY24_CCS_ISTAT_RDMA

#define ENVY24_CCS_ISTAT_RDMA 0x02 /* Consumer record DMA */

Definition at line 125 of file envy24.h.

◆ ENVY24_CCS_ISTAT_SB

#define ENVY24_CCS_ISTAT_SB 0x01 /* Consumer/SB mode playback */

Definition at line 126 of file envy24.h.

◆ ENVY24_CCS_ISTAT_SMIDI

#define ENVY24_CCS_ISTAT_SMIDI 0x20 /* Secondary MIDI */

Definition at line 121 of file envy24.h.

◆ ENVY24_CCS_ISTAT_TIMER

#define ENVY24_CCS_ISTAT_TIMER 0x40 /* Timer */

Definition at line 120 of file envy24.h.

◆ ENVY24_CCS_JOY

#define ENVY24_CCS_JOY 0x0f /* Game port register */

Definition at line 170 of file envy24.h.

◆ ENVY24_CCS_NMI1

#define ENVY24_CCS_NMI1 0x05 /* NMI Status Register 1 */

Definition at line 131 of file envy24.h.

◆ ENVY24_CCS_NMI1_DSDMA

#define ENVY24_CCS_NMI1_DSDMA 0x08 /* DS channel C DMA interrupt */

Definition at line 135 of file envy24.h.

◆ ENVY24_CCS_NMI1_FM

#define ENVY24_CCS_NMI1_FM 0x01 /* FM data register write */

Definition at line 137 of file envy24.h.

◆ ENVY24_CCS_NMI1_MIDI

#define ENVY24_CCS_NMI1_MIDI 0x04 /* MIDI 330h or [PCI_10]h+Ch write */

Definition at line 136 of file envy24.h.

◆ ENVY24_CCS_NMI1_PCI

#define ENVY24_CCS_NMI1_PCI 0x80 /* PCI I/O read/write cycle */

Definition at line 132 of file envy24.h.

◆ ENVY24_CCS_NMI1_SB

#define ENVY24_CCS_NMI1_SB 0x40 /* SB 22C/24C write */

Definition at line 133 of file envy24.h.

◆ ENVY24_CCS_NMI1_SBDMA

#define ENVY24_CCS_NMI1_SBDMA 0x10 /* SB interrupt (SB DMA/SB F2 command) */

Definition at line 134 of file envy24.h.

◆ ENVY24_CCS_NMI2

#define ENVY24_CCS_NMI2 0x0e /* NMI Status Register 2 */

Definition at line 156 of file envy24.h.

◆ ENVY24_CCS_NMI2_FM0

#define ENVY24_CCS_NMI2_FM0 0x10 /* FM bank 0 (388h/220h/228h) */

Definition at line 158 of file envy24.h.

◆ ENVY24_CCS_NMI2_FM1

#define ENVY24_CCS_NMI2_FM1 0x20 /* FM bank 1 (38ah/222h) */

Definition at line 159 of file envy24.h.

◆ ENVY24_CCS_NMI2_FMBANK

#define ENVY24_CCS_NMI2_FMBANK 0x30 /* FM bank indicator */

Definition at line 157 of file envy24.h.

◆ ENVY24_CCS_NMI2_PIC20R

#define ENVY24_CCS_NMI2_PIC20R 0x09 /* 20h read */

Definition at line 165 of file envy24.h.

◆ ENVY24_CCS_NMI2_PIC20W

#define ENVY24_CCS_NMI2_PIC20W 0x01 /* 20h write */

Definition at line 161 of file envy24.h.

◆ ENVY24_CCS_NMI2_PIC21R

#define ENVY24_CCS_NMI2_PIC21R 0x0d /* 21h read */

Definition at line 167 of file envy24.h.

◆ ENVY24_CCS_NMI2_PIC21W

#define ENVY24_CCS_NMI2_PIC21W 0x05 /* 21h write */

Definition at line 163 of file envy24.h.

◆ ENVY24_CCS_NMI2_PICA0R

#define ENVY24_CCS_NMI2_PICA0R 0x0a /* a0h read */

Definition at line 166 of file envy24.h.

◆ ENVY24_CCS_NMI2_PICA0W

#define ENVY24_CCS_NMI2_PICA0W 0x02 /* a0h write */

Definition at line 162 of file envy24.h.

◆ ENVY24_CCS_NMI2_PICA1R

#define ENVY24_CCS_NMI2_PICA1R 0x0e /* a1h read */

Definition at line 168 of file envy24.h.

◆ ENVY24_CCS_NMI2_PICA1W

#define ENVY24_CCS_NMI2_PICA1W 0x06 /* a1h write */

Definition at line 164 of file envy24.h.

◆ ENVY24_CCS_NMI2_PICIO

#define ENVY24_CCS_NMI2_PICIO 0x0f /* PIC I/O cycle */

Definition at line 160 of file envy24.h.

◆ ENVY24_CCS_NMIDAT

#define ENVY24_CCS_NMIDAT 0x06 /* NMI Data Register */

Definition at line 139 of file envy24.h.

◆ ENVY24_CCS_NMIIDX

#define ENVY24_CCS_NMIIDX 0x07 /* NMI Index Register */

Definition at line 140 of file envy24.h.

◆ ENVY24_CCS_PMIDICMD

#define ENVY24_CCS_PMIDICMD 0x0d /* Primary MIDI UART Command/Status Register */

Definition at line 154 of file envy24.h.

◆ ENVY24_CCS_PMIDIDAT

#define ENVY24_CCS_PMIDIDAT 0x0c /* Primary MIDI UART Data Register */

Definition at line 153 of file envy24.h.

◆ ENVY24_CCS_SERR

#define ENVY24_CCS_SERR 0x1b /* PCI Configuration SERR# Shadow Register */

Definition at line 187 of file envy24.h.

◆ ENVY24_CCS_SMIDICMD

#define ENVY24_CCS_SMIDICMD 0x1d /* Secondary MIDI UART Command/Status Register */

Definition at line 189 of file envy24.h.

◆ ENVY24_CCS_SMIDIDAT

#define ENVY24_CCS_SMIDIDAT 0x1c /* Secondary MIDI UART Data Register */

Definition at line 188 of file envy24.h.

◆ ENVY24_CCS_TIMER

#define ENVY24_CCS_TIMER 0x1e /* Timer Register */

Definition at line 191 of file envy24.h.

◆ ENVY24_CCS_TIMER_EN

#define ENVY24_CCS_TIMER_EN 0x8000 /* Timer count enable */

Definition at line 192 of file envy24.h.

◆ ENVY24_CCS_TIMER_MASK

#define ENVY24_CCS_TIMER_MASK 0x7fff /* Timer counter mask */

Definition at line 193 of file envy24.h.

◆ ENVY24_CHAN_NUM

#define ENVY24_CHAN_NUM 11 /* Play * 5 + Record * 5 + Mix * 1 */

Definition at line 374 of file envy24.h.

◆ ENVY24_CHAN_PLAY_DAC1

#define ENVY24_CHAN_PLAY_DAC1 0

Definition at line 376 of file envy24.h.

◆ ENVY24_CHAN_PLAY_DAC2

#define ENVY24_CHAN_PLAY_DAC2 1

Definition at line 377 of file envy24.h.

◆ ENVY24_CHAN_PLAY_DAC3

#define ENVY24_CHAN_PLAY_DAC3 2

Definition at line 378 of file envy24.h.

◆ ENVY24_CHAN_PLAY_DAC4

#define ENVY24_CHAN_PLAY_DAC4 3

Definition at line 379 of file envy24.h.

◆ ENVY24_CHAN_PLAY_SPDIF

#define ENVY24_CHAN_PLAY_SPDIF 4

Definition at line 380 of file envy24.h.

◆ ENVY24_CHAN_REC_ADC1

#define ENVY24_CHAN_REC_ADC1 5

Definition at line 381 of file envy24.h.

◆ ENVY24_CHAN_REC_ADC2

#define ENVY24_CHAN_REC_ADC2 6

Definition at line 382 of file envy24.h.

◆ ENVY24_CHAN_REC_ADC3

#define ENVY24_CHAN_REC_ADC3 7

Definition at line 383 of file envy24.h.

◆ ENVY24_CHAN_REC_ADC4

#define ENVY24_CHAN_REC_ADC4 8

Definition at line 384 of file envy24.h.

◆ ENVY24_CHAN_REC_MIX

#define ENVY24_CHAN_REC_MIX 10

Definition at line 386 of file envy24.h.

◆ ENVY24_CHAN_REC_SPDIF

#define ENVY24_CHAN_REC_SPDIF 9

Definition at line 385 of file envy24.h.

◆ ENVY24_CS8404_PRO_RATE

#define ENVY24_CS8404_PRO_RATE 0x18

Definition at line 475 of file envy24.h.

◆ ENVY24_CS8404_PRO_RATE32

#define ENVY24_CS8404_PRO_RATE32 0x00

Definition at line 476 of file envy24.h.

◆ ENVY24_CS8404_PRO_RATE441

#define ENVY24_CS8404_PRO_RATE441 0x10

Definition at line 477 of file envy24.h.

◆ ENVY24_CS8404_PRO_RATE48

#define ENVY24_CS8404_PRO_RATE48 0x08

Definition at line 478 of file envy24.h.

◆ ENVY24_CS_CHDAT

#define ENVY24_CS_CHDAT 0x04 /* Channel Data register */

Definition at line 269 of file envy24.h.

◆ ENVY24_CS_CHIDX

#define ENVY24_CS_CHIDX 0x08 /* Channel Index Register */

Definition at line 271 of file envy24.h.

◆ ENVY24_CS_CHIDX_ADDR0

#define ENVY24_CS_CHIDX_ADDR0 0x00 /* Buffer_0 DMA base address */

Definition at line 273 of file envy24.h.

◆ ENVY24_CS_CHIDX_ADDR1

#define ENVY24_CS_CHIDX_ADDR1 0x02 /* Buffer_1 DMA base address */

Definition at line 275 of file envy24.h.

◆ ENVY24_CS_CHIDX_CNT0

#define ENVY24_CS_CHIDX_CNT0 0x01 /* Buffer_0 DMA base count */

Definition at line 274 of file envy24.h.

◆ ENVY24_CS_CHIDX_CNT1

#define ENVY24_CS_CHIDX_CNT1 0x03 /* Buffer_1 DMA base count */

Definition at line 276 of file envy24.h.

◆ ENVY24_CS_CHIDX_CTL

#define ENVY24_CS_CHIDX_CTL 0x04 /* Channel Control and Status register */

Definition at line 277 of file envy24.h.

◆ ENVY24_CS_CHIDX_NUM

#define ENVY24_CS_CHIDX_NUM 0xf0 /* Channel number */

Definition at line 272 of file envy24.h.

◆ ENVY24_CS_CHIDX_RATE

#define ENVY24_CS_CHIDX_RATE 0x05 /* Channel Sampling Rate */

Definition at line 278 of file envy24.h.

◆ ENVY24_CS_CHIDX_VOL

#define ENVY24_CS_CHIDX_VOL 0x06 /* Channel left and right volume/pan control */

Definition at line 279 of file envy24.h.

◆ ENVY24_CS_CTL_AUTO0

#define ENVY24_CS_CTL_AUTO0 0x20 /* Buffer_0 auto init. enable */

Definition at line 283 of file envy24.h.

◆ ENVY24_CS_CTL_AUTO1

#define ENVY24_CS_CTL_AUTO1 0x40 /* Buffer_1 auto init. enable */

Definition at line 282 of file envy24.h.

◆ ENVY24_CS_CTL_BUF

#define ENVY24_CS_CTL_BUF 0x80 /* indicating that the current active buffer */

Definition at line 281 of file envy24.h.

◆ ENVY24_CS_CTL_FLUSH

#define ENVY24_CS_CTL_FLUSH 0x10 /* Flush FIFO */

Definition at line 284 of file envy24.h.

◆ ENVY24_CS_CTL_PAUSE

#define ENVY24_CS_CTL_PAUSE 0x02 /* DMA request 1:pause */

Definition at line 287 of file envy24.h.

◆ ENVY24_CS_CTL_START

#define ENVY24_CS_CTL_START 0x01 /* DMA request 1: start, 0:stop */

Definition at line 288 of file envy24.h.

◆ ENVY24_CS_CTL_STEREO

#define ENVY24_CS_CTL_STEREO 0x08 /* stereo(or mono) */

Definition at line 285 of file envy24.h.

◆ ENVY24_CS_CTL_U8

#define ENVY24_CS_CTL_U8 0x04 /* 8-bit unsigned(or 16-bit signed) */

Definition at line 286 of file envy24.h.

◆ ENVY24_CS_INTMASK

#define ENVY24_CS_INTMASK 0x00 /* DirectSound DMA Interrupt Mask Register */

Definition at line 267 of file envy24.h.

◆ ENVY24_CS_INTSTAT

#define ENVY24_CS_INTSTAT 0x02 /* DirectSound DMA Interrupt Status Register */

Definition at line 268 of file envy24.h.

◆ ENVY24_CS_VOL_LEFT

#define ENVY24_CS_VOL_LEFT 0x003f

Definition at line 291 of file envy24.h.

◆ ENVY24_CS_VOL_RIGHT

#define ENVY24_CS_VOL_RIGHT 0x3f00

Definition at line 290 of file envy24.h.

◆ ENVY24_DDMA_ADDR0

#define ENVY24_DDMA_ADDR0 0x00 /* DMA Base and Current Address bit 0-7 */

Definition at line 253 of file envy24.h.

◆ ENVY24_DDMA_ADDR16

#define ENVY24_DDMA_ADDR16 0x02 /* DMA Base and Current Address bit 16-23 */

Definition at line 255 of file envy24.h.

◆ ENVY24_DDMA_ADDR24

#define ENVY24_DDMA_ADDR24 0x03 /* DMA Base and Current Address bit 24-31 */

Definition at line 256 of file envy24.h.

◆ ENVY24_DDMA_ADDR8

#define ENVY24_DDMA_ADDR8 0x01 /* DMA Base and Current Address bit 8-15 */

Definition at line 254 of file envy24.h.

◆ ENVY24_DDMA_CHAN

#define ENVY24_DDMA_CHAN 0x0f /* Channel Mask */

Definition at line 263 of file envy24.h.

◆ ENVY24_DDMA_CMD

#define ENVY24_DDMA_CMD 0x08 /* Status and Command */

Definition at line 260 of file envy24.h.

◆ ENVY24_DDMA_CNT0

#define ENVY24_DDMA_CNT0 0x04 /* DMA Base and Current Count 0-7 */

Definition at line 257 of file envy24.h.

◆ ENVY24_DDMA_CNT16

#define ENVY24_DDMA_CNT16 0x06 /* (not supported) */

Definition at line 259 of file envy24.h.

◆ ENVY24_DDMA_CNT8

#define ENVY24_DDMA_CNT8 0x05 /* DMA Base and Current Count 8-15 */

Definition at line 258 of file envy24.h.

◆ ENVY24_DDMA_MODE

#define ENVY24_DDMA_MODE 0x0b /* Mode */

Definition at line 261 of file envy24.h.

◆ ENVY24_DDMA_RESET

#define ENVY24_DDMA_RESET 0x0c /* Master reset */

Definition at line 262 of file envy24.h.

◆ ENVY24_DELTA_AK4524_CIF

#define ENVY24_DELTA_AK4524_CIF 0

Definition at line 481 of file envy24.h.

◆ ENVY24_E2PROM_AC97MAIN

#define ENVY24_E2PROM_AC97MAIN 0x0d

Definition at line 456 of file envy24.h.

◆ ENVY24_E2PROM_AC97PCM

#define ENVY24_E2PROM_AC97PCM 0x0f

Definition at line 457 of file envy24.h.

◆ ENVY24_E2PROM_AC97REC

#define ENVY24_E2PROM_AC97REC 0x11

Definition at line 458 of file envy24.h.

◆ ENVY24_E2PROM_AC97RECSRC

#define ENVY24_E2PROM_AC97RECSRC 0x13

Definition at line 459 of file envy24.h.

◆ ENVY24_E2PROM_ACL

#define ENVY24_E2PROM_ACL 0x07

Definition at line 450 of file envy24.h.

◆ ENVY24_E2PROM_ADCID

#define ENVY24_E2PROM_ADCID 0x18

Definition at line 461 of file envy24.h.

◆ ENVY24_E2PROM_DACID

#define ENVY24_E2PROM_DACID 0x14

Definition at line 460 of file envy24.h.

◆ ENVY24_E2PROM_EXTRA

#define ENVY24_E2PROM_EXTRA 0x1c

Definition at line 462 of file envy24.h.

◆ ENVY24_E2PROM_GPIODIR

#define ENVY24_E2PROM_GPIODIR 0x0c

Definition at line 455 of file envy24.h.

◆ ENVY24_E2PROM_GPIOMASK

#define ENVY24_E2PROM_GPIOMASK 0x0a

Definition at line 453 of file envy24.h.

◆ ENVY24_E2PROM_GPIOSTATE

#define ENVY24_E2PROM_GPIOSTATE 0x0b

Definition at line 454 of file envy24.h.

◆ ENVY24_E2PROM_I2S

#define ENVY24_E2PROM_I2S 0x08

Definition at line 451 of file envy24.h.

◆ ENVY24_E2PROM_SCFG

#define ENVY24_E2PROM_SCFG 0x06

Definition at line 449 of file envy24.h.

◆ ENVY24_E2PROM_SIZE

#define ENVY24_E2PROM_SIZE 0x04

Definition at line 447 of file envy24.h.

◆ ENVY24_E2PROM_SPDIF

#define ENVY24_E2PROM_SPDIF 0x09

Definition at line 452 of file envy24.h.

◆ ENVY24_E2PROM_SUBDEVICE

#define ENVY24_E2PROM_SUBDEVICE 0x02

Definition at line 446 of file envy24.h.

◆ ENVY24_E2PROM_SUBVENDOR

#define ENVY24_E2PROM_SUBVENDOR 0x00

Definition at line 445 of file envy24.h.

◆ ENVY24_E2PROM_VERSION

#define ENVY24_E2PROM_VERSION 0x05

Definition at line 448 of file envy24.h.

◆ ENVY24_GPIO_AK4524_CCLK

#define ENVY24_GPIO_AK4524_CCLK 0x20

Definition at line 470 of file envy24.h.

◆ ENVY24_GPIO_AK4524_CDTI

#define ENVY24_GPIO_AK4524_CDTI 0x10 /* this value is duplicated to input select */

Definition at line 469 of file envy24.h.

◆ ENVY24_GPIO_AK4524_CS0

#define ENVY24_GPIO_AK4524_CS0 0x40

Definition at line 471 of file envy24.h.

◆ ENVY24_GPIO_AK4524_CS1

#define ENVY24_GPIO_AK4524_CS1 0x80

Definition at line 472 of file envy24.h.

◆ ENVY24_GPIO_CS8414_STATUS

#define ENVY24_GPIO_CS8414_STATUS 0x02

Definition at line 466 of file envy24.h.

◆ ENVY24_GPIO_CS84X4_CLK

#define ENVY24_GPIO_CS84X4_CLK 0x04

Definition at line 467 of file envy24.h.

◆ ENVY24_GPIO_CS84X4_DATA

#define ENVY24_GPIO_CS84X4_DATA 0x08

Definition at line 468 of file envy24.h.

◆ ENVY24_GPIO_CS84X4_PRO

#define ENVY24_GPIO_CS84X4_PRO 0x01

Definition at line 465 of file envy24.h.

◆ ENVY24_MIX_MASK

#define ENVY24_MIX_MASK 0x3ff

Definition at line 388 of file envy24.h.

◆ ENVY24_MIX_REC_MASK

#define ENVY24_MIX_REC_MASK 0x3e0

Definition at line 389 of file envy24.h.

◆ ENVY24_MT_AC97CMD

#define ENVY24_MT_AC97CMD 0x05 /* Command and Status Register for AC'97 Codecs */

Definition at line 325 of file envy24.h.

◆ ENVY24_MT_AC97CMD_CLD

#define ENVY24_MT_AC97CMD_CLD 0x80 /* Cold reset */

Definition at line 326 of file envy24.h.

◆ ENVY24_MT_AC97CMD_ID

#define ENVY24_MT_AC97CMD_ID 0x03 /* ID(0-3) for external AC 97 registers */

Definition at line 331 of file envy24.h.

◆ ENVY24_MT_AC97CMD_RD

#define ENVY24_MT_AC97CMD_RD 0x10 /* read AC'97 CODEC register */

Definition at line 329 of file envy24.h.

◆ ENVY24_MT_AC97CMD_RDY

#define ENVY24_MT_AC97CMD_RDY 0x08 /* AC'97 codec ready status bit */

Definition at line 330 of file envy24.h.

◆ ENVY24_MT_AC97CMD_WR

#define ENVY24_MT_AC97CMD_WR 0x20 /* write to AC'97 codec register */

Definition at line 328 of file envy24.h.

◆ ENVY24_MT_AC97CMD_WRM

#define ENVY24_MT_AC97CMD_WRM 0x40 /* Warm reset */

Definition at line 327 of file envy24.h.

◆ ENVY24_MT_AC97DHI

#define ENVY24_MT_AC97DHI 0x07 /* AC'97 codec register data high byte */

Definition at line 334 of file envy24.h.

◆ ENVY24_MT_AC97DLO

#define ENVY24_MT_AC97DLO 0x06 /* AC'97 codec register data low byte */

Definition at line 333 of file envy24.h.

◆ ENVY24_MT_AC97IDX

#define ENVY24_MT_AC97IDX 0x04 /* Index Register for AC'97 Codecs */

Definition at line 323 of file envy24.h.

◆ ENVY24_MT_I2S

#define ENVY24_MT_I2S 0x02 /* I2S Data Format Register */

Definition at line 318 of file envy24.h.

◆ ENVY24_MT_I2S_FORM

#define ENVY24_MT_I2S_FORM 0x00 /* I2S data format */

Definition at line 321 of file envy24.h.

◆ ENVY24_MT_I2S_MLR128

#define ENVY24_MT_I2S_MLR128 0x08 /* MCLK/LRCLK ratio 128x(or 256x) */

Definition at line 319 of file envy24.h.

◆ ENVY24_MT_I2S_SLR48

#define ENVY24_MT_I2S_SLR48 0x04 /* SCLK/LRCLK ratio 48bpf(or 64bpf) */

Definition at line 320 of file envy24.h.

◆ ENVY24_MT_INT

#define ENVY24_MT_INT 0x00 /* DMA Interrupt Mask and Status Register */

Definition at line 295 of file envy24.h.

◆ ENVY24_MT_INT_PMASK

#define ENVY24_MT_INT_PMASK 0x40 /* Multi-track playback interrupt mask */

Definition at line 297 of file envy24.h.

◆ ENVY24_MT_INT_PSTAT

#define ENVY24_MT_INT_PSTAT 0x01 /* Multi-track playback interrupt status */

Definition at line 299 of file envy24.h.

◆ ENVY24_MT_INT_RMASK

#define ENVY24_MT_INT_RMASK 0x80 /* Multi-track record interrupt mask */

Definition at line 296 of file envy24.h.

◆ ENVY24_MT_INT_RSTAT

#define ENVY24_MT_INT_RSTAT 0x02 /* Multi-track record interrupt status */

Definition at line 298 of file envy24.h.

◆ ENVY24_MT_MONAC97

#define ENVY24_MT_MONAC97 0x3c /* Digital Mixer Monitor Routing Control Register */

Definition at line 362 of file envy24.h.

◆ ENVY24_MT_PADDR

#define ENVY24_MT_PADDR 0x10 /* Playback DMA Current/Base Address Register */

Definition at line 335 of file envy24.h.

◆ ENVY24_MT_PCNT

#define ENVY24_MT_PCNT 0x14 /* Playback DMA Current/Base Count Register */

Definition at line 336 of file envy24.h.

◆ ENVY24_MT_PCTL

#define ENVY24_MT_PCTL 0x18 /* Playback and Record Control Register */

Definition at line 338 of file envy24.h.

◆ ENVY24_MT_PCTL_PAUSE

#define ENVY24_MT_PCTL_PAUSE 0x02 /* 1: Pause; 0: Resume */

Definition at line 340 of file envy24.h.

◆ ENVY24_MT_PCTL_PSTART

#define ENVY24_MT_PCTL_PSTART 0x01 /* 1: Playback start; 0: Playback stop */

Definition at line 341 of file envy24.h.

◆ ENVY24_MT_PCTL_RSTART

#define ENVY24_MT_PCTL_RSTART 0x04 /* 1: Record start; 0: Record stop */

Definition at line 339 of file envy24.h.

◆ ENVY24_MT_PEAKDAT

#define ENVY24_MT_PEAKDAT 0x3f /* Peak Meter Data Register */

Definition at line 364 of file envy24.h.

◆ ENVY24_MT_PEAKIDX

#define ENVY24_MT_PEAKIDX 0x3e /* Peak Meter Index Register */

Definition at line 363 of file envy24.h.

◆ ENVY24_MT_PSDOUT

#define ENVY24_MT_PSDOUT 0x30 /* Routing Control Register for Data to PSDOUT[0:3] */

Definition at line 349 of file envy24.h.

◆ ENVY24_MT_PTERM

#define ENVY24_MT_PTERM 0x16 /* Playback Current/Base Terminal Count Register */

Definition at line 337 of file envy24.h.

◆ ENVY24_MT_RADDR

#define ENVY24_MT_RADDR 0x20 /* Record DMA Current/Base Address Register */

Definition at line 343 of file envy24.h.

◆ ENVY24_MT_RATE

#define ENVY24_MT_RATE 0x01 /* Sampling Rate Select Register */

Definition at line 301 of file envy24.h.

◆ ENVY24_MT_RATE_11025

#define ENVY24_MT_RATE_11025 0x0a

Definition at line 314 of file envy24.h.

◆ ENVY24_MT_RATE_12000

#define ENVY24_MT_RATE_12000 0x02

Definition at line 305 of file envy24.h.

◆ ENVY24_MT_RATE_16000

#define ENVY24_MT_RATE_16000 0x05

Definition at line 308 of file envy24.h.

◆ ENVY24_MT_RATE_22050

#define ENVY24_MT_RATE_22050 0x09

Definition at line 313 of file envy24.h.

◆ ENVY24_MT_RATE_24000

#define ENVY24_MT_RATE_24000 0x01

Definition at line 304 of file envy24.h.

◆ ENVY24_MT_RATE_32000

#define ENVY24_MT_RATE_32000 0x04

Definition at line 307 of file envy24.h.

◆ ENVY24_MT_RATE_44100

#define ENVY24_MT_RATE_44100 0x08

Definition at line 312 of file envy24.h.

◆ ENVY24_MT_RATE_48000

#define ENVY24_MT_RATE_48000 0x00

Definition at line 303 of file envy24.h.

◆ ENVY24_MT_RATE_64000

#define ENVY24_MT_RATE_64000 0x0f

Definition at line 311 of file envy24.h.

◆ ENVY24_MT_RATE_8000

#define ENVY24_MT_RATE_8000 0x06

Definition at line 309 of file envy24.h.

◆ ENVY24_MT_RATE_88200

#define ENVY24_MT_RATE_88200 0x0b

Definition at line 315 of file envy24.h.

◆ ENVY24_MT_RATE_9600

#define ENVY24_MT_RATE_9600 0x03

Definition at line 306 of file envy24.h.

◆ ENVY24_MT_RATE_96000

#define ENVY24_MT_RATE_96000 0x07

Definition at line 310 of file envy24.h.

◆ ENVY24_MT_RATE_MASK

#define ENVY24_MT_RATE_MASK 0x0f

Definition at line 316 of file envy24.h.

◆ ENVY24_MT_RATE_SPDIF

#define ENVY24_MT_RATE_SPDIF 0x10 /* S/PDIF input clock as the master */

Definition at line 302 of file envy24.h.

◆ ENVY24_MT_RCNT

#define ENVY24_MT_RCNT 0x24 /* Record DMA Current/Base Count Register */

Definition at line 344 of file envy24.h.

◆ ENVY24_MT_RCTL

#define ENVY24_MT_RCTL 0x28 /* Record Control Register */

Definition at line 346 of file envy24.h.

◆ ENVY24_MT_RCTL_RSTART

#define ENVY24_MT_RCTL_RSTART 0x01 /* 1: Record start; 0: Record stop */

Definition at line 347 of file envy24.h.

◆ ENVY24_MT_RECORD

#define ENVY24_MT_RECORD 0x34 /* Captured (Recorded) data Routing Selection Register */

Definition at line 351 of file envy24.h.

◆ ENVY24_MT_RTERM

#define ENVY24_MT_RTERM 0x26 /* Record Current/Base Terminal Count Register */

Definition at line 345 of file envy24.h.

◆ ENVY24_MT_SPDOUT

#define ENVY24_MT_SPDOUT 0x32 /* Routing Control Register for SPDOUT */

Definition at line 350 of file envy24.h.

◆ ENVY24_MT_VOLIDX

#define ENVY24_MT_VOLIDX 0x3a /* Volume Control Stream Index Register */

Definition at line 360 of file envy24.h.

◆ ENVY24_MT_VOLRATE

#define ENVY24_MT_VOLRATE 0x3b /* Volume Control Rate Register */

Definition at line 361 of file envy24.h.

◆ ENVY24_MT_VOLUME

#define ENVY24_MT_VOLUME 0x38 /* Left/Right Volume Control Data Register */

Definition at line 356 of file envy24.h.

◆ ENVY24_MT_VOLUME_L

#define ENVY24_MT_VOLUME_L 0x007f /* Left Volume Mask */

Definition at line 357 of file envy24.h.

◆ ENVY24_MT_VOLUME_R

#define ENVY24_MT_VOLUME_R 0x7f00 /* Right Volume Mask */

Definition at line 358 of file envy24.h.

◆ ENVY24_ROUTE_ADC_1

#define ENVY24_ROUTE_ADC_1 0

Definition at line 429 of file envy24.h.

◆ ENVY24_ROUTE_ADC_2

#define ENVY24_ROUTE_ADC_2 1

Definition at line 430 of file envy24.h.

◆ ENVY24_ROUTE_ADC_3

#define ENVY24_ROUTE_ADC_3 2

Definition at line 431 of file envy24.h.

◆ ENVY24_ROUTE_ADC_4

#define ENVY24_ROUTE_ADC_4 3

Definition at line 432 of file envy24.h.

◆ ENVY24_ROUTE_CLASS_ADC

#define ENVY24_ROUTE_CLASS_ADC 2

Definition at line 426 of file envy24.h.

◆ ENVY24_ROUTE_CLASS_DMA

#define ENVY24_ROUTE_CLASS_DMA 0

Definition at line 424 of file envy24.h.

◆ ENVY24_ROUTE_CLASS_MIX

#define ENVY24_ROUTE_CLASS_MIX 1

Definition at line 425 of file envy24.h.

◆ ENVY24_ROUTE_CLASS_SPDIF

#define ENVY24_ROUTE_CLASS_SPDIF 3

Definition at line 427 of file envy24.h.

◆ ENVY24_ROUTE_DAC_1

#define ENVY24_ROUTE_DAC_1 0

Definition at line 418 of file envy24.h.

◆ ENVY24_ROUTE_DAC_2

#define ENVY24_ROUTE_DAC_2 1

Definition at line 419 of file envy24.h.

◆ ENVY24_ROUTE_DAC_3

#define ENVY24_ROUTE_DAC_3 2

Definition at line 420 of file envy24.h.

◆ ENVY24_ROUTE_DAC_4

#define ENVY24_ROUTE_DAC_4 3

Definition at line 421 of file envy24.h.

◆ ENVY24_ROUTE_DAC_SPDIF

#define ENVY24_ROUTE_DAC_SPDIF 4

Definition at line 422 of file envy24.h.

◆ ENVY24_ROUTE_LEFT

#define ENVY24_ROUTE_LEFT 0

Definition at line 436 of file envy24.h.

◆ ENVY24_ROUTE_NORMAL

#define ENVY24_ROUTE_NORMAL 0

Definition at line 434 of file envy24.h.

◆ ENVY24_ROUTE_REVERSE

#define ENVY24_ROUTE_REVERSE 1

Definition at line 435 of file envy24.h.

◆ ENVY24_ROUTE_RIGHT

#define ENVY24_ROUTE_RIGHT 1

Definition at line 437 of file envy24.h.

◆ ENVY24_VOL_MAX

#define ENVY24_VOL_MAX 0 /* 0db(negate) */

Definition at line 392 of file envy24.h.

◆ ENVY24_VOL_MIN

#define ENVY24_VOL_MIN 96 /* -144db(negate) */

Definition at line 393 of file envy24.h.

◆ ENVY24_VOL_MUTE

#define ENVY24_VOL_MUTE 127 /* mute */

Definition at line 394 of file envy24.h.

◆ I2C_DELAY

#define I2C_DELAY 1000

Definition at line 483 of file envy24.h.

◆ PCA9554_DIR

#define PCA9554_DIR 0x03 /* port directions */

Definition at line 490 of file envy24.h.

◆ PCA9554_I2CDEV

#define PCA9554_I2CDEV 0x40 /* I2C device address */

Definition at line 486 of file envy24.h.

◆ PCA9554_IN

#define PCA9554_IN 0x00 /* input port */

Definition at line 487 of file envy24.h.

◆ PCA9554_INVERT

#define PCA9554_INVERT 0x02 /* polarity invert */

Definition at line 489 of file envy24.h.

◆ PCA9554_OUT

#define PCA9554_OUT 0x01 /* output port */

Definition at line 488 of file envy24.h.

◆ PCF8574_I2CDEV_DAC

#define PCF8574_I2CDEV_DAC 0x48

Definition at line 493 of file envy24.h.

◆ PCF8574_SENSE_MASK

#define PCF8574_SENSE_MASK 0x40

Definition at line 494 of file envy24.h.

◆ PCID_ENVY24

#define PCID_ENVY24 0x1712

Definition at line 35 of file envy24.h.

◆ PCIM_ACL_IMODE

#define PCIM_ACL_IMODE 0x01 /* AC 97 codec SDATA_IN 0:split 1:packed */

Definition at line 79 of file envy24.h.

◆ PCIM_ACL_MTC

#define PCIM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */

Definition at line 77 of file envy24.h.

◆ PCIM_ACL_OMODE

#define PCIM_ACL_OMODE 0x02 /* AC 97 codec SDATA_OUT 0:split 1:packed */

Definition at line 78 of file envy24.h.

◆ PCIM_I2S_16BIT

#define PCIM_I2S_16BIT 0x00 /* 16bit */

Definition at line 85 of file envy24.h.

◆ PCIM_I2S_18BIT

#define PCIM_I2S_18BIT 0x10 /* 18bit */

Definition at line 86 of file envy24.h.

◆ PCIM_I2S_20BIT

#define PCIM_I2S_20BIT 0x20 /* 20bit */

Definition at line 87 of file envy24.h.

◆ PCIM_I2S_24BIT

#define PCIM_I2S_24BIT 0x30 /* 24bit */

Definition at line 88 of file envy24.h.

◆ PCIM_I2S_96KHZ

#define PCIM_I2S_96KHZ 0x40 /* I2S converter 96kHz sampling rate support */

Definition at line 83 of file envy24.h.

◆ PCIM_I2S_ID

#define PCIM_I2S_ID 0x0f /* Other I2S IDs */

Definition at line 89 of file envy24.h.

◆ PCIM_I2S_RES

#define PCIM_I2S_RES 0x30 /* Converter resolution */

Definition at line 84 of file envy24.h.

◆ PCIM_I2S_VOL

#define PCIM_I2S_VOL 0x80 /* I2S codec Volume and mute */

Definition at line 82 of file envy24.h.

◆ PCIM_LAC_DISABLE

#define PCIM_LAC_DISABLE 0x8000 /* Legacy Audio Hardware disabled */

Definition at line 45 of file envy24.h.

◆ PCIM_LAC_FM

#define PCIM_LAC_FM 0x0002 /* FM I/O enable (AdLib 388h base) */

Definition at line 52 of file envy24.h.

◆ PCIM_LAC_GAME

#define PCIM_LAC_GAME 0x0004 /* Game Port enable (200h) */

Definition at line 51 of file envy24.h.

◆ PCIM_LAC_IOADDR10

#define PCIM_LAC_IOADDR10 0x0020 /* I/O Address Alias Control */

Definition at line 49 of file envy24.h.

◆ PCIM_LAC_MPU401

#define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */

Definition at line 50 of file envy24.h.

◆ PCIM_LAC_SB

#define PCIM_LAC_SB 0x0001 /* SB I/O enable */

Definition at line 53 of file envy24.h.

◆ PCIM_LAC_SBDMA0

#define PCIM_LAC_SBDMA0 0x0000 /* SB DMA Channel Select: 0 */

Definition at line 46 of file envy24.h.

◆ PCIM_LAC_SBDMA1

#define PCIM_LAC_SBDMA1 0x0040 /* SB DMA Channel Select: 1 */

Definition at line 47 of file envy24.h.

◆ PCIM_LAC_SBDMA3

#define PCIM_LAC_SBDMA3 0x00c0 /* SB DMA Channel Select: 3 */

Definition at line 48 of file envy24.h.

◆ PCIM_LCC_LDMA

#define PCIM_LCC_LDMA 0x0001 /* Legacy DMA enable */

Definition at line 63 of file envy24.h.

◆ PCIM_LCC_MPUBASE

#define PCIM_LCC_MPUBASE 0x0006 /* MPU-401 base 300h-330h */

Definition at line 62 of file envy24.h.

◆ PCIM_LCC_SBBASE

#define PCIM_LCC_SBBASE 0x0008 /* SB base 240h(1)/220h(0) */

Definition at line 61 of file envy24.h.

◆ PCIM_LCC_SNPPCI

#define PCIM_LCC_SNPPCI 0x0010 /* snoop PCI bus interrupt acknowledge cycle */

Definition at line 60 of file envy24.h.

◆ PCIM_LCC_SNPPIC

#define PCIM_LCC_SNPPIC 0x0020 /* snoop PIC I/O R/W cycle */

Definition at line 59 of file envy24.h.

◆ PCIM_LCC_SNPSB

#define PCIM_LCC_SNPSB 0x0040 /* snoop SB 22C/24Ch I/O write cycle */

Definition at line 58 of file envy24.h.

◆ PCIM_LCC_SVIDRW

#define PCIM_LCC_SVIDRW 0x0080 /* SVID read/write enable */

Definition at line 57 of file envy24.h.

◆ PCIM_LCC_VINT

#define PCIM_LCC_VINT 0xff00 /* Interrupt vector to be snooped */

Definition at line 56 of file envy24.h.

◆ PCIM_SCFG_AC97

#define PCIM_SCFG_AC97 0x10 /* 0: AC'97 codec exist */

Definition at line 71 of file envy24.h.

◆ PCIM_SCFG_ADC

#define PCIM_SCFG_ADC 0x0c /* 1-4 stereo ADC connected */

Definition at line 73 of file envy24.h.

◆ PCIM_SCFG_DAC

#define PCIM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */

Definition at line 74 of file envy24.h.

◆ PCIM_SCFG_MPU

#define PCIM_SCFG_MPU 0x20 /* 1(0)/2(1) MPU-401 UART(s) */

Definition at line 70 of file envy24.h.

◆ PCIM_SCFG_XIN2

#define PCIM_SCFG_XIN2 0xc0 /* XIN2 Clock Source Configuration */

Definition at line 66 of file envy24.h.

◆ PCIM_SPDIF_ID

#define PCIM_SPDIF_ID 0xfc /* S/PDIF chip ID */

Definition at line 92 of file envy24.h.

◆ PCIM_SPDIF_IN

#define PCIM_SPDIF_IN 0x02 /* S/PDIF Stereo In is present */

Definition at line 93 of file envy24.h.

◆ PCIM_SPDIF_OUT

#define PCIM_SPDIF_OUT 0x01 /* S/PDIF Stereo Out is present */

Definition at line 94 of file envy24.h.

◆ PCIR_ACL

#define PCIR_ACL 0x61 /* AC-Link Configuration Register */

Definition at line 76 of file envy24.h.

◆ PCIR_CCS

#define PCIR_CCS 0x10 /* Controller I/O Base Address */

Definition at line 39 of file envy24.h.

◆ PCIR_DDMA

#define PCIR_DDMA 0x14 /* DDMA I/O Base Address */

Definition at line 40 of file envy24.h.

◆ PCIR_DS

#define PCIR_DS 0x18 /* DMA Path Registers I/O Base Address */

Definition at line 41 of file envy24.h.

◆ PCIR_I2S

#define PCIR_I2S 0x62 /* I2S Converters Features Register */

Definition at line 81 of file envy24.h.

◆ PCIR_LAC

#define PCIR_LAC 0x40 /* Legacy Audio Control */

Definition at line 44 of file envy24.h.

◆ PCIR_LCC

#define PCIR_LCC 0x42 /* Legacy Configuration Control */

Definition at line 55 of file envy24.h.

◆ PCIR_MT

#define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */

Definition at line 42 of file envy24.h.

◆ PCIR_POWER_STAT

#define PCIR_POWER_STAT 0x84 /* Power Management Control and Status */

Definition at line 96 of file envy24.h.

◆ PCIR_SCFG

#define PCIR_SCFG 0x60 /* System Configuration Register */

Definition at line 65 of file envy24.h.

◆ PCIR_SPDIF

#define PCIR_SPDIF 0x63 /* S/PDIF Configuration Register */

Definition at line 91 of file envy24.h.

◆ PCIV_ENVY24

#define PCIV_ENVY24 0x1412

Definition at line 34 of file envy24.h.

Macros