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Macros
#define	ES1370_REG_CONTROL 0x00

#define	ES1370_REG_STATUS 0x04

#define	ES1370_REG_UART_DATA 0x08

#define	ES1370_REG_UART_STATUS 0x09

#define	ES1370_REG_UART_CONTROL 0x09

#define	ES1370_REG_UART_TEST 0x0a

#define	ES1370_REG_MEMPAGE 0x0c

#define	ES1370_REG_CODEC 0x10

#define	CODEC_INDEX_SHIFT 8

#define	ES1370_REG_SERIAL_CONTROL 0x20

#define	ES1370_REG_DAC1_SCOUNT 0x24

#define	ES1370_REG_DAC2_SCOUNT 0x28

#define	ES1370_REG_ADC_SCOUNT 0x2c

#define	ES1370_REG_DAC1_FRAMEADR 0xc30

#define	ES1370_REG_DAC1_FRAMECNT 0xc34

#define	ES1370_REG_DAC2_FRAMEADR 0xc38

#define	ES1370_REG_DAC2_FRAMECNT 0xc3c

#define	ES1370_REG_ADC_FRAMEADR 0xd30

#define	ES1370_REG_ADC_FRAMECNT 0xd34

#define	DAC2_SRTODIV(x) (((1411200 + (x) / 2) / (x) - 2) & 0x1fff)

#define	DAC2_DIVTOSR(x) (1411200 / ((x) + 2))

#define	CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */

#define	CTRL_XCTL1 0x40000000 /* SERR pin if enabled */

#define	CTRL_OPEN

#define	CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */

#define	CTRL_SH_PCLKDIV 16

#define	CTRL_MSFMTSEL

#define	CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */

#define	CTRL_WTSRSEL

#define	CTRL_SH_WTSRSEL 12

#define	CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */

#define	CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */

#define	CTRL_M_CB

#define	CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */

#define	CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */

#define	CTRL_DAC1_EN 0x00000040 /* enable DAC1 */

#define	CTRL_DAC2_EN 0x00000020 /* enable DAC2 */

#define	CTRL_ADC_EN 0x00000010 /* enable ADC */

#define	CTRL_UART_EN 0x00000008 /* enable MIDI uart */

#define	CTRL_JYSTK_EN

#define	CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */

#define	CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */

#define	SCTRL_P2ENDINC 0x00380000 /* */

#define	SCTRL_SH_P2ENDINC 19

#define	SCTRL_P2STINC 0x00070000 /* */

#define	SCTRL_SH_P2STINC 16

#define	SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */

#define	SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */

#define	SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */

#define	SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */

#define	SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */

#define	SCTRL_R1INTEN 0x00000400 /* enable interrupt */

#define	SCTRL_P2INTEN 0x00000200 /* enable interrupt */

#define	SCTRL_P1INTEN 0x00000100 /* enable interrupt */

#define	SCTRL_P1SCTRLD

#define	SCTRL_P2DACSEN

#define	SCTRL_R1SEB 0x00000020 /* 1 = 16bit */

#define	SCTRL_R1SMB 0x00000010 /* 1 = stereo */

#define	SCTRL_R1FMT 0x00000030 /* format mask */

#define	SCTRL_SH_R1FMT 4

#define	SCTRL_P2SEB 0x00000008 /* 1 = 16bit */

#define	SCTRL_P2SMB 0x00000004 /* 1 = stereo */

#define	SCTRL_P2FMT 0x0000000c /* format mask */

#define	SCTRL_SH_P2FMT 2

#define	SCTRL_P1SEB 0x00000002 /* 1 = 16bit */

#define	SCTRL_P1SMB 0x00000001 /* 1 = stereo */

#define	SCTRL_P1FMT 0x00000003 /* format mask */

#define	SCTRL_SH_P1FMT 0

#define	STAT_INTR 0x80000000 /* wired or of all interrupt bits */

#define	STAT_CSTAT

#define	STAT_CBUSY 0x00000200 /* 1 = codec busy */

#define	STAT_CWRIP 0x00000100 /* 1 = codec write in progress */

#define	STAT_VC

#define	STAT_SH_VC 5

#define	STAT_MCCB 0x00000010 /* CCB int pending */

#define	STAT_UART 0x00000008 /* UART int pending */

#define	STAT_DAC1 0x00000004 /* DAC1 int pending */

#define	STAT_DAC2 0x00000002 /* DAC2 int pending */

#define	STAT_ADC 0x00000001 /* ADC int pending */

#define	CODEC_OMIX1 0x10

#define	CODEC_OMIX2 0x11

#define	CODEC_LIMIX1 0x12

#define	CODEC_RIMIX1 0x13

#define	CODEC_LIMIX2 0x14

#define	CODEC_RIMIX2 0x15

#define	CODEC_RES_PD 0x16

#define	CODEC_CSEL 0x17

#define	CODEC_ADSEL 0x18

#define	CODEC_MGAIN 0x19

#define	CODEC_ID_SESHIFT 10

#define	CODEC_ID_SEMASK 0x1f

#define	CODEC_PIRD 0x00800000 /* 0 = write AC97 register */

#define	CODEC_PIADD_MASK 0x007f0000

#define	CODEC_PIADD_SHIFT 16

#define	CODEC_PIDAT_MASK 0x0000ffff

#define	CODEC_PIDAT_SHIFT 0

#define	CODEC_PORD 0x00800000 /* 0 = write AC97 register */

#define	CODEC_POADD_MASK 0x007f0000

#define	CODEC_POADD_SHIFT 16

#define	CODEC_PODAT_MASK 0x0000ffff

#define	CODEC_PODAT_SHIFT 0

#define	CODEC_RDY 0x80000000 /* AC97 read data valid */

#define	CODEC_WIP 0x40000000 /* AC97 write in progress */

#define	ES1370_REG_CONTROL 0x00

#define	ES1370_REG_SERIAL_CONTROL 0x20

#define	ES1371_REG_CODEC 0x14

#define	ES1371_REG_LEGACY 0x18 /* W/R: Legacy control/status register */

#define	ES1371_REG_SMPRATE 0x10 /* W/R: Codec rate converter interface register */

#define	ES1371_SYNC_RES (1<<14) /* Warm AC97 reset */

#define	ES1371_DIS_R1 (1<<19) /* record channel accumulator update disable */

#define	ES1371_DIS_P2 (1<<20) /* playback channel 2 accumulator update disable */

#define	ES1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */

#define	ES1371_DIS_SRC (1<<22) /* sample rate converter disable */

#define	ES1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */

#define	ES1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */

#define	ES1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25) /* address of the sample rate converter */

#define	ES1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0) /* current value of the sample rate converter */

#define	ES1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff) /* current value of the sample rate converter */

#define	RECEN_B 0x08000000 /* Used to control mixing of analog with digital data */

#define	SPDIFEN_B 0x04000000 /* Reset to switch digital output mux to "THRU" mode */

#define	ENABLE_SPDIF 0x00040000 /* Used to enable the S/PDIF circuitry */

#define	TEST_SPDIF 0x00020000 /* Used to put the S/PDIF module in "test mode" */

#define	ES_SMPREG_DAC1 0x70

#define	ES_SMPREG_DAC2 0x74

#define	ES_SMPREG_ADC 0x78

#define	ES_SMPREG_TRUNC_N 0x00

#define	ES_SMPREG_INT_REGS 0x01

#define	ES_SMPREG_VFREQ_FRAC 0x03

#define	ES_SMPREG_VOL_ADC 0x6c

#define	ES_SMPREG_VOL_DAC1 0x7c

#define	ES_SMPREG_VOL_DAC2 0x7e

Macro Definition Documentation

◆ CODEC_ADSEL

#define CODEC_ADSEL 0x18

Definition at line 129 of file es137x.h.

◆ CODEC_CSEL

#define CODEC_CSEL 0x17

Definition at line 128 of file es137x.h.

◆ CODEC_ID_SEMASK

#define CODEC_ID_SEMASK 0x1f

Definition at line 135 of file es137x.h.

◆ CODEC_ID_SESHIFT

#define CODEC_ID_SESHIFT 10

Definition at line 134 of file es137x.h.

◆ CODEC_INDEX_SHIFT

#define CODEC_INDEX_SHIFT 8

Definition at line 44 of file es137x.h.

◆ CODEC_LIMIX1

#define CODEC_LIMIX1 0x12

Definition at line 123 of file es137x.h.

◆ CODEC_LIMIX2

#define CODEC_LIMIX2 0x14

Definition at line 125 of file es137x.h.

◆ CODEC_MGAIN

#define CODEC_MGAIN 0x19

Definition at line 130 of file es137x.h.

◆ CODEC_OMIX1

#define CODEC_OMIX1 0x10

Definition at line 121 of file es137x.h.

◆ CODEC_OMIX2

#define CODEC_OMIX2 0x11

Definition at line 122 of file es137x.h.

◆ CODEC_PIADD_MASK

#define CODEC_PIADD_MASK 0x007f0000

Definition at line 138 of file es137x.h.

◆ CODEC_PIADD_SHIFT

#define CODEC_PIADD_SHIFT 16

Definition at line 139 of file es137x.h.

◆ CODEC_PIDAT_MASK

#define CODEC_PIDAT_MASK 0x0000ffff

Definition at line 140 of file es137x.h.

◆ CODEC_PIDAT_SHIFT

#define CODEC_PIDAT_SHIFT 0

Definition at line 141 of file es137x.h.

◆ CODEC_PIRD

#define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */

Definition at line 137 of file es137x.h.

◆ CODEC_POADD_MASK

#define CODEC_POADD_MASK 0x007f0000

Definition at line 144 of file es137x.h.

◆ CODEC_POADD_SHIFT

#define CODEC_POADD_SHIFT 16

Definition at line 145 of file es137x.h.

◆ CODEC_PODAT_MASK

#define CODEC_PODAT_MASK 0x0000ffff

Definition at line 146 of file es137x.h.

◆ CODEC_PODAT_SHIFT

#define CODEC_PODAT_SHIFT 0

Definition at line 147 of file es137x.h.

◆ CODEC_PORD

#define CODEC_PORD 0x00800000 /* 0 = write AC97 register */

Definition at line 143 of file es137x.h.

◆ CODEC_RDY

#define CODEC_RDY 0x80000000 /* AC97 read data valid */

Definition at line 149 of file es137x.h.

◆ CODEC_RES_PD

#define CODEC_RES_PD 0x16

Definition at line 127 of file es137x.h.

◆ CODEC_RIMIX1

#define CODEC_RIMIX1 0x13

Definition at line 124 of file es137x.h.

◆ CODEC_RIMIX2

#define CODEC_RIMIX2 0x15

Definition at line 126 of file es137x.h.

◆ CODEC_WIP

#define CODEC_WIP 0x40000000 /* AC97 write in progress */

Definition at line 150 of file es137x.h.

◆ CTRL_ADC_EN

#define CTRL_ADC_EN 0x00000010 /* enable ADC */

Definition at line 76 of file es137x.h.

◆ CTRL_ADC_STOP

#define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */

Definition at line 60 of file es137x.h.

◆ CTRL_BREQ

#define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */

Definition at line 73 of file es137x.h.

◆ CTRL_CCB_INTRM

#define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */

Definition at line 70 of file es137x.h.

◆ CTRL_CDC_EN

#define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */

Definition at line 79 of file es137x.h.

◆ CTRL_DAC1_EN

#define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */

Definition at line 74 of file es137x.h.

◆ CTRL_DAC2_EN

#define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */

Definition at line 75 of file es137x.h.

◆ CTRL_DAC_SYNC

#define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */

Definition at line 69 of file es137x.h.

◆ CTRL_JYSTK_EN

#define CTRL_JYSTK_EN

Value:

0x00000004 /* enable Joystick port (presumably

* at address 0x200) */

Definition at line 78 of file es137x.h.

◆ CTRL_M_CB

#define CTRL_M_CB

Value:

0x00000200 /* recording source: 0 = ADC, 1 =

* MPEG */

Definition at line 71 of file es137x.h.

◆ CTRL_M_SBB

#define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */

Definition at line 66 of file es137x.h.

◆ CTRL_MSFMTSEL

#define CTRL_MSFMTSEL

Value:

0x00008000 /* MPEG serial data fmt: 0 = Sony, 1

* = I2S */

Definition at line 65 of file es137x.h.

◆ CTRL_OPEN

#define CTRL_OPEN

Value:

0x20000000 /* no function, can be read and

* written */

Definition at line 62 of file es137x.h.

◆ CTRL_PCLKDIV

#define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */

Definition at line 63 of file es137x.h.

◆ CTRL_SERR_DIS

#define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */

Definition at line 80 of file es137x.h.

◆ CTRL_SH_PCLKDIV

#define CTRL_SH_PCLKDIV 16

Definition at line 64 of file es137x.h.

◆ CTRL_SH_WTSRSEL

#define CTRL_SH_WTSRSEL 12

Definition at line 68 of file es137x.h.

◆ CTRL_UART_EN

#define CTRL_UART_EN 0x00000008 /* enable MIDI uart */

Definition at line 77 of file es137x.h.

◆ CTRL_WTSRSEL

#define CTRL_WTSRSEL

Value:

0x00003000 /* DAC1 clock freq: 0=5512, 1=11025,

* 2=22050, 3=44100 */

Definition at line 67 of file es137x.h.

◆ CTRL_XCTL0

#define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */

Definition at line 72 of file es137x.h.

◆ CTRL_XCTL1

#define CTRL_XCTL1 0x40000000 /* SERR pin if enabled */

Definition at line 61 of file es137x.h.

◆ DAC2_DIVTOSR

#define DAC2_DIVTOSR ( x ) (1411200 / ((x) + 2))

Definition at line 58 of file es137x.h.

◆ DAC2_SRTODIV

#define DAC2_SRTODIV ( x ) (((1411200 + (x) / 2) / (x) - 2) & 0x1fff)

Definition at line 57 of file es137x.h.

◆ ENABLE_SPDIF

#define ENABLE_SPDIF 0x00040000 /* Used to enable the S/PDIF circuitry */

Definition at line 177 of file es137x.h.

◆ ES1370_REG_ADC_FRAMEADR

#define ES1370_REG_ADC_FRAMEADR 0xd30

Definition at line 54 of file es137x.h.

◆ ES1370_REG_ADC_FRAMECNT

#define ES1370_REG_ADC_FRAMECNT 0xd34

Definition at line 55 of file es137x.h.

◆ ES1370_REG_ADC_SCOUNT

#define ES1370_REG_ADC_SCOUNT 0x2c

Definition at line 48 of file es137x.h.

◆ ES1370_REG_CODEC

#define ES1370_REG_CODEC 0x10

Definition at line 43 of file es137x.h.

◆ ES1370_REG_CONTROL [1/2]

#define ES1370_REG_CONTROL 0x00

Definition at line 152 of file es137x.h.

◆ ES1370_REG_CONTROL [2/2]

#define ES1370_REG_CONTROL 0x00

Definition at line 152 of file es137x.h.

◆ ES1370_REG_DAC1_FRAMEADR

#define ES1370_REG_DAC1_FRAMEADR 0xc30

Definition at line 50 of file es137x.h.

◆ ES1370_REG_DAC1_FRAMECNT

#define ES1370_REG_DAC1_FRAMECNT 0xc34

Definition at line 51 of file es137x.h.

◆ ES1370_REG_DAC1_SCOUNT

#define ES1370_REG_DAC1_SCOUNT 0x24

Definition at line 46 of file es137x.h.

◆ ES1370_REG_DAC2_FRAMEADR

#define ES1370_REG_DAC2_FRAMEADR 0xc38

Definition at line 52 of file es137x.h.

◆ ES1370_REG_DAC2_FRAMECNT

#define ES1370_REG_DAC2_FRAMECNT 0xc3c

Definition at line 53 of file es137x.h.

◆ ES1370_REG_DAC2_SCOUNT

#define ES1370_REG_DAC2_SCOUNT 0x28

Definition at line 47 of file es137x.h.

◆ ES1370_REG_MEMPAGE

#define ES1370_REG_MEMPAGE 0x0c

Definition at line 42 of file es137x.h.

◆ ES1370_REG_SERIAL_CONTROL [1/2]

#define ES1370_REG_SERIAL_CONTROL 0x20

Definition at line 153 of file es137x.h.

◆ ES1370_REG_SERIAL_CONTROL [2/2]

#define ES1370_REG_SERIAL_CONTROL 0x20

Definition at line 153 of file es137x.h.

◆ ES1370_REG_STATUS

#define ES1370_REG_STATUS 0x04

Definition at line 37 of file es137x.h.

◆ ES1370_REG_UART_CONTROL

#define ES1370_REG_UART_CONTROL 0x09

Definition at line 40 of file es137x.h.

◆ ES1370_REG_UART_DATA

#define ES1370_REG_UART_DATA 0x08

Definition at line 38 of file es137x.h.

◆ ES1370_REG_UART_STATUS

#define ES1370_REG_UART_STATUS 0x09

Definition at line 39 of file es137x.h.

◆ ES1370_REG_UART_TEST

#define ES1370_REG_UART_TEST 0x0a

Definition at line 41 of file es137x.h.

◆ ES1371_DIS_P1

#define ES1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */

Definition at line 161 of file es137x.h.

◆ ES1371_DIS_P2

#define ES1371_DIS_P2 (1<<20) /* playback channel 2 accumulator update disable */

Definition at line 160 of file es137x.h.

◆ ES1371_DIS_R1

#define ES1371_DIS_R1 (1<<19) /* record channel accumulator update disable */

Definition at line 159 of file es137x.h.

◆ ES1371_DIS_SRC

#define ES1371_DIS_SRC (1<<22) /* sample rate converter disable */

Definition at line 162 of file es137x.h.

◆ ES1371_REG_CODEC

#define ES1371_REG_CODEC 0x14

Definition at line 154 of file es137x.h.

◆ ES1371_REG_LEGACY

#define ES1371_REG_LEGACY 0x18 /* W/R: Legacy control/status register */

Definition at line 155 of file es137x.h.

◆ ES1371_REG_SMPRATE

#define ES1371_REG_SMPRATE 0x10 /* W/R: Codec rate converter interface register */

Definition at line 156 of file es137x.h.

◆ ES1371_SRC_RAM_ADDRO

#define ES1371_SRC_RAM_ADDRO ( o ) (((o)&0x7f)<<25) /* address of the sample rate converter */

Definition at line 165 of file es137x.h.

◆ ES1371_SRC_RAM_BUSY

#define ES1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */

Definition at line 163 of file es137x.h.

◆ ES1371_SRC_RAM_DATAI

#define ES1371_SRC_RAM_DATAI ( i ) (((i)>>0)&0xffff) /* current value of the sample rate converter */

Definition at line 167 of file es137x.h.

◆ ES1371_SRC_RAM_DATAO

#define ES1371_SRC_RAM_DATAO ( o ) (((o)&0xffff)<<0) /* current value of the sample rate converter */

Definition at line 166 of file es137x.h.

◆ ES1371_SRC_RAM_WE

#define ES1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */

Definition at line 164 of file es137x.h.

◆ ES1371_SYNC_RES

#define ES1371_SYNC_RES (1<<14) /* Warm AC97 reset */

Definition at line 158 of file es137x.h.

◆ ES_SMPREG_ADC

#define ES_SMPREG_ADC 0x78

Definition at line 186 of file es137x.h.

◆ ES_SMPREG_DAC1

#define ES_SMPREG_DAC1 0x70

Definition at line 184 of file es137x.h.

◆ ES_SMPREG_DAC2

#define ES_SMPREG_DAC2 0x74

Definition at line 185 of file es137x.h.

◆ ES_SMPREG_INT_REGS

#define ES_SMPREG_INT_REGS 0x01

Definition at line 188 of file es137x.h.

◆ ES_SMPREG_TRUNC_N

#define ES_SMPREG_TRUNC_N 0x00

Definition at line 187 of file es137x.h.

◆ ES_SMPREG_VFREQ_FRAC

#define ES_SMPREG_VFREQ_FRAC 0x03

Definition at line 189 of file es137x.h.

◆ ES_SMPREG_VOL_ADC

#define ES_SMPREG_VOL_ADC 0x6c

Definition at line 190 of file es137x.h.

◆ ES_SMPREG_VOL_DAC1

#define ES_SMPREG_VOL_DAC1 0x7c

Definition at line 191 of file es137x.h.

◆ ES_SMPREG_VOL_DAC2

#define ES_SMPREG_VOL_DAC2 0x7e

Definition at line 192 of file es137x.h.

◆ RECEN_B

#define RECEN_B 0x08000000 /* Used to control mixing of analog with digital data */

Definition at line 174 of file es137x.h.

◆ SCTRL_P1FMT

#define SCTRL_P1FMT 0x00000003 /* format mask */

Definition at line 106 of file es137x.h.

◆ SCTRL_P1INTEN

#define SCTRL_P1INTEN 0x00000100 /* enable interrupt */

Definition at line 93 of file es137x.h.

◆ SCTRL_P1LOOPSEL

#define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */

Definition at line 88 of file es137x.h.

◆ SCTRL_P1PAUSE

#define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */

Definition at line 90 of file es137x.h.

◆ SCTRL_P1SCTRLD

#define SCTRL_P1SCTRLD

Value:

0x00000080 /* reload sample count register for

* DAC1 */

Definition at line 94 of file es137x.h.

◆ SCTRL_P1SEB

#define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */

Definition at line 104 of file es137x.h.

◆ SCTRL_P1SMB

#define SCTRL_P1SMB 0x00000001 /* 1 = stereo */

Definition at line 105 of file es137x.h.

◆ SCTRL_P2DACSEN

#define SCTRL_P2DACSEN

Value:

0x00000040 /* 1 = DAC2 play back last sample

* when disabled */

Definition at line 95 of file es137x.h.

◆ SCTRL_P2ENDINC

#define SCTRL_P2ENDINC 0x00380000 /* */

Definition at line 82 of file es137x.h.

◆ SCTRL_P2FMT

#define SCTRL_P2FMT 0x0000000c /* format mask */

Definition at line 102 of file es137x.h.

◆ SCTRL_P2INTEN

#define SCTRL_P2INTEN 0x00000200 /* enable interrupt */

Definition at line 92 of file es137x.h.

◆ SCTRL_P2LOOPSEL

#define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */

Definition at line 87 of file es137x.h.

◆ SCTRL_P2PAUSE

#define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */

Definition at line 89 of file es137x.h.

◆ SCTRL_P2SEB

#define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */

Definition at line 100 of file es137x.h.

◆ SCTRL_P2SMB

#define SCTRL_P2SMB 0x00000004 /* 1 = stereo */

Definition at line 101 of file es137x.h.

◆ SCTRL_P2STINC

#define SCTRL_P2STINC 0x00070000 /* */

Definition at line 84 of file es137x.h.

◆ SCTRL_R1FMT

#define SCTRL_R1FMT 0x00000030 /* format mask */

Definition at line 98 of file es137x.h.

◆ SCTRL_R1INTEN

#define SCTRL_R1INTEN 0x00000400 /* enable interrupt */

Definition at line 91 of file es137x.h.

◆ SCTRL_R1LOOPSEL

#define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */

Definition at line 86 of file es137x.h.

◆ SCTRL_R1SEB

#define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */

Definition at line 96 of file es137x.h.

◆ SCTRL_R1SMB

#define SCTRL_R1SMB 0x00000010 /* 1 = stereo */

Definition at line 97 of file es137x.h.

◆ SCTRL_SH_P1FMT

#define SCTRL_SH_P1FMT 0

Definition at line 107 of file es137x.h.

◆ SCTRL_SH_P2ENDINC

#define SCTRL_SH_P2ENDINC 19

Definition at line 83 of file es137x.h.

◆ SCTRL_SH_P2FMT

#define SCTRL_SH_P2FMT 2

Definition at line 103 of file es137x.h.

◆ SCTRL_SH_P2STINC

#define SCTRL_SH_P2STINC 16

Definition at line 85 of file es137x.h.

◆ SCTRL_SH_R1FMT

#define SCTRL_SH_R1FMT 4

Definition at line 99 of file es137x.h.

◆ SPDIFEN_B

#define SPDIFEN_B 0x04000000 /* Reset to switch digital output mux to "THRU" mode */

Definition at line 175 of file es137x.h.

◆ STAT_ADC

#define STAT_ADC 0x00000001 /* ADC int pending */

Definition at line 119 of file es137x.h.

◆ STAT_CBUSY

#define STAT_CBUSY 0x00000200 /* 1 = codec busy */

Definition at line 111 of file es137x.h.

◆ STAT_CSTAT

#define STAT_CSTAT

Value:

0x00000400 /* 1 = codec busy or codec write in

* progress */

Definition at line 110 of file es137x.h.

◆ STAT_CWRIP

#define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */

Definition at line 112 of file es137x.h.

◆ STAT_DAC1

#define STAT_DAC1 0x00000004 /* DAC1 int pending */

Definition at line 117 of file es137x.h.

◆ STAT_DAC2

#define STAT_DAC2 0x00000002 /* DAC2 int pending */

Definition at line 118 of file es137x.h.

◆ STAT_INTR

#define STAT_INTR 0x80000000 /* wired or of all interrupt bits */

Definition at line 109 of file es137x.h.

◆ STAT_MCCB

#define STAT_MCCB 0x00000010 /* CCB int pending */

Definition at line 115 of file es137x.h.

◆ STAT_SH_VC

#define STAT_SH_VC 5

Definition at line 114 of file es137x.h.

◆ STAT_UART

#define STAT_UART 0x00000008 /* UART int pending */

Definition at line 116 of file es137x.h.

◆ STAT_VC

#define STAT_VC

Value:

0x00000060 /* CCB int source, 0=DAC1, 1=DAC2,

* 2=ADC, 3=undef */

Definition at line 113 of file es137x.h.

◆ TEST_SPDIF

#define TEST_SPDIF 0x00020000 /* Used to put the S/PDIF module in "test mode" */

Definition at line 178 of file es137x.h.

Macros

Macro Definition Documentation

◆ CODEC_ADSEL

◆ CODEC_CSEL

◆ CODEC_ID_SEMASK

◆ CODEC_ID_SESHIFT

◆ CODEC_INDEX_SHIFT

◆ CODEC_LIMIX1

◆ CODEC_LIMIX2

◆ CODEC_MGAIN

◆ CODEC_OMIX1

◆ CODEC_OMIX2

◆ CODEC_PIADD_MASK

◆ CODEC_PIADD_SHIFT

◆ CODEC_PIDAT_MASK

◆ CODEC_PIDAT_SHIFT

◆ CODEC_PIRD

◆ CODEC_POADD_MASK

◆ CODEC_POADD_SHIFT

◆ CODEC_PODAT_MASK

◆ CODEC_PODAT_SHIFT

◆ CODEC_PORD

◆ CODEC_RDY

◆ CODEC_RES_PD

◆ CODEC_RIMIX1

◆ CODEC_RIMIX2

◆ CODEC_WIP

◆ CTRL_ADC_EN

◆ CTRL_ADC_STOP

◆ CTRL_BREQ

◆ CTRL_CCB_INTRM

◆ CTRL_CDC_EN

◆ CTRL_DAC1_EN

◆ CTRL_DAC2_EN

◆ CTRL_DAC_SYNC

◆ CTRL_JYSTK_EN

◆ CTRL_M_CB

◆ CTRL_M_SBB

◆ CTRL_MSFMTSEL

◆ CTRL_OPEN

◆ CTRL_PCLKDIV

◆ CTRL_SERR_DIS

◆ CTRL_SH_PCLKDIV

◆ CTRL_SH_WTSRSEL

◆ CTRL_UART_EN

◆ CTRL_WTSRSEL

◆ CTRL_XCTL0

◆ CTRL_XCTL1

◆ DAC2_DIVTOSR

◆ DAC2_SRTODIV

◆ ENABLE_SPDIF

◆ ES1370_REG_ADC_FRAMEADR

◆ ES1370_REG_ADC_FRAMECNT

◆ ES1370_REG_ADC_SCOUNT

◆ ES1370_REG_CODEC

◆ ES1370_REG_CONTROL [1/2]

◆ ES1370_REG_CONTROL [2/2]

◆ ES1370_REG_DAC1_FRAMEADR

◆ ES1370_REG_DAC1_FRAMECNT

◆ ES1370_REG_DAC1_SCOUNT

◆ ES1370_REG_DAC2_FRAMEADR

◆ ES1370_REG_DAC2_FRAMECNT

◆ ES1370_REG_DAC2_SCOUNT

◆ ES1370_REG_MEMPAGE

◆ ES1370_REG_SERIAL_CONTROL [1/2]

◆ ES1370_REG_SERIAL_CONTROL [2/2]

◆ ES1370_REG_STATUS

◆ ES1370_REG_UART_CONTROL

◆ ES1370_REG_UART_DATA

◆ ES1370_REG_UART_STATUS

◆ ES1370_REG_UART_TEST

◆ ES1371_DIS_P1

◆ ES1371_DIS_P2

◆ ES1371_DIS_R1

◆ ES1371_DIS_SRC

◆ ES1371_REG_CODEC

◆ ES1371_REG_LEGACY

◆ ES1371_REG_SMPRATE

◆ ES1371_SRC_RAM_ADDRO

◆ ES1371_SRC_RAM_BUSY