103#define VENDORID_SK 0x1148
108#define VENDORID_MARVELL 0x11AB
113#define VENDORID_DLINK 0x1186
118#define DEVICEID_SK_YUKON2 0x9000
119#define DEVICEID_SK_YUKON2_EXPR 0x9e00
124#define DEVICEID_MRVL_8021CU 0x4340
125#define DEVICEID_MRVL_8022CU 0x4341
126#define DEVICEID_MRVL_8061CU 0x4342
127#define DEVICEID_MRVL_8062CU 0x4343
128#define DEVICEID_MRVL_8021X 0x4344
129#define DEVICEID_MRVL_8022X 0x4345
130#define DEVICEID_MRVL_8061X 0x4346
131#define DEVICEID_MRVL_8062X 0x4347
132#define DEVICEID_MRVL_8035 0x4350
133#define DEVICEID_MRVL_8036 0x4351
134#define DEVICEID_MRVL_8038 0x4352
135#define DEVICEID_MRVL_8039 0x4353
136#define DEVICEID_MRVL_8040 0x4354
137#define DEVICEID_MRVL_8040T 0x4355
138#define DEVICEID_MRVL_8042 0x4357
139#define DEVICEID_MRVL_8048 0x435A
140#define DEVICEID_MRVL_4360 0x4360
141#define DEVICEID_MRVL_4361 0x4361
142#define DEVICEID_MRVL_4362 0x4362
143#define DEVICEID_MRVL_4363 0x4363
144#define DEVICEID_MRVL_4364 0x4364
145#define DEVICEID_MRVL_4365 0x4365
146#define DEVICEID_MRVL_436A 0x436A
147#define DEVICEID_MRVL_436B 0x436B
148#define DEVICEID_MRVL_436C 0x436C
149#define DEVICEID_MRVL_436D 0x436D
150#define DEVICEID_MRVL_4370 0x4370
151#define DEVICEID_MRVL_4380 0x4380
152#define DEVICEID_MRVL_4381 0x4381
157#define DEVICEID_DLINK_DGE550SX 0x4001
158#define DEVICEID_DLINK_DGE560SX 0x4002
159#define DEVICEID_DLINK_DGE560T 0x4b00
161#define BIT_31 (1U << 31)
162#define BIT_30 (1 << 30)
163#define BIT_29 (1 << 29)
164#define BIT_28 (1 << 28)
165#define BIT_27 (1 << 27)
166#define BIT_26 (1 << 26)
167#define BIT_25 (1 << 25)
168#define BIT_24 (1 << 24)
169#define BIT_23 (1 << 23)
170#define BIT_22 (1 << 22)
171#define BIT_21 (1 << 21)
172#define BIT_20 (1 << 20)
173#define BIT_19 (1 << 19)
174#define BIT_18 (1 << 18)
175#define BIT_17 (1 << 17)
176#define BIT_16 (1 << 16)
177#define BIT_15 (1 << 15)
178#define BIT_14 (1 << 14)
179#define BIT_13 (1 << 13)
180#define BIT_12 (1 << 12)
181#define BIT_11 (1 << 11)
182#define BIT_10 (1 << 10)
183#define BIT_9 (1 << 9)
184#define BIT_8 (1 << 8)
185#define BIT_7 (1 << 7)
186#define BIT_6 (1 << 6)
187#define BIT_5 (1 << 5)
188#define BIT_4 (1 << 4)
189#define BIT_3 (1 << 3)
190#define BIT_2 (1 << 2)
191#define BIT_1 (1 << 1)
192#define BIT_0 (1 << 0)
194#define SHIFT31(x) ((x) << 31)
195#define SHIFT30(x) ((x) << 30)
196#define SHIFT29(x) ((x) << 29)
197#define SHIFT28(x) ((x) << 28)
198#define SHIFT27(x) ((x) << 27)
199#define SHIFT26(x) ((x) << 26)
200#define SHIFT25(x) ((x) << 25)
201#define SHIFT24(x) ((x) << 24)
202#define SHIFT23(x) ((x) << 23)
203#define SHIFT22(x) ((x) << 22)
204#define SHIFT21(x) ((x) << 21)
205#define SHIFT20(x) ((x) << 20)
206#define SHIFT19(x) ((x) << 19)
207#define SHIFT18(x) ((x) << 18)
208#define SHIFT17(x) ((x) << 17)
209#define SHIFT16(x) ((x) << 16)
210#define SHIFT15(x) ((x) << 15)
211#define SHIFT14(x) ((x) << 14)
212#define SHIFT13(x) ((x) << 13)
213#define SHIFT12(x) ((x) << 12)
214#define SHIFT11(x) ((x) << 11)
215#define SHIFT10(x) ((x) << 10)
216#define SHIFT9(x) ((x) << 9)
217#define SHIFT8(x) ((x) << 8)
218#define SHIFT7(x) ((x) << 7)
219#define SHIFT6(x) ((x) << 6)
220#define SHIFT5(x) ((x) << 5)
221#define SHIFT4(x) ((x) << 4)
222#define SHIFT3(x) ((x) << 3)
223#define SHIFT2(x) ((x) << 2)
224#define SHIFT1(x) ((x) << 1)
225#define SHIFT0(x) ((x) << 0)
230#define PCI_BASE_1ST 0x10
231#define PCI_BASE_2ND 0x14
232#define PCI_OUR_REG_1 0x40
233#define PCI_OUR_REG_2 0x44
234#define PCI_OUR_STATUS 0x7c
235#define PCI_OUR_REG_3 0x80
236#define PCI_OUR_REG_4 0x84
237#define PCI_OUR_REG_5 0x88
238#define PCI_CFG_REG_0 0x90
239#define PCI_CFG_REG_1 0x94
242#define PEX_CAP_ID 0xe0
243#define PEX_NITEM 0xe1
244#define PEX_CAP_REG 0xe2
245#define PEX_DEV_CAP 0xe4
246#define PEX_DEV_CTRL 0xe8
247#define PEX_DEV_STAT 0xea
248#define PEX_LNK_CAP 0xec
249#define PEX_LNK_CTRL 0xf0
250#define PEX_LNK_STAT 0xf2
253#define PEX_ADV_ERR_REP 0x100
254#define PEX_UNC_ERR_STAT 0x104
255#define PEX_UNC_ERR_MASK 0x108
256#define PEX_UNC_ERR_SEV 0x10c
257#define PEX_COR_ERR_STAT 0x110
258#define PEX_COR_ERR_MASK 0x114
259#define PEX_ADV_ERR_CAP_C 0x118
260#define PEX_HEADER_LOG 0x11c
263#define PCI_Y2_PIG_ENA BIT_31
264#define PCI_Y2_DLL_DIS BIT_30
265#define PCI_Y2_PHY2_COMA BIT_29
266#define PCI_Y2_PHY1_COMA BIT_28
267#define PCI_Y2_PHY2_POWD BIT_27
268#define PCI_Y2_PHY1_POWD BIT_26
269#define PCI_DIS_BOOT BIT_24
270#define PCI_EN_IO BIT_23
271#define PCI_EN_FPROM BIT_22
274#define PCI_PAGESIZE (3L<<20)
275#define PCI_PAGE_16 (0L<<20)
276#define PCI_PAGE_32K (1L<<20)
277#define PCI_PAGE_64K (2L<<20)
278#define PCI_PAGE_128K (3L<<20)
279#define PCI_PAGEREG (7L<<16)
280#define PCI_PEX_LEGNAT BIT_15
281#define PCI_FORCE_BE BIT_14
282#define PCI_DIS_MRL BIT_13
283#define PCI_DIS_MRM BIT_12
284#define PCI_DIS_MWI BIT_11
285#define PCI_DISC_CLS BIT_10
286#define PCI_BURST_DIS BIT_9
287#define PCI_DIS_PCI_CLK BIT_8
288#define PCI_SKEW_DAS (0xfL<<4)
289#define PCI_SKEW_BASE 0xfL
290#define PCI_CLS_OPT BIT_3
293#define PCI_VPD_WR_THR (0xff<<24)
294#define PCI_DEV_SEL (0x7f<<17)
295#define PCI_VPD_ROM_SZ (0x07<<14)
297#define PCI_PATCH_DIR (0x0f<<8)
298#define PCI_PATCH_DIR_3 BIT_11
299#define PCI_PATCH_DIR_2 BIT_10
300#define PCI_PATCH_DIR_1 BIT_9
301#define PCI_PATCH_DIR_0 BIT_8
302#define PCI_EXT_PATCHS (0x0f<<4)
303#define PCI_EXT_PATCH_3 BIT_7
304#define PCI_EXT_PATCH_2 BIT_6
305#define PCI_EXT_PATCH_1 BIT_5
306#define PCI_EXT_PATCH_0 BIT_4
307#define PCI_EN_DUMMY_RD BIT_3
308#define PCI_REV_DESC BIT_2
309#define PCI_USEDATA64 BIT_0
312#define PCI_OS_PCI64B BIT_31
313#define PCI_OS_PCIX BIT_30
314#define PCI_OS_MODE_MSK (3<<28)
315#define PCI_OS_PCI66M BIT_27
316#define PCI_OS_PCI_X BIT_26
317#define PCI_OS_DLLE_MSK (3<<24)
318#define PCI_OS_DLLR_MSK (0x0f<<20)
319#define PCI_OS_DLLC_MSK (0x0f<<16)
321#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28)
323#define PCI_OS_SPD_PCI 0
324#define PCI_OS_SPD_X66 1
325#define PCI_OS_SPD_X100 2
326#define PCI_OS_SPD_X133 3
329#define PCI_CLK_MACSEC_DIS BIT_17
332#define PCI_TIMER_VALUE_MSK (0xff<<16)
333#define PCI_FORCE_ASPM_REQUEST BIT_15
334#define PCI_ASPM_GPHY_LINK_DOWN BIT_14
335#define PCI_ASPM_INT_FIFO_EMPTY BIT_13
336#define PCI_ASPM_CLKRUN_REQUEST BIT_12
337#define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4
338#define PCI_ASPM_CLKREQ_PAD_CTL BIT_3
339#define PCI_ASPM_A1_MODE_SELECT BIT_2
340#define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1
341#define PCI_CLK_GATE_ROOT_COR_ENA BIT_0
345#define PCI_CTL_DIV_CORE_CLK_ENA BIT_31
346#define PCI_CTL_SRESET_VMAIN_AV BIT_30
347#define PCI_CTL_BYPASS_VMAIN_AV BIT_29
348#define PCI_CTL_TIM_VMAIN_AV1 BIT_28
349#define PCI_CTL_TIM_VMAIN_AV0 BIT_27
350#define PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27)
352#define PCI_REL_PCIE_RST_DE_ASS BIT_26
353#define PCI_REL_GPHY_REC_PACKET BIT_25
354#define PCI_REL_INT_FIFO_N_EMPTY BIT_24
355#define PCI_REL_MAIN_PWR_AVAIL BIT_23
356#define PCI_REL_CLKRUN_REQ_REL BIT_22
357#define PCI_REL_PCIE_RESET_ASS BIT_21
358#define PCI_REL_PME_ASSERTED BIT_20
359#define PCI_REL_PCIE_EXIT_L1_ST BIT_19
360#define PCI_REL_LOADER_NOT_FIN BIT_18
361#define PCI_REL_PCIE_RX_EX_IDLE BIT_17
362#define PCI_REL_GPHY_LINK_UP BIT_16
364#define PCI_GAT_PCIE_RST_ASSERTED BIT_10
365#define PCI_GAT_GPHY_N_REC_PACKET BIT_9
366#define PCI_GAT_INT_FIFO_EMPTY BIT_8
367#define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7
368#define PCI_GAT_CLKRUN_REQ_REL BIT_6
369#define PCI_GAT_PCIE_RESET_ASS BIT_5
370#define PCI_GAT_PME_DE_ASSERTED BIT_4
371#define PCI_GAT_PCIE_ENTER_L1_ST BIT_3
372#define PCI_GAT_LOADER_FINISHED BIT_2
373#define PCI_GAT_PCIE_RX_EL_IDLE BIT_1
374#define PCI_GAT_GPHY_LINK_DOWN BIT_0
377#define PCI_CF1_DIS_REL_EVT_RST BIT_24
379#define PCI_CF1_REL_LDR_NOT_FIN BIT_23
380#define PCI_CF1_REL_VMAIN_AVLBL BIT_22
381#define PCI_CF1_REL_PCIE_RESET BIT_21
383#define PCI_CF1_GAT_LDR_NOT_FIN BIT_20
384#define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19
385#define PCI_CF1_GAT_PCIE_RESET BIT_18
386#define PCI_CF1_PRST_PHY_CLKREQ BIT_17
387#define PCI_CF1_PCIE_RST_CLKREQ BIT_16
389#define PCI_CF1_ENA_CFG_LDR_DONE BIT_8
390#define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1
391#define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0
394#define PEX_DC_MAX_RRS_MSK (7<<12)
395#define PEX_DC_EN_NO_SNOOP BIT_11
396#define PEX_DC_EN_AUX_POW BIT_10
397#define PEX_DC_EN_PHANTOM BIT_9
398#define PEX_DC_EN_EXT_TAG BIT_8
399#define PEX_DC_MAX_PLS_MSK (7<<5)
400#define PEX_DC_EN_REL_ORD BIT_4
401#define PEX_DC_EN_UNS_RQ_RP BIT_3
402#define PEX_DC_EN_FAT_ER_RP BIT_2
403#define PEX_DC_EN_NFA_ER_RP BIT_1
404#define PEX_DC_EN_COR_ER_RP BIT_0
406#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK)
409#define PEX_LS_SLOT_CLK_CFG BIT_12
410#define PEX_LS_LINK_TRAIN BIT_11
411#define PEX_LS_TRAIN_ERROR BIT_10
412#define PEX_LS_LINK_WI_MSK (0x3f<<4)
413#define PEX_LS_LINK_SP_MSK 0x0f
416#define PEX_UNSUP_REQ BIT_20
417#define PEX_MALFOR_TLP BIT_18
418#define PEX_RX_OV BIT_17
419#define PEX_UNEXP_COMP BIT_16
420#define PEX_COMP_TO BIT_14
421#define PEX_FLOW_CTRL_P BIT_13
422#define PEX_POIS_TLP BIT_12
423#define PEX_DATA_LINK_P BIT_4
425#define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P)
433#define B0_CTST 0x0004
435#define B0_POWER_CTRL 0x0007
436#define B0_ISRC 0x0008
437#define B0_IMSK 0x000c
438#define B0_HWE_ISRC 0x0010
439#define B0_HWE_IMSK 0x0014
440#define B0_SP_ISRC 0x0018
443#define B0_Y2_SP_ISRC2 0x001c
444#define B0_Y2_SP_ISRC3 0x0020
445#define B0_Y2_SP_EISR 0x0024
446#define B0_Y2_SP_LISR 0x0028
447#define B0_Y2_SP_ICR 0x002c
459#define B2_MAC_1 0x0100
460#define B2_MAC_2 0x0108
461#define B2_MAC_3 0x0110
462#define B2_CONN_TYP 0x0118
463#define B2_PMD_TYP 0x0119
464#define B2_MAC_CFG 0x011a
465#define B2_CHIP_ID 0x011b
467#define B2_Y2_CLK_GATE 0x011d
468#define B2_Y2_HW_RES 0x011e
470#define B2_Y2_CLK_CTRL 0x0120
471#define B2_TI_INI 0x0130
472#define B2_TI_VAL 0x0134
473#define B2_TI_CTRL 0x0138
474#define B2_TI_TEST 0x0139
475#define B2_IRQM_INI 0x0140
476#define B2_IRQM_VAL 0x0144
477#define B2_IRQM_CTRL 0x0148
478#define B2_IRQM_TEST 0x0149
479#define B2_IRQM_MSK 0x014c
480#define B2_IRQM_HWE_MSK 0x0150
481#define B2_TST_CTRL1 0x0158
482#define B2_TST_CTRL2 0x0159
483#define B2_GP_IO 0x015c
484#define B2_I2C_CTRL 0x0160
485#define B2_I2C_DATA 0x0164
486#define B2_I2C_IRQ 0x0168
487#define B2_I2C_SW 0x016c
489#define Y2_PEX_PHY_DATA 0x0170
490#define Y2_PEX_PHY_ADDR 0x0172
496#define B3_RAM_ADDR 0x0180
497#define B3_RAM_DATA_LO 0x0184
498#define B3_RAM_DATA_HI 0x0188
500#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6))
509#define B3_RI_WTO_R1 0x0190
510#define B3_RI_WTO_XA1 0x0191
511#define B3_RI_WTO_XS1 0x0192
512#define B3_RI_RTO_R1 0x0193
513#define B3_RI_RTO_XA1 0x0194
514#define B3_RI_RTO_XS1 0x0195
515#define B3_RI_WTO_R2 0x0196
516#define B3_RI_WTO_XA2 0x0197
517#define B3_RI_WTO_XS2 0x0198
518#define B3_RI_RTO_R2 0x0199
519#define B3_RI_RTO_XA2 0x019a
520#define B3_RI_RTO_XS2 0x019b
521#define B3_RI_TO_VAL 0x019c
522#define B3_RI_CTRL 0x01a0
523#define B3_RI_TEST 0x01a2
529#define TXA_ITI_INI 0x0200
530#define TXA_ITI_VAL 0x0204
531#define TXA_LIM_INI 0x0208
532#define TXA_LIM_VAL 0x020c
533#define TXA_CTRL 0x0210
534#define TXA_TEST 0x0211
535#define TXA_STAT 0x0212
537#define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs))
540#define B4_RSS_KEY 0x0220
547#define RSS_KEY_ADDR(Port, KeyIndex) \
548 ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex))
554#define B8_Q_REGS 0x0400
581#define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs))
584#define Y2_B8_PREF_REGS 0x0450
586#define PREF_UNIT_CTRL_REG 0x00
587#define PREF_UNIT_LAST_IDX_REG 0x04
588#define PREF_UNIT_ADDR_LOW_REG 0x08
589#define PREF_UNIT_ADDR_HI_REG 0x0c
590#define PREF_UNIT_GET_IDX_REG 0x10
591#define PREF_UNIT_PUT_IDX_REG 0x14
592#define PREF_UNIT_FIFO_WP_REG 0x20
593#define PREF_UNIT_FIFO_RP_REG 0x24
594#define PREF_UNIT_FIFO_WM_REG 0x28
595#define PREF_UNIT_FIFO_LEV_REG 0x2c
597#define PREF_UNIT_MASK_IDX 0x0fff
599#define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs))
605#define B16_RAM_REGS 0x0800
612#define RB_RX_UTPP 0x10
613#define RB_RX_LTPP 0x14
614#define RB_RX_UTHP 0x18
615#define RB_RX_LTHP 0x1c
626#define RX_GMF_EA 0x0c40
627#define RX_GMF_AF_THR 0x0c44
628#define RX_GMF_CTRL_T 0x0c48
629#define RX_GMF_FL_MSK 0x0c4c
630#define RX_GMF_FL_THR 0x0c50
631#define RX_GMF_TR_THR 0x0c54
632#define RX_GMF_UP_THR 0x0c58
633#define RX_GMF_LP_THR 0x0c5a
634#define RX_GMF_VLAN 0x0c5c
635#define RX_GMF_WP 0x0c60
636#define RX_GMF_WLEV 0x0c68
637#define RX_GMF_RP 0x0c70
638#define RX_GMF_RLEV 0x0c78
650#define TX_GMF_EA 0x0d40
651#define TX_GMF_AE_THR 0x0d44
652#define TX_GMF_CTRL_T 0x0d48
653#define TX_GMF_VLAN 0x0d5c
654#define TX_GMF_WP 0x0d60
655#define TX_GMF_WSP 0x0d64
656#define TX_GMF_WLEV 0x0d68
657#define TX_GMF_RP 0x0d70
658#define TX_GMF_RSTP 0x0d74
659#define TX_GMF_RLEV 0x0d78
671#define B28_DPT_INI 0x0e00
672#define B28_DPT_VAL 0x0e04
673#define B28_DPT_CTRL 0x0e08
674#define B28_DPT_TST 0x0e0a
676#define GMAC_TI_ST_VAL 0x0e14
677#define GMAC_TI_ST_CTRL 0x0e18
678#define GMAC_TI_ST_TST 0x0e1a
680#define POLL_CTRL 0x0e20
681#define POLL_LAST_IDX 0x0e24
682#define POLL_LIST_ADDR_LO 0x0e28
683#define POLL_LIST_ADDR_HI 0x0e2c
685#define B28_Y2_SMB_CONFIG 0x0e40
686#define B28_Y2_SMB_CSD_REG 0x0e44
687#define B28_Y2_CPU_WDOG 0x0e48
688#define B28_Y2_ASF_IRQ_V_BASE 0x0e60
689#define B28_Y2_ASF_STAT_CMD 0x0e68
690#define B28_Y2_ASF_HCU_CCSR 0x0e68
691#define B28_Y2_ASF_HOST_COM 0x0e6c
692#define B28_Y2_DATA_REG_1 0x0e70
693#define B28_Y2_DATA_REG_2 0x0e74
694#define B28_Y2_DATA_REG_3 0x0e78
695#define B28_Y2_DATA_REG_4 0x0e7c
702#define STAT_CTRL 0x0e80
703#define STAT_LAST_IDX 0x0e84
704#define STAT_LIST_ADDR_LO 0x0e88
705#define STAT_LIST_ADDR_HI 0x0e8c
706#define STAT_TXA1_RIDX 0x0e90
707#define STAT_TXS1_RIDX 0x0e92
708#define STAT_TXA2_RIDX 0x0e94
709#define STAT_TXS2_RIDX 0x0e96
710#define STAT_TX_IDX_TH 0x0e98
711#define STAT_PUT_IDX 0x0e9c
713#define STAT_FIFO_WP 0x0ea0
714#define STAT_FIFO_RP 0x0ea4
715#define STAT_FIFO_RSP 0x0ea6
716#define STAT_FIFO_LEVEL 0x0ea8
717#define STAT_FIFO_SHLVL 0x0eaa
718#define STAT_FIFO_WM 0x0eac
719#define STAT_FIFO_ISR_WM 0x0ead
721#define STAT_LEV_TIMER_INI 0x0eb0
722#define STAT_LEV_TIMER_CNT 0x0eb4
723#define STAT_LEV_TIMER_CTRL 0x0eb8
724#define STAT_LEV_TIMER_TEST 0x0eb9
725#define STAT_TX_TIMER_INI 0x0ec0
726#define STAT_TX_TIMER_CNT 0x0ec4
727#define STAT_TX_TIMER_CTRL 0x0ec8
728#define STAT_TX_TIMER_TEST 0x0ec9
729#define STAT_ISR_TIMER_INI 0x0ed0
730#define STAT_ISR_TIMER_CNT 0x0ed4
731#define STAT_ISR_TIMER_CTRL 0x0ed8
732#define STAT_ISR_TIMER_TEST 0x0ed9
734#define ST_LAST_IDX_MASK 0x007f
735#define ST_TXRP_IDX_MASK 0x0fff
736#define ST_TXTH_IDX_MASK 0x0fff
737#define ST_WM_IDX_MASK 0x3f
743#define GMAC_CTRL 0x0f00
744#define GPHY_CTRL 0x0f04
745#define GMAC_IRQ_SRC 0x0f08
746#define GMAC_IRQ_MSK 0x0f0c
747#define GMAC_LINK_CTRL 0x0f10
751#define WOL_REG_OFFS 0x20
753#define WOL_CTRL_STAT 0x0f20
754#define WOL_MATCH_CTL 0x0f22
755#define WOL_MATCH_RES 0x0f23
756#define WOL_MAC_ADDR_LO 0x0f24
757#define WOL_MAC_ADDR_HI 0x0f28
758#define WOL_PATT_PME 0x0f2a
759#define WOL_PATT_ASFM 0x0f2b
760#define WOL_PATT_RPTR 0x0f2c
764#define WOL_PATT_LEN_LO 0x0f30
765#define WOL_PATT_LEN_HI 0x0f34
769#define WOL_PATT_CNT_0 0x0f38
770#define WOL_PATT_CNT_4 0x0f3c
775#define WOL_PATT_RAM_1 0x1000
776#define WOL_PATT_RAM_2 0x1400
779#define Y2_CFG_SPC 0x1c00
780#define BASE_GMAC_1 0x2800
781#define BASE_GMAC_2 0x3800
787#define Y2_VMAIN_AVAIL BIT_17
788#define Y2_VAUX_AVAIL BIT_16
789#define Y2_HW_WOL_ON BIT_15
790#define Y2_HW_WOL_OFF BIT_14
791#define Y2_ASF_ENABLE BIT_13
792#define Y2_ASF_DISABLE BIT_12
793#define Y2_CLK_RUN_ENA BIT_11
794#define Y2_CLK_RUN_DIS BIT_10
795#define Y2_LED_STAT_ON BIT_9
796#define Y2_LED_STAT_OFF BIT_8
797#define CS_ST_SW_IRQ BIT_7
798#define CS_CL_SW_IRQ BIT_6
799#define CS_STOP_DONE BIT_5
800#define CS_STOP_MAST BIT_4
801#define CS_MRST_CLR BIT_3
802#define CS_MRST_SET BIT_2
803#define CS_RST_CLR BIT_1
804#define CS_RST_SET BIT_0
806#define LED_STAT_ON BIT_1
807#define LED_STAT_OFF BIT_0
810#define PC_VAUX_ENA BIT_7
811#define PC_VAUX_DIS BIT_6
812#define PC_VCC_ENA BIT_5
813#define PC_VCC_DIS BIT_4
814#define PC_VAUX_ON BIT_3
815#define PC_VAUX_OFF BIT_2
816#define PC_VCC_ON BIT_1
817#define PC_VCC_OFF BIT_0
827#define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8))
828#define Y2_IS_HW_ERR BIT_31
829#define Y2_IS_STAT_BMU BIT_30
830#define Y2_IS_ASF BIT_29
831#define Y2_IS_POLL_CHK BIT_27
832#define Y2_IS_TWSI_RDY BIT_26
833#define Y2_IS_IRQ_SW BIT_25
834#define Y2_IS_TIMINT BIT_24
835#define Y2_IS_IRQ_PHY2 BIT_12
836#define Y2_IS_IRQ_MAC2 BIT_11
837#define Y2_IS_CHK_RX2 BIT_10
838#define Y2_IS_CHK_TXS2 BIT_9
839#define Y2_IS_CHK_TXA2 BIT_8
840#define Y2_IS_PSM_ACK BIT_7
841#define Y2_IS_PTP_TIST BIT_6
842#define Y2_IS_PHY_QLNK BIT_5
843#define Y2_IS_IRQ_PHY1 BIT_4
844#define Y2_IS_IRQ_MAC1 BIT_3
845#define Y2_IS_CHK_RX1 BIT_2
846#define Y2_IS_CHK_TXS1 BIT_1
847#define Y2_IS_CHK_TXA1 BIT_0
849#define Y2_IS_L1_MASK 0x0000001f
851#define Y2_IS_L2_MASK 0x00001f00
853#define Y2_IS_ALL_MSK 0xef001f1f
855#define Y2_IS_PORT_A \
856 (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1)
857#define Y2_IS_PORT_B \
858 (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2)
863#define Y2_IS_TIST_OV BIT_29
864#define Y2_IS_SENSOR BIT_28
865#define Y2_IS_MST_ERR BIT_27
866#define Y2_IS_IRQ_STAT BIT_26
867#define Y2_IS_PCI_EXP BIT_25
868#define Y2_IS_PCI_NEXP BIT_24
869#define Y2_IS_PAR_RD2 BIT_13
870#define Y2_IS_PAR_WR2 BIT_12
871#define Y2_IS_PAR_MAC2 BIT_11
872#define Y2_IS_PAR_RX2 BIT_10
873#define Y2_IS_TCP_TXS2 BIT_9
874#define Y2_IS_TCP_TXA2 BIT_8
875#define Y2_IS_PAR_RD1 BIT_5
876#define Y2_IS_PAR_WR1 BIT_4
877#define Y2_IS_PAR_MAC1 BIT_3
878#define Y2_IS_PAR_RX1 BIT_2
879#define Y2_IS_TCP_TXS1 BIT_1
880#define Y2_IS_TCP_TXA1 BIT_0
882#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\
883 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1)
884#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\
885 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2)
887#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | Y2_IS_MST_ERR |\
888 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |\
889 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK)
892#define CFG_CHIP_R_MSK (0x0f<<4)
893#define CFG_DIS_M2_CLK BIT_1
894#define CFG_SNG_MAC BIT_0
897#define CHIP_ID_GENESIS 0x0a
898#define CHIP_ID_YUKON 0xb0
899#define CHIP_ID_YUKON_LITE 0xb1
900#define CHIP_ID_YUKON_LP 0xb2
901#define CHIP_ID_YUKON_XL 0xb3
902#define CHIP_ID_YUKON_EC_U 0xb4
903#define CHIP_ID_YUKON_EX 0xb5
904#define CHIP_ID_YUKON_EC 0xb6
905#define CHIP_ID_YUKON_FE 0xb7
906#define CHIP_ID_YUKON_FE_P 0xb8
907#define CHIP_ID_YUKON_SUPR 0xb9
908#define CHIP_ID_YUKON_UL_2 0xba
909#define CHIP_ID_YUKON_UNKNOWN 0xbb
910#define CHIP_ID_YUKON_OPT 0xbc
912#define CHIP_REV_YU_XL_A0 0
913#define CHIP_REV_YU_XL_A1 1
914#define CHIP_REV_YU_XL_A2 2
915#define CHIP_REV_YU_XL_A3 3
917#define CHIP_REV_YU_EC_A1 0
918#define CHIP_REV_YU_EC_A2 1
919#define CHIP_REV_YU_EC_A3 2
921#define CHIP_REV_YU_EC_U_A0 1
922#define CHIP_REV_YU_EC_U_A1 2
924#define CHIP_REV_YU_FE_P_A0 0
926#define CHIP_REV_YU_EX_A0 1
927#define CHIP_REV_YU_EX_B0 2
929#define CHIP_REV_YU_SU_A0 0
930#define CHIP_REV_YU_SU_B0 1
931#define CHIP_REV_YU_SU_B1 3
934#define Y2_STATUS_LNK2_INAC BIT_7
935#define Y2_CLK_GAT_LNK2_DIS BIT_6
936#define Y2_COR_CLK_LNK2_DIS BIT_5
937#define Y2_PCI_CLK_LNK2_DIS BIT_4
938#define Y2_STATUS_LNK1_INAC BIT_3
939#define Y2_CLK_GAT_LNK1_DIS BIT_2
940#define Y2_COR_CLK_LNK1_DIS BIT_1
941#define Y2_PCI_CLK_LNK1_DIS BIT_0
944#define CFG_LED_MODE_MSK (0x07<<2)
945#define CFG_LINK_2_AVAIL BIT_1
946#define CFG_LINK_1_AVAIL BIT_0
948#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
949#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
952#define B2_E3_RES_MASK 0x0f
956#define Y2_CLK_DIV_VAL_MSK (0xff<<16)
957#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK)
959#define Y2_CLK_DIV_VAL2_MSK (0x07<<21)
960#define Y2_CLK_SELECT2_MSK (0x1f<<16)
961#define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK)
962#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK)
963#define Y2_CLK_DIV_ENA BIT_1
964#define Y2_CLK_DIV_DIS BIT_0
968#define TIM_START BIT_2
969#define TIM_STOP BIT_1
970#define TIM_CLR_IRQ BIT_0
975#define TIM_T_ON BIT_2
976#define TIM_T_OFF BIT_1
977#define TIM_T_STEP BIT_0
981#define DPT_MSK 0x00ffffff
984#define DPT_START BIT_1
985#define DPT_STOP BIT_0
988#define TST_FRC_DPERR_MR BIT_7
989#define TST_FRC_DPERR_MW BIT_6
990#define TST_FRC_DPERR_TR BIT_5
991#define TST_FRC_DPERR_TW BIT_4
992#define TST_FRC_APERR_M BIT_3
993#define TST_FRC_APERR_T BIT_2
994#define TST_CFG_WRITE_ON BIT_1
995#define TST_CFG_WRITE_OFF BIT_0
998#define GLB_GPIO_CLK_DEB_ENA BIT_31
999#define GLB_GPIO_CLK_DBG_MSK 0x3c000000
1001#define GLB_GPIO_INT_RST_D3_DIS BIT_15
1002#define GLB_GPIO_LED_PAD_SPEED_UP BIT_14
1003#define GLB_GPIO_STAT_RACE_DIS BIT_13
1004#define GLB_GPIO_TEST_SEL_MSK 0x00001800
1005#define GLB_GPIO_TEST_SEL_BASE BIT_11
1006#define GLB_GPIO_RAND_ENA BIT_10
1007#define GLB_GPIO_RAND_BIT_1 BIT_9
1010#define I2C_FLAG BIT_31
1011#define I2C_ADDR (0x7fff<<16)
1012#define I2C_DEV_SEL (0x7f<<9)
1013#define I2C_BURST_LEN BIT_4
1014#define I2C_DEV_SIZE (7<<1)
1015#define I2C_025K_DEV (0<<1)
1016#define I2C_05K_DEV (1<<1)
1017#define I2C_1K_DEV (2<<1)
1018#define I2C_2K_DEV (3<<1)
1019#define I2C_4K_DEV (4<<1)
1020#define I2C_8K_DEV (5<<1)
1021#define I2C_16K_DEV (6<<1)
1022#define I2C_32K_DEV (7<<1)
1023#define I2C_STOP BIT_0
1026#define I2C_CLR_IRQ BIT_0
1029#define I2C_DATA_DIR BIT_2
1030#define I2C_DATA BIT_1
1031#define I2C_CLK BIT_0
1034#define I2C_SENS_ADDR LM80_ADDR
1038#define BSC_START BIT_1
1039#define BSC_STOP BIT_0
1042#define BSC_SRC BIT_0
1045#define BSC_T_ON BIT_2
1046#define BSC_T_OFF BIT_1
1047#define BSC_T_STEP BIT_0
1050#define PEX_RD_ACCESS BIT_31
1051#define PEX_DB_ACCESS BIT_30
1054#define RAM_ADR_RAN 0x0007ffff
1058#define RI_CLR_RD_PERR BIT_9
1059#define RI_CLR_WR_PERR BIT_8
1060#define RI_RST_CLR BIT_1
1061#define RI_RST_SET BIT_0
1063#define MSK_RI_TO_53 36
1070#define TXA_MAX_VAL 0x00ffffff
1073#define TXA_ENA_FSYNC BIT_7
1074#define TXA_DIS_FSYNC BIT_6
1075#define TXA_ENA_ALLOC BIT_5
1076#define TXA_DIS_ALLOC BIT_4
1077#define TXA_START_RC BIT_3
1078#define TXA_STOP_RC BIT_2
1079#define TXA_ENA_ARB BIT_1
1080#define TXA_DIS_ARB BIT_0
1083#define TXA_INT_T_ON BIT_5
1084#define TXA_INT_T_OFF BIT_4
1085#define TXA_INT_T_STEP BIT_3
1086#define TXA_LIM_T_ON BIT_2
1087#define TXA_LIM_T_OFF BIT_1
1088#define TXA_LIM_T_STEP BIT_0
1091#define TXA_PRIO_XS BIT_0
1094#define BC_MAX 0xffff
1097#define BMU_IDLE BIT_31
1098#define BMU_RX_TCP_PKT BIT_30
1099#define BMU_RX_IP_PKT BIT_29
1100#define BMU_ENA_RX_RSS_HASH BIT_15
1101#define BMU_DIS_RX_RSS_HASH BIT_14
1102#define BMU_ENA_RX_CHKSUM BIT_13
1103#define BMU_DIS_RX_CHKSUM BIT_12
1104#define BMU_CLR_IRQ_PAR BIT_11
1105#define BMU_CLR_IRQ_TCP BIT_11
1106#define BMU_CLR_IRQ_CHK BIT_10
1107#define BMU_STOP BIT_9
1108#define BMU_START BIT_8
1109#define BMU_FIFO_OP_ON BIT_7
1110#define BMU_FIFO_OP_OFF BIT_6
1111#define BMU_FIFO_ENA BIT_5
1112#define BMU_FIFO_RST BIT_4
1113#define BMU_OP_ON BIT_3
1114#define BMU_OP_OFF BIT_2
1115#define BMU_RST_CLR BIT_1
1116#define BMU_RST_SET BIT_0
1118#define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR)
1119#define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | \
1120 BMU_START | BMU_FIFO_ENA | BMU_OP_ON)
1124#define BMU_TX_IPIDINCR_ON BIT_13
1125#define BMU_TX_IPIDINCR_OFF BIT_12
1126#define BMU_TX_CLR_IRQ_TCP BIT_11
1130#define F_TX_CHK_AUTO_OFF BIT_31
1131#define F_TX_CHK_AUTO_ON BIT_30
1132#define F_ALM_FULL BIT_28
1133#define F_EMPTY BIT_27
1134#define F_FIFO_EOF BIT_26
1135#define F_WM_REACHED BIT_25
1136#define F_M_RX_RAM_DIS BIT_24
1137#define F_FIFO_LEVEL (0x1f<<16)
1139#define F_WATER_MARK 0x0007ff
1143#define PREF_UNIT_OP_ON BIT_3
1144#define PREF_UNIT_OP_OFF BIT_2
1145#define PREF_UNIT_RST_CLR BIT_1
1146#define PREF_UNIT_RST_SET BIT_0
1159#define RB_MSK 0x0007ffff
1162#define RB_PC_DEC BIT_3
1163#define RB_PC_T_ON BIT_2
1164#define RB_PC_T_OFF BIT_1
1165#define RB_PC_INC BIT_0
1168#define RB_WP_T_ON BIT_6
1169#define RB_WP_T_OFF BIT_5
1170#define RB_WP_INC BIT_4
1171#define RB_RP_T_ON BIT_2
1172#define RB_RP_T_OFF BIT_1
1173#define RB_RP_INC BIT_0
1176#define RB_ENA_STFWD BIT_5
1177#define RB_DIS_STFWD BIT_4
1178#define RB_ENA_OP_MD BIT_3
1179#define RB_DIS_OP_MD BIT_2
1180#define RB_RST_CLR BIT_1
1181#define RB_RST_SET BIT_0
1184#define MSK_RB_ULPP (8 * 1024)
1185#define MSK_RB_LLPP_S (10 * 1024)
1186#define MSK_RB_LLPP_B (16 * 1024)
1189#define MSK_ECU_ULPP 0x0080
1190#define MSK_ECU_LLPP 0x0060
1191#define MSK_ECU_AE_THR 0x0070
1192#define MSK_ECU_TXFF_LEV 0x01a0
1193#define MSK_ECU_JUMBO_WM 0x01
1195#define MSK_BMU_RX_WM 0x600
1196#define MSK_BMU_TX_WM 0x600
1198#define MSK_BMU_RX_WM_PEX 0x600
1208#define Q_ASF_R1 0x100
1209#define Q_ASF_R2 0x180
1210#define Q_ASF_T1 0x140
1211#define Q_ASF_T2 0x1c0
1213#define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs))
1216#define MSK_MIN_RXQ_SIZE 10
1218#define MSK_MIN_TXQ_SIZE 10
1220#define MSK_RAM_QUOTA_RX 80
1223#define WOL_CTL_LINK_CHG_OCC BIT_15
1224#define WOL_CTL_MAGIC_PKT_OCC BIT_14
1225#define WOL_CTL_PATTERN_OCC BIT_13
1226#define WOL_CTL_CLEAR_RESULT BIT_12
1227#define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11
1228#define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10
1229#define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9
1230#define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8
1231#define WOL_CTL_ENA_PME_ON_PATTERN BIT_7
1232#define WOL_CTL_DIS_PME_ON_PATTERN BIT_6
1233#define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5
1234#define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4
1235#define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3
1236#define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2
1237#define WOL_CTL_ENA_PATTERN_UNIT BIT_1
1238#define WOL_CTL_DIS_PATTERN_UNIT BIT_0
1240#define WOL_CTL_DEFAULT \
1241 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1242 WOL_CTL_DIS_PME_ON_PATTERN | \
1243 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1244 WOL_CTL_DIS_LINK_CHG_UNIT | \
1245 WOL_CTL_DIS_PATTERN_UNIT | \
1246 WOL_CTL_DIS_MAGIC_PKT_UNIT)
1249#define WOL_CTL_PATT_ENA(x) (BIT_0 << (x))
1252#define WOL_PATT_FORCE_PME BIT_7
1253#define WOL_PATT_MATCH_PME_ALL 0x7f
1259#define PHY_MARV_CTRL 0x00
1260#define PHY_MARV_STAT 0x01
1261#define PHY_MARV_ID0 0x02
1262#define PHY_MARV_ID1 0x03
1263#define PHY_MARV_AUNE_ADV 0x04
1264#define PHY_MARV_AUNE_LP 0x05
1265#define PHY_MARV_AUNE_EXP 0x06
1266#define PHY_MARV_NEPG 0x07
1267#define PHY_MARV_NEPG_LP 0x08
1269#define PHY_MARV_1000T_CTRL 0x09
1270#define PHY_MARV_1000T_STAT 0x0a
1272#define PHY_MARV_EXT_STAT 0x0f
1273#define PHY_MARV_PHY_CTRL 0x10
1274#define PHY_MARV_PHY_STAT 0x11
1275#define PHY_MARV_INT_MASK 0x12
1276#define PHY_MARV_INT_STAT 0x13
1277#define PHY_MARV_EXT_CTRL 0x14
1278#define PHY_MARV_RXE_CNT 0x15
1279#define PHY_MARV_EXT_ADR 0x16
1280#define PHY_MARV_PORT_IRQ 0x17
1281#define PHY_MARV_LED_CTRL 0x18
1282#define PHY_MARV_LED_OVER 0x19
1283#define PHY_MARV_EXT_CTRL_2 0x1a
1284#define PHY_MARV_EXT_P_STAT 0x1b
1285#define PHY_MARV_CABLE_DIAG 0x1c
1286#define PHY_MARV_PAGE_ADDR 0x1d
1287#define PHY_MARV_PAGE_DATA 0x1e
1290#define PHY_MARV_FE_LED_PAR 0x16
1291#define PHY_MARV_FE_LED_SER 0x17
1292#define PHY_MARV_FE_VCT_TX 0x1a
1293#define PHY_MARV_FE_VCT_RX 0x1b
1294#define PHY_MARV_FE_SPEC_2 0x1c
1296#define PHY_CT_RESET (1<<15)
1297#define PHY_CT_LOOP (1<<14)
1298#define PHY_CT_SPS_LSB (1<<13)
1299#define PHY_CT_ANE (1<<12)
1300#define PHY_CT_PDOWN (1<<11)
1301#define PHY_CT_ISOL (1<<10)
1302#define PHY_CT_RE_CFG (1<<9)
1303#define PHY_CT_DUP_MD (1<<8)
1304#define PHY_CT_COL_TST (1<<7)
1305#define PHY_CT_SPS_MSB (1<<6)
1307#define PHY_CT_SP1000 PHY_CT_SPS_MSB
1308#define PHY_CT_SP100 PHY_CT_SPS_LSB
1309#define PHY_CT_SP10 (0)
1311#define PHY_ST_EXT_ST (1<<8)
1312#define PHY_ST_PRE_SUP (1<<6)
1313#define PHY_ST_AN_OVER (1<<5)
1314#define PHY_ST_REM_FLT (1<<4)
1315#define PHY_ST_AN_CAP (1<<3)
1316#define PHY_ST_LSYNC (1<<2)
1317#define PHY_ST_JAB_DET (1<<1)
1318#define PHY_ST_EXT_REG (1<<0)
1320#define PHY_I1_OUI_MSK (0x3f<<10)
1321#define PHY_I1_MOD_NUM (0x3f<<4)
1322#define PHY_I1_REV_MSK 0xf
1325#define PHY_MARV_ID0_VAL 0x0141
1327#define PHY_MARV_ID1_B0 0x0C23
1328#define PHY_MARV_ID1_B2 0x0C25
1329#define PHY_MARV_ID1_C2 0x0CC2
1330#define PHY_MARV_ID1_Y2 0x0C91
1331#define PHY_MARV_ID1_FE 0x0C83
1332#define PHY_MARV_ID1_ECU 0x0CB0
1335#define PHY_B_1000S_MSF (1<<15)
1336#define PHY_B_1000S_MSR (1<<14)
1337#define PHY_B_1000S_LRS (1<<13)
1338#define PHY_B_1000S_RRS (1<<12)
1339#define PHY_B_1000S_LP_FD (1<<11)
1340#define PHY_B_1000S_LP_HD (1<<10)
1341#define PHY_B_1000S_IEC 0xff
1345#define PHY_M_AN_NXT_PG BIT_15
1346#define PHY_M_AN_ACK BIT_14
1347#define PHY_M_AN_RF BIT_13
1348#define PHY_M_AN_ASP BIT_11
1349#define PHY_M_AN_PC BIT_10
1350#define PHY_M_AN_100_T4 BIT_9
1351#define PHY_M_AN_100_FD BIT_8
1352#define PHY_M_AN_100_HD BIT_7
1353#define PHY_M_AN_10_FD BIT_6
1354#define PHY_M_AN_10_HD BIT_5
1355#define PHY_M_AN_SEL_MSK (0x1f<<4)
1358#define PHY_M_AN_ASP_X BIT_8
1359#define PHY_M_AN_PC_X BIT_7
1360#define PHY_M_AN_1000X_AHD BIT_6
1361#define PHY_M_AN_1000X_AFD BIT_5
1364#define PHY_M_P_NO_PAUSE_X (0<<7)
1365#define PHY_M_P_SYM_MD_X (1<<7)
1366#define PHY_M_P_ASYM_MD_X (2<<7)
1367#define PHY_M_P_BOTH_MD_X (3<<7)
1370#define PHY_M_1000C_TEST (7<<13)
1371#define PHY_M_1000C_MSE BIT_12
1372#define PHY_M_1000C_MSC BIT_11
1373#define PHY_M_1000C_MPD BIT_10
1374#define PHY_M_1000C_AFD BIT_9
1375#define PHY_M_1000C_AHD BIT_8
1378#define PHY_M_PC_TX_FFD_MSK (3<<14)
1379#define PHY_M_PC_RX_FFD_MSK (3<<12)
1380#define PHY_M_PC_ASS_CRS_TX BIT_11
1381#define PHY_M_PC_FL_GOOD BIT_10
1382#define PHY_M_PC_EN_DET_MSK (3<<8)
1383#define PHY_M_PC_ENA_EXT_D BIT_7
1384#define PHY_M_PC_MDIX_MSK (3<<5)
1385#define PHY_M_PC_DIS_125CLK BIT_4
1386#define PHY_M_PC_MAC_POW_UP BIT_3
1387#define PHY_M_PC_SQE_T_ENA BIT_2
1388#define PHY_M_PC_POL_R_DIS BIT_1
1389#define PHY_M_PC_DIS_JABBER BIT_0
1391#define PHY_M_PC_EN_DET SHIFT8(2)
1392#define PHY_M_PC_EN_DET_PLUS SHIFT8(3)
1394#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK)
1396#define PHY_M_PC_MAN_MDI 0
1397#define PHY_M_PC_MAN_MDIX 1
1398#define PHY_M_PC_ENA_AUTO 3
1401#define PHY_M_PC_DIS_LINK_P BIT_15
1402#define PHY_M_PC_DSC_MSK (7<<12)
1403#define PHY_M_PC_DOWN_S_ENA BIT_11
1406#define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK)
1411#define PHY_M_PC_ENA_DTE_DT BIT_15
1412#define PHY_M_PC_ENA_ENE_DT BIT_14
1413#define PHY_M_PC_DIS_NLP_CK BIT_13
1414#define PHY_M_PC_ENA_LIP_NP BIT_12
1415#define PHY_M_PC_DIS_NLP_GN BIT_11
1416#define PHY_M_PC_DIS_SCRAMB BIT_9
1417#define PHY_M_PC_DIS_FEFI BIT_8
1418#define PHY_M_PC_SH_TP_SEL BIT_6
1419#define PHY_M_PC_RX_FD_MSK (3<<2)
1422#define PHY_M_PS_SPEED_MSK (3<<14)
1423#define PHY_M_PS_SPEED_1000 BIT_15
1424#define PHY_M_PS_SPEED_100 BIT_14
1425#define PHY_M_PS_SPEED_10 0
1426#define PHY_M_PS_FULL_DUP BIT_13
1427#define PHY_M_PS_PAGE_REC BIT_12
1428#define PHY_M_PS_SPDUP_RES BIT_11
1429#define PHY_M_PS_LINK_UP BIT_10
1430#define PHY_M_PS_CABLE_MSK (7<<7)
1431#define PHY_M_PS_MDI_X_STAT BIT_6
1432#define PHY_M_PS_DOWNS_STAT BIT_5
1433#define PHY_M_PS_ENDET_STAT BIT_4
1434#define PHY_M_PS_TX_P_EN BIT_3
1435#define PHY_M_PS_RX_P_EN BIT_2
1436#define PHY_M_PS_POL_REV BIT_1
1437#define PHY_M_PS_JABBER BIT_0
1439#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1442#define PHY_M_PS_DTE_DETECT BIT_15
1443#define PHY_M_PS_RES_SPEED BIT_14
1447#define PHY_M_IS_AN_ERROR BIT_15
1448#define PHY_M_IS_LSP_CHANGE BIT_14
1449#define PHY_M_IS_DUP_CHANGE BIT_13
1450#define PHY_M_IS_AN_PR BIT_12
1451#define PHY_M_IS_AN_COMPL BIT_11
1452#define PHY_M_IS_LST_CHANGE BIT_10
1453#define PHY_M_IS_SYMB_ERROR BIT_9
1454#define PHY_M_IS_FALSE_CARR BIT_8
1455#define PHY_M_IS_FIFO_ERROR BIT_7
1456#define PHY_M_IS_MDI_CHANGE BIT_6
1457#define PHY_M_IS_DOWNSH_DET BIT_5
1458#define PHY_M_IS_END_CHANGE BIT_4
1459#define PHY_M_IS_DTE_CHANGE BIT_2
1460#define PHY_M_IS_POL_CHANGE BIT_1
1461#define PHY_M_IS_JABBER BIT_0
1463#define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \
1464 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
1467#define PHY_M_EC_ENA_BC_EXT BIT_15
1468#define PHY_M_EC_ENA_LIN_LB BIT_14
1469#define PHY_M_EC_DIS_LINK_P BIT_12
1470#define PHY_M_EC_M_DSC_MSK (3<<10)
1472#define PHY_M_EC_S_DSC_MSK (3<<8)
1474#define PHY_M_EC_DSC_MSK_2 (7<<9)
1476#define PHY_M_EC_DOWN_S_ENA BIT_8
1478#define PHY_M_EC_RX_TIM_CT BIT_7
1479#define PHY_M_EC_MAC_S_MSK (7<<4)
1480#define PHY_M_EC_FIB_AN_ENA BIT_3
1481#define PHY_M_EC_DTE_D_ENA BIT_2
1482#define PHY_M_EC_TX_TIM_CT BIT_1
1483#define PHY_M_EC_TRANS_DIS BIT_0
1485#define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK)
1487#define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK)
1489#define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK)
1492#define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2)
1495#define MAC_TX_CLK_0_MHZ 2
1496#define MAC_TX_CLK_2_5_MHZ 6
1497#define MAC_TX_CLK_25_MHZ 7
1500#define PHY_M_LEDC_DIS_LED BIT_15
1501#define PHY_M_LEDC_PULS_MSK (7<<12)
1502#define PHY_M_LEDC_F_INT BIT_11
1503#define PHY_M_LEDC_BL_R_MSK (7<<8)
1504#define PHY_M_LEDC_DP_C_LSB BIT_7
1505#define PHY_M_LEDC_TX_C_LSB BIT_6
1506#define PHY_M_LEDC_LK_C_MSK (7<<3)
1508#define PHY_M_LEDC_LINK_MSK (3<<3)
1510#define PHY_M_LEDC_DP_CTRL BIT_2
1511#define PHY_M_LEDC_DP_C_MSB BIT_2
1512#define PHY_M_LEDC_RX_CTRL BIT_1
1513#define PHY_M_LEDC_TX_CTRL BIT_0
1514#define PHY_M_LEDC_TX_C_MSB BIT_0
1516#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK)
1518#define PULS_NO_STR 0
1525#define PULS_1300MS 7
1527#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK)
1531#define BLINK_170MS 2
1532#define BLINK_340MS 3
1533#define BLINK_670MS 4
1536#define PHY_M_LED_MO_SGMII(x) SHIFT14(x)
1537#define PHY_M_LED_MO_DUP(x) SHIFT10(x)
1538#define PHY_M_LED_MO_10(x) SHIFT8(x)
1539#define PHY_M_LED_MO_100(x) SHIFT6(x)
1540#define PHY_M_LED_MO_1000(x) SHIFT4(x)
1541#define PHY_M_LED_MO_RX(x) SHIFT2(x)
1542#define PHY_M_LED_MO_TX(x) SHIFT0(x)
1544#define MO_LED_NORM 0
1545#define MO_LED_BLINK 1
1550#define PHY_M_EC2_FI_IMPED BIT_6
1551#define PHY_M_EC2_FO_IMPED BIT_5
1552#define PHY_M_EC2_FO_M_CLK BIT_4
1553#define PHY_M_EC2_FO_BOOST BIT_3
1554#define PHY_M_EC2_FO_AM_MSK 7
1557#define PHY_M_FC_AUTO_SEL BIT_15
1558#define PHY_M_FC_AN_REG_ACC BIT_14
1559#define PHY_M_FC_RESOLUTION BIT_13
1560#define PHY_M_SER_IF_AN_BP BIT_12
1561#define PHY_M_SER_IF_BP_ST BIT_11
1562#define PHY_M_IRQ_POLARITY BIT_10
1563#define PHY_M_DIS_AUT_MED BIT_9
1565#define PHY_M_UNDOC1 BIT_7
1566#define PHY_M_DTE_POW_STAT BIT_4
1567#define PHY_M_MODE_MASK 0xf
1570#define PHY_M_CABD_ENA_TEST BIT_15
1571#define PHY_M_CABD_DIS_WAIT BIT_15
1573#define PHY_M_CABD_STAT_MSK (3<<13)
1574#define PHY_M_CABD_AMPL_MSK (0x1f<<8)
1576#define PHY_M_CABD_DIST_MSK 0xff
1579#define CABD_STAT_NORMAL 0
1580#define CABD_STAT_SHORT 1
1581#define CABD_STAT_OPEN 2
1582#define CABD_STAT_FAIL 3
1586#define PHY_M_FELP_LED2_MSK (0xf<<8)
1587#define PHY_M_FELP_LED1_MSK (0xf<<4)
1588#define PHY_M_FELP_LED0_MSK 0xf
1590#define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK)
1591#define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK)
1592#define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK)
1594#define LED_PAR_CTRL_COLX 0x00
1595#define LED_PAR_CTRL_ERROR 0x01
1596#define LED_PAR_CTRL_DUPLEX 0x02
1597#define LED_PAR_CTRL_DP_COL 0x03
1598#define LED_PAR_CTRL_SPEED 0x04
1599#define LED_PAR_CTRL_LINK 0x05
1600#define LED_PAR_CTRL_TX 0x06
1601#define LED_PAR_CTRL_RX 0x07
1602#define LED_PAR_CTRL_ACT 0x08
1603#define LED_PAR_CTRL_LNK_RX 0x09
1604#define LED_PAR_CTRL_LNK_AC 0x0a
1605#define LED_PAR_CTRL_ACT_BL 0x0b
1606#define LED_PAR_CTRL_TX_BL 0x0c
1607#define LED_PAR_CTRL_RX_BL 0x0d
1608#define LED_PAR_CTRL_COL_BL 0x0e
1609#define LED_PAR_CTRL_INACT 0x0f
1612#define PHY_M_FESC_DIS_WAIT BIT_2
1613#define PHY_M_FESC_ENA_MCLK BIT_1
1614#define PHY_M_FESC_SEL_CL_A BIT_0
1618#define PHY_M_FIB_FORCE_LNK BIT_10
1619#define PHY_M_FIB_SIGD_POL BIT_9
1620#define PHY_M_FIB_TX_DIS BIT_3
1623#define PHY_M_MAC_MD_MSK (7<<7)
1624#define PHY_M_MAC_MD_AUTO 3
1625#define PHY_M_MAC_MD_COPPER 5
1626#define PHY_M_MAC_MD_1000BX 7
1627#define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK)
1630#define PHY_M_LEDC_LOS_MSK (0xf<<12)
1631#define PHY_M_LEDC_INIT_MSK (0xf<<8)
1632#define PHY_M_LEDC_STA1_MSK (0xf<<4)
1633#define PHY_M_LEDC_STA0_MSK 0xf
1635#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK)
1636#define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK)
1637#define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK)
1638#define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK)
1641#define PHY_M_POLC_LS1M_MSK (0xf<<12)
1642#define PHY_M_POLC_IS0M_MSK (0xf<<8)
1643#define PHY_M_POLC_LOS_MSK (0x3<<6)
1644#define PHY_M_POLC_INIT_MSK (0x3<<4)
1645#define PHY_M_POLC_STA1_MSK (0x3<<2)
1646#define PHY_M_POLC_STA0_MSK 0x3
1648#define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK)
1649#define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK)
1650#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK)
1651#define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK)
1652#define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK)
1653#define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK)
1666#define GM_GP_STAT 0x0000
1667#define GM_GP_CTRL 0x0004
1668#define GM_TX_CTRL 0x0008
1669#define GM_RX_CTRL 0x000c
1670#define GM_TX_FLOW_CTRL 0x0010
1671#define GM_TX_PARAM 0x0014
1672#define GM_SERIAL_MODE 0x0018
1675#define GM_SRC_ADDR_1L 0x001c
1676#define GM_SRC_ADDR_1M 0x0020
1677#define GM_SRC_ADDR_1H 0x0024
1678#define GM_SRC_ADDR_2L 0x0028
1679#define GM_SRC_ADDR_2M 0x002c
1680#define GM_SRC_ADDR_2H 0x0030
1683#define GM_MC_ADDR_H1 0x0034
1684#define GM_MC_ADDR_H2 0x0038
1685#define GM_MC_ADDR_H3 0x003c
1686#define GM_MC_ADDR_H4 0x0040
1689#define GM_TX_IRQ_SRC 0x0044
1690#define GM_RX_IRQ_SRC 0x0048
1691#define GM_TR_IRQ_SRC 0x004c
1694#define GM_TX_IRQ_MSK 0x0050
1695#define GM_RX_IRQ_MSK 0x0054
1696#define GM_TR_IRQ_MSK 0x0058
1699#define GM_SMI_CTRL 0x0080
1700#define GM_SMI_DATA 0x0084
1701#define GM_PHY_ADDR 0x0088
1704#define GM_MIB_CNT_BASE 0x0100
1705#define GM_MIB_CNT_SIZE 44
1711#define GM_RXF_UC_OK \
1712 (GM_MIB_CNT_BASE + 0)
1713#define GM_RXF_BC_OK \
1714 (GM_MIB_CNT_BASE + 8)
1715#define GM_RXF_MPAUSE \
1716 (GM_MIB_CNT_BASE + 16)
1717#define GM_RXF_MC_OK \
1718 (GM_MIB_CNT_BASE + 24)
1719#define GM_RXF_FCS_ERR \
1720 (GM_MIB_CNT_BASE + 32)
1721#define GM_RXF_SPARE1 \
1722 (GM_MIB_CNT_BASE + 40)
1723#define GM_RXO_OK_LO \
1724 (GM_MIB_CNT_BASE + 48)
1725#define GM_RXO_OK_HI \
1726 (GM_MIB_CNT_BASE + 56)
1727#define GM_RXO_ERR_LO \
1728 (GM_MIB_CNT_BASE + 64)
1729#define GM_RXO_ERR_HI \
1730 (GM_MIB_CNT_BASE + 72)
1732 (GM_MIB_CNT_BASE + 80)
1733#define GM_RXE_FRAG \
1734 (GM_MIB_CNT_BASE + 88)
1736 (GM_MIB_CNT_BASE + 96)
1737#define GM_RXF_127B \
1738 (GM_MIB_CNT_BASE + 104)
1739#define GM_RXF_255B \
1740 (GM_MIB_CNT_BASE + 112)
1741#define GM_RXF_511B \
1742 (GM_MIB_CNT_BASE + 120)
1743#define GM_RXF_1023B \
1744 (GM_MIB_CNT_BASE + 128)
1745#define GM_RXF_1518B \
1746 (GM_MIB_CNT_BASE + 136)
1747#define GM_RXF_MAX_SZ \
1748 (GM_MIB_CNT_BASE + 144)
1749#define GM_RXF_LNG_ERR \
1750 (GM_MIB_CNT_BASE + 152)
1751#define GM_RXF_JAB_PKT \
1752 (GM_MIB_CNT_BASE + 160)
1753#define GM_RXF_SPARE2 \
1754 (GM_MIB_CNT_BASE + 168)
1755#define GM_RXE_FIFO_OV \
1756 (GM_MIB_CNT_BASE + 176)
1757#define GM_RXF_SPARE3 \
1758 (GM_MIB_CNT_BASE + 184)
1759#define GM_TXF_UC_OK \
1760 (GM_MIB_CNT_BASE + 192)
1761#define GM_TXF_BC_OK \
1762 (GM_MIB_CNT_BASE + 200)
1763#define GM_TXF_MPAUSE \
1764 (GM_MIB_CNT_BASE + 208)
1765#define GM_TXF_MC_OK \
1766 (GM_MIB_CNT_BASE + 216)
1767#define GM_TXO_OK_LO \
1768 (GM_MIB_CNT_BASE + 224)
1769#define GM_TXO_OK_HI \
1770 (GM_MIB_CNT_BASE + 232)
1772 (GM_MIB_CNT_BASE + 240)
1773#define GM_TXF_127B \
1774 (GM_MIB_CNT_BASE + 248)
1775#define GM_TXF_255B \
1776 (GM_MIB_CNT_BASE + 256)
1777#define GM_TXF_511B \
1778 (GM_MIB_CNT_BASE + 264)
1779#define GM_TXF_1023B \
1780 (GM_MIB_CNT_BASE + 272)
1781#define GM_TXF_1518B \
1782 (GM_MIB_CNT_BASE + 280)
1783#define GM_TXF_MAX_SZ \
1784 (GM_MIB_CNT_BASE + 288)
1785#define GM_TXF_SPARE1 \
1786 (GM_MIB_CNT_BASE + 296)
1788 (GM_MIB_CNT_BASE + 304)
1789#define GM_TXF_LAT_COL \
1790 (GM_MIB_CNT_BASE + 312)
1791#define GM_TXF_ABO_COL \
1792 (GM_MIB_CNT_BASE + 320)
1793#define GM_TXF_MUL_COL \
1794 (GM_MIB_CNT_BASE + 328)
1795#define GM_TXF_SNG_COL \
1796 (GM_MIB_CNT_BASE + 336)
1797#define GM_TXE_FIFO_UR \
1798 (GM_MIB_CNT_BASE + 344)
1812#define GM_GPSR_SPEED BIT_15
1813#define GM_GPSR_DUPLEX BIT_14
1814#define GM_GPSR_FC_TX_DIS BIT_13
1815#define GM_GPSR_LINK_UP BIT_12
1816#define GM_GPSR_PAUSE BIT_11
1817#define GM_GPSR_TX_ACTIVE BIT_10
1818#define GM_GPSR_EXC_COL BIT_9
1819#define GM_GPSR_LAT_COL BIT_8
1820#define GM_GPSR_PHY_ST_CH BIT_5
1821#define GM_GPSR_GIG_SPEED BIT_4
1822#define GM_GPSR_PART_MODE BIT_3
1823#define GM_GPSR_FC_RX_DIS BIT_2
1826#define GM_GPCR_RMII_PH_ENA BIT_15
1827#define GM_GPCR_RMII_LB_ENA BIT_14
1828#define GM_GPCR_FC_TX_DIS BIT_13
1829#define GM_GPCR_TX_ENA BIT_12
1830#define GM_GPCR_RX_ENA BIT_11
1831#define GM_GPCR_LOOP_ENA BIT_9
1832#define GM_GPCR_PART_ENA BIT_8
1833#define GM_GPCR_GIGS_ENA BIT_7
1834#define GM_GPCR_FL_PASS BIT_6
1835#define GM_GPCR_DUP_FULL BIT_5
1836#define GM_GPCR_FC_RX_DIS BIT_4
1837#define GM_GPCR_SPEED_100 BIT_3
1838#define GM_GPCR_AU_DUP_DIS BIT_2
1839#define GM_GPCR_AU_FCT_DIS BIT_1
1840#define GM_GPCR_AU_SPD_DIS BIT_0
1842#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1843#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\
1847#define GM_TXCR_FORCE_JAM BIT_15
1848#define GM_TXCR_CRC_DIS BIT_14
1849#define GM_TXCR_PAD_DIS BIT_13
1850#define GM_TXCR_COL_THR_MSK (7<<10)
1851#define GM_TXCR_PAD_PAT_MSK 0xff
1854#define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK)
1855#define TX_COL_DEF 0x04
1858#define GM_RXCR_UCF_ENA BIT_15
1859#define GM_RXCR_MCF_ENA BIT_14
1860#define GM_RXCR_CRC_DIS BIT_13
1861#define GM_RXCR_PASS_FC BIT_12
1864#define GM_TXPA_JAMLEN_MSK (3<<14)
1865#define GM_TXPA_JAMIPG_MSK (0x1f<<9)
1866#define GM_TXPA_JAMDAT_MSK (0x1f<<4)
1867#define GM_TXPA_BO_LIM_MSK 0x0f
1870#define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK)
1871#define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK)
1872#define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK)
1873#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1875#define TX_JAM_LEN_DEF 0x03
1876#define TX_JAM_IPG_DEF 0x0b
1877#define TX_IPG_JAM_DEF 0x1c
1878#define TX_BOF_LIM_DEF 0x04
1881#define GM_SMOD_DATABL_MSK (0x1f<<11)
1883#define GM_SMOD_LIMIT_4 BIT_10
1884#define GM_SMOD_VLAN_ENA BIT_9
1885#define GM_SMOD_JUMBO_ENA BIT_8
1886#define GM_SMOD_IPG_MSK 0x1f
1888#define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK)
1889#define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK)
1891#define DATA_BLIND_DEF 0x04
1892#define IPG_DATA_DEF 0x1e
1895#define GM_SMI_CT_PHY_A_MSK (0x1f<<11)
1896#define GM_SMI_CT_REG_A_MSK (0x1f<<6)
1897#define GM_SMI_CT_OP_RD BIT_5
1898#define GM_SMI_CT_RD_VAL BIT_4
1899#define GM_SMI_CT_BUSY BIT_3
1901#define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK)
1902#define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK)
1905#define GM_PAR_MIB_CLR BIT_5
1906#define GM_PAR_MIB_TST BIT_4
1909#define GMR_FS_LEN_MSK (0xffff<<16)
1910#define GMR_FS_VLAN BIT_13
1911#define GMR_FS_JABBER BIT_12
1912#define GMR_FS_UN_SIZE BIT_11
1913#define GMR_FS_MC BIT_10
1914#define GMR_FS_BC BIT_9
1915#define GMR_FS_RX_OK BIT_8
1916#define GMR_FS_GOOD_FC BIT_7
1917#define GMR_FS_BAD_FC BIT_6
1918#define GMR_FS_MII_ERR BIT_5
1919#define GMR_FS_LONG_ERR BIT_4
1920#define GMR_FS_FRAGMENT BIT_3
1921#define GMR_FS_CRC_ERR BIT_1
1922#define GMR_FS_RX_FF_OV BIT_0
1924#define GMR_FS_LEN_SHIFT 16
1926#define GMR_FS_ANY_ERR ( \
1938#define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR
1958#define RX_TRUNC_ON BIT_27
1959#define RX_TRUNC_OFF BIT_26
1960#define RX_VLAN_STRIP_ON BIT_25
1961#define RX_VLAN_STRIP_OFF BIT_24
1962#define GMF_RX_MACSEC_FLUSH_ON BIT_23
1963#define GMF_RX_MACSEC_FLUSH_OFF BIT_22
1964#define GMF_RX_OVER_ON BIT_19
1965#define GMF_RX_OVER_OFF BIT_18
1966#define GMF_ASF_RX_OVER_ON BIT_17
1967#define GMF_ASF_RX_OVER_OFF BIT_16
1968#define GMF_WP_TST_ON BIT_14
1969#define GMF_WP_TST_OFF BIT_13
1970#define GMF_WP_STEP BIT_12
1971#define GMF_RP_TST_ON BIT_10
1972#define GMF_RP_TST_OFF BIT_9
1973#define GMF_RP_STEP BIT_8
1974#define GMF_RX_F_FL_ON BIT_7
1975#define GMF_RX_F_FL_OFF BIT_6
1976#define GMF_CLI_RX_FO BIT_5
1977#define GMF_CLI_RX_FC BIT_4
1978#define GMF_OPER_ON BIT_3
1979#define GMF_OPER_OFF BIT_2
1980#define GMF_RST_CLR BIT_1
1981#define GMF_RST_SET BIT_0
1984#define TX_STFW_DIS BIT_31
1985#define TX_STFW_ENA BIT_30
1986#define TX_VLAN_TAG_ON BIT_25
1987#define TX_VLAN_TAG_OFF BIT_24
1988#define TX_JUMBO_ENA BIT_23
1989#define TX_JUMBO_DIS BIT_22
1990#define GMF_WSP_TST_ON BIT_18
1991#define GMF_WSP_TST_OFF BIT_17
1992#define GMF_WSP_STEP BIT_16
1994#define GMF_CLI_TX_FU BIT_6
1995#define GMF_CLI_TX_FC BIT_5
1996#define GMF_CLI_TX_PE BIT_4
1999#define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON)
2000#define GMF_TX_CTRL_DEF GMF_OPER_ON
2002#define RX_GMF_AF_THR_MIN 0x0c
2003#define RX_GMF_FL_THR_DEF 0x0a
2006#define GMT_ST_START BIT_2
2007#define GMT_ST_STOP BIT_1
2008#define GMT_ST_CLR_IRQ BIT_0
2011#define PC_CLR_IRQ_CHK BIT_5
2012#define PC_POLL_RQ BIT_4
2013#define PC_POLL_OP_ON BIT_3
2014#define PC_POLL_OP_OFF BIT_2
2015#define PC_POLL_RST_CLR BIT_1
2016#define PC_POLL_RST_SET BIT_0
2020#define Y2_ASF_OS_PRES BIT_4
2021#define Y2_ASF_RESET BIT_3
2022#define Y2_ASF_RUNNING BIT_2
2023#define Y2_ASF_CLR_HSTI BIT_1
2024#define Y2_ASF_IRQ BIT_0
2026#define Y2_ASF_UC_STATE (3<<2)
2027#define Y2_ASF_CLK_HALT 0
2030#define Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27
2031#define Y2_ASF_HCU_CCSR_CPU_SLEEP BIT_26
2032#define Y2_ASF_HCU_CCSR_CS_TO BIT_25
2033#define Y2_ASF_HCU_CCSR_WDOG BIT_24
2034#define Y2_ASF_HCU_CCSR_CLR_IRQ_HOST BIT_17
2035#define Y2_ASF_HCU_CCSR_SET_IRQ_HCU BIT_16
2036#define Y2_ASF_HCU_CCSR_AHB_RST BIT_9
2037#define Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8
2038#define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5
2039#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4
2040#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3
2041#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3)
2042#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3
2043#define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2
2045#define Y2_ASF_HCU_CCSR_UC_STATE_MSK 3
2046#define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0
2047#define Y2_ASF_HCU_CCSR_ASF_RESET 0
2048#define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1
2049#define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0
2053#define Y2_ASF_CLR_ASFI BIT_1
2054#define Y2_ASF_HOST_IRQ BIT_0
2057#define SC_STAT_CLR_IRQ BIT_4
2058#define SC_STAT_OP_ON BIT_3
2059#define SC_STAT_OP_OFF BIT_2
2060#define SC_STAT_RST_CLR BIT_1
2061#define SC_STAT_RST_SET BIT_0
2064#define GMC_SEC_RST BIT_15
2065#define GMC_SEC_RST_OFF BIT_14
2066#define GMC_BYP_MACSECRX_ON BIT_13
2067#define GMC_BYP_MACSECRX_OFF BIT_12
2068#define GMC_BYP_MACSECTX_ON BIT_11
2069#define GMC_BYP_MACSECTX_OFF BIT_10
2070#define GMC_BYP_RETR_ON BIT_9
2071#define GMC_BYP_RETR_OFF BIT_8
2072#define GMC_H_BURST_ON BIT_7
2073#define GMC_H_BURST_OFF BIT_6
2074#define GMC_F_LOOPB_ON BIT_5
2075#define GMC_F_LOOPB_OFF BIT_4
2076#define GMC_PAUSE_ON BIT_3
2077#define GMC_PAUSE_OFF BIT_2
2078#define GMC_RST_CLR BIT_1
2079#define GMC_RST_SET BIT_0
2082#define GPC_SEL_BDT BIT_28
2083#define GPC_INT_POL BIT_27
2084#define GPC_75_OHM BIT_26
2085#define GPC_DIS_FC BIT_25
2086#define GPC_DIS_SLEEP BIT_24
2087#define GPC_HWCFG_M_3 BIT_23
2088#define GPC_HWCFG_M_2 BIT_22
2089#define GPC_HWCFG_M_1 BIT_21
2090#define GPC_HWCFG_M_0 BIT_20
2091#define GPC_ANEG_0 BIT_19
2092#define GPC_ENA_XC BIT_18
2093#define GPC_DIS_125 BIT_17
2094#define GPC_ANEG_3 BIT_16
2095#define GPC_ANEG_2 BIT_15
2096#define GPC_ANEG_1 BIT_14
2097#define GPC_ENA_PAUSE BIT_13
2098#define GPC_PHYADDR_4 BIT_12
2099#define GPC_PHYADDR_3 BIT_11
2100#define GPC_PHYADDR_2 BIT_10
2101#define GPC_PHYADDR_1 BIT_9
2102#define GPC_PHYADDR_0 BIT_8
2103#define GPC_RST_CLR BIT_1
2104#define GPC_RST_SET BIT_0
2108#define GM_IS_RX_CO_OV BIT_5
2109#define GM_IS_TX_CO_OV BIT_4
2110#define GM_IS_TX_FF_UR BIT_3
2111#define GM_IS_TX_COMPL BIT_2
2112#define GM_IS_RX_FF_OR BIT_1
2113#define GM_IS_RX_COMPL BIT_0
2115#define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR)
2118#define GMLC_RST_CLR BIT_1
2119#define GMLC_RST_SET BIT_0
2125#define CSR_WRITE_4(sc, reg, val) \
2126 bus_write_4((sc)->msk_res[0], (reg), (val))
2127#define CSR_WRITE_2(sc, reg, val) \
2128 bus_write_2((sc)->msk_res[0], (reg), (val))
2129#define CSR_WRITE_1(sc, reg, val) \
2130 bus_write_1((sc)->msk_res[0], (reg), (val))
2132#define CSR_READ_4(sc, reg) \
2133 bus_read_4((sc)->msk_res[0], (reg))
2134#define CSR_READ_2(sc, reg) \
2135 bus_read_2((sc)->msk_res[0], (reg))
2136#define CSR_READ_1(sc, reg) \
2137 bus_read_1((sc)->msk_res[0], (reg))
2139#define CSR_PCI_WRITE_4(sc, reg, val) \
2140 bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2141#define CSR_PCI_WRITE_2(sc, reg, val) \
2142 bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2143#define CSR_PCI_WRITE_1(sc, reg, val) \
2144 bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2146#define CSR_PCI_READ_4(sc, reg) \
2147 bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2148#define CSR_PCI_READ_2(sc, reg) \
2149 bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2150#define CSR_PCI_READ_1(sc, reg) \
2151 bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2153#define MSK_IF_READ_4(sc_if, reg) \
2154 CSR_READ_4((sc_if)->msk_softc, (reg))
2155#define MSK_IF_READ_2(sc_if, reg) \
2156 CSR_READ_2((sc_if)->msk_softc, (reg))
2157#define MSK_IF_READ_1(sc_if, reg) \
2158 CSR_READ_1((sc_if)->msk_softc, (reg))
2160#define MSK_IF_WRITE_4(sc_if, reg, val) \
2161 CSR_WRITE_4((sc_if)->msk_softc, (reg), (val))
2162#define MSK_IF_WRITE_2(sc_if, reg, val) \
2163 CSR_WRITE_2((sc_if)->msk_softc, (reg), (val))
2164#define MSK_IF_WRITE_1(sc_if, reg, val) \
2165 CSR_WRITE_1((sc_if)->msk_softc, (reg), (val))
2167#define GMAC_REG(port, reg) \
2168 ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))
2169#define GMAC_WRITE_2(sc, port, reg, val) \
2170 CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val))
2171#define GMAC_READ_2(sc, port, reg) \
2172 CSR_READ_2((sc), GMAC_REG((port), (reg)))
2175#define PHY_ADDR_MARV 0
2177#define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL)
2178#define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32)
2180#define MSK_RING_ALIGN 32768
2181#define MSK_STAT_ALIGN 32768
2202#define STLE_TXA1_MSKL 0x00000fff
2203#define STLE_TXA1_SHIFTL 0
2206#define STLE_TXS1_MSKL 0x00fff000
2207#define STLE_TXS1_SHIFTL 12
2210#define STLE_TXA2_MSKL 0xff000000
2211#define STLE_TXA2_SHIFTL 24
2212#define STLE_TXA2_MSKH 0x000f
2214#define STLE_TXA2_SHIFTH 8
2217#define STLE_TXS2_MSKL 0x00000000
2218#define STLE_TXS2_SHIFTL 0
2219#define STLE_TXS2_MSKH 0xfff0
2220#define STLE_TXS2_SHIFTH 4
2223#define HW_OWNER 0x80000000
2224#define SW_OWNER 0x00000000
2226#define PU_PUTIDX_VALID 0x10000000
2229#define UDPTCP 0x00010000
2230#define CALSUM 0x00020000
2231#define WR_SUM 0x00040000
2232#define INIT_SUM 0x00080000
2233#define LOCK_SUM 0x00100000
2234#define INS_VLAN 0x00200000
2235#define FRC_STAT 0x00400000
2236#define EOP 0x00800000
2238#define TX_LOCK 0x01000000
2239#define BUF_SEND 0x02000000
2240#define PACKET_SEND 0x04000000
2242#define NO_WARNING 0x40000000
2243#define NO_UPDATE 0x80000000
2246#define OP_TCPWRITE 0x11000000
2247#define OP_TCPSTART 0x12000000
2248#define OP_TCPINIT 0x14000000
2249#define OP_TCPLCK 0x18000000
2250#define OP_TCPCHKSUM OP_TCPSTART
2251#define OP_TCPIS (OP_TCPINIT | OP_TCPSTART)
2252#define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE)
2253#define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE)
2254#define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE)
2255#define OP_ADDR64 0x21000000
2256#define OP_VLAN 0x22000000
2257#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN)
2258#define OP_LRGLEN 0x24000000
2259#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN)
2260#define OP_MSS 0x28000000
2261#define OP_MSSVLAN (OP_MSS | OP_VLAN)
2262#define OP_BUFFER 0x40000000
2263#define OP_PACKET 0x41000000
2264#define OP_LARGESEND 0x43000000
2267#define OP_RXSTAT 0x60000000
2268#define OP_RXTIMESTAMP 0x61000000
2269#define OP_RXVLAN 0x62000000
2270#define OP_RXCHKS 0x64000000
2271#define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN)
2272#define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN)
2273#define OP_RSS_HASH 0x65000000
2274#define OP_TXINDEXLE 0x68000000
2277#define OP_PUTIDX 0x70000000
2279#define STLE_OP_MASK 0xff000000
2280#define STLE_CSS_MASK 0x00ff0000
2281#define STLE_LEN_MASK 0x0000ffff
2284#define CSS_TCPUDP_CSUM_OK 0x00800000
2285#define CSS_UDP 0x00400000
2286#define CSS_TCP 0x00200000
2287#define CSS_IPFRAG 0x00100000
2288#define CSS_IPV6 0x00080000
2289#define CSS_IPV4_CSUM_OK 0x00040000
2290#define CSS_IPV4 0x00020000
2291#define CSS_PORT 0x00010000
2296#define BMU_OWN BIT_31
2297#define BMU_STF BIT_30
2298#define BMU_EOF BIT_29
2299#define BMU_IRQ_EOB BIT_28
2300#define BMU_IRQ_EOF BIT_27
2302#define BMU_STFWD BIT_26
2303#define BMU_NO_FCS BIT_25
2304#define BMU_SW BIT_24
2306#define BMU_DEV_0 BIT_26
2307#define BMU_STAT_VAL BIT_25
2308#define BMU_TIST_VAL BIT_24
2310#define BMU_CHECK (0x55<<16)
2311#define BMU_TCP_CHECK (0x56<<16)
2312#define BMU_UDP_CHECK (0x57<<16)
2313#define BMU_BBC 0xffff
2327#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
2328#define MSK_64BIT_DMA
2329#define MSK_TX_RING_CNT 384
2330#define MSK_RX_RING_CNT 512
2333#define MSK_TX_RING_CNT 256
2334#define MSK_RX_RING_CNT 256
2336#define MSK_RX_BUF_ALIGN 8
2337#define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT
2338#define MSK_MAXTXSEGS 35
2339#define MSK_TSO_MAXSGSIZE 4096
2340#define MSK_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
2352#define MSK_RESERVED_TX_DESC_CNT (MSK_MAXTXSEGS + 3)
2354#define MSK_RESERVED_TX_DESC_CNT 3
2357#define MSK_JUMBO_FRAMELEN 9022
2358#define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2359#define MSK_MAX_FRAMELEN \
2360 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)
2361#define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
2412#define MSK_TX_RING_ADDR(sc, i) \
2413 ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i))
2414#define MSK_RX_RING_ADDR(sc, i) \
2415 ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i))
2416#define MSK_JUMBO_RX_RING_ADDR(sc, i) \
2417 ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i))
2419#define MSK_TX_RING_SZ \
2420 (sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT)
2421#define MSK_RX_RING_SZ \
2422 (sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT)
2423#define MSK_JUMBO_RX_RING_SZ \
2424 (sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT)
2426#define MSK_INC(x, y) (x) = (x + 1) % y
2428#define MSK_RX_INC(x, y) (x) = (x + 2) % y
2429#define MSK_RX_BUF_CNT (MSK_RX_RING_CNT / 2)
2430#define MSK_JUMBO_RX_BUF_CNT (MSK_JUMBO_RX_RING_CNT / 2)
2432#define MSK_RX_INC(x, y) (x) = (x + 1) % y
2433#define MSK_RX_BUF_CNT MSK_RX_RING_CNT
2434#define MSK_JUMBO_RX_BUF_CNT MSK_JUMBO_RX_RING_CNT
2437#define MSK_PCI_BUS 0
2438#define MSK_PCIX_BUS 1
2439#define MSK_PEX_BUS 2
2441#define MSK_PROC_DEFAULT (MSK_RX_RING_CNT / 2)
2442#define MSK_PROC_MIN 30
2443#define MSK_PROC_MAX (MSK_RX_RING_CNT - 1)
2445#define MSK_INT_HOLDOFF_DEFAULT 100
2447#define MSK_TX_TIMEOUT 5
2448#define MSK_PUT_WM 10
2544#define MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx)
2545#define MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx)
2546#define MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED)
2547#define MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc)
2548#define MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc)
2549#define MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc)
2551#define MSK_USECS(sc, us) ((sc)->msk_clock * (us))
2563#define MSK_FLAG_MSI 0x0001
2564#define MSK_FLAG_FASTETHER 0x0004
2565#define MSK_FLAG_JUMBO 0x0008
2566#define MSK_FLAG_JUMBO_NOCSUM 0x0010
2567#define MSK_FLAG_RAMBUF 0x0020
2568#define MSK_FLAG_DESCV2 0x0040
2569#define MSK_FLAG_AUTOTX_CSUM 0x0080
2570#define MSK_FLAG_NOHWVLAN 0x0100
2571#define MSK_FLAG_NORXCHK 0x0200
2572#define MSK_FLAG_NORX_CSUM 0x0400
2573#define MSK_FLAG_SUSPEND 0x2000
2574#define MSK_FLAG_DETACH 0x4000
2575#define MSK_FLAG_LINK 0x8000
2590#define MSK_TIMEOUT 1000
2591#define MSK_PHY_POWERUP 1
2592#define MSK_PHY_POWERDOWN 0
#define MSK_JUMBO_RX_RING_CNT
bus_dma_tag_t msk_jumbo_rx_tag
struct msk_rxdesc msk_jumbo_rxdesc[MSK_JUMBO_RX_RING_CNT]
bus_dmamap_t msk_tx_ring_map
bus_dmamap_t msk_jumbo_rx_sparemap
bus_dma_tag_t msk_parent_tag
bus_dma_tag_t msk_jumbo_rx_ring_tag
bus_dmamap_t msk_rx_sparemap
bus_dma_tag_t msk_rx_ring_tag
uint32_t msk_tx_high_addr
bus_dma_tag_t msk_tx_ring_tag
bus_dmamap_t msk_rx_ring_map
bus_dmamap_t msk_jumbo_rx_ring_map
uint32_t rx_pkts_1024_1518
uint32_t tx_pkts_512_1023
uint32_t tx_pkts_1024_1518
uint32_t tx_pkts_1519_max
uint32_t rx_pkts_too_long
uint32_t rx_pkts_512_1023
uint32_t rx_pkts_1519_max
struct msk_ring_data msk_rdata
struct msk_hw_stats msk_stats
struct callout msk_tick_ch
struct msk_chain_data msk_cdata
struct msk_softc * msk_softc
bus_addr_t msk_jumbo_rx_ring_paddr
bus_addr_t msk_tx_ring_paddr
bus_addr_t msk_rx_ring_paddr
struct msk_rx_desc * msk_jumbo_rx_ring
struct msk_tx_desc * msk_tx_ring
struct msk_rx_desc * msk_rx_ring
struct msk_rx_desc * rx_le
struct resource_spec * msk_res_spec
struct msk_if_softc * msk_if[2]
struct resource * msk_res[1]
struct resource * msk_irq[1]
bus_addr_t msk_stat_ring_paddr
bus_dmamap_t msk_stat_map
bus_dma_tag_t msk_stat_tag
struct msk_stat_desc * msk_stat_ring
struct resource_spec * msk_irq_spec
struct msk_tx_desc * tx_le