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Data Structures | |
| struct | msk_rx_desc |
| struct | msk_tx_desc |
| struct | msk_stat_desc |
| struct | msk_txdesc |
| struct | msk_rxdesc |
| struct | msk_chain_data |
| struct | msk_ring_data |
| struct | msk_mii_data |
| struct | msk_hw_stats |
| struct | msk_softc |
| struct | msk_if_softc |
Macros | |
| #define | VENDORID_SK 0x1148 |
| #define | VENDORID_MARVELL 0x11AB |
| #define | VENDORID_DLINK 0x1186 |
| #define | DEVICEID_SK_YUKON2 0x9000 |
| #define | DEVICEID_SK_YUKON2_EXPR 0x9e00 |
| #define | DEVICEID_MRVL_8021CU 0x4340 |
| #define | DEVICEID_MRVL_8022CU 0x4341 |
| #define | DEVICEID_MRVL_8061CU 0x4342 |
| #define | DEVICEID_MRVL_8062CU 0x4343 |
| #define | DEVICEID_MRVL_8021X 0x4344 |
| #define | DEVICEID_MRVL_8022X 0x4345 |
| #define | DEVICEID_MRVL_8061X 0x4346 |
| #define | DEVICEID_MRVL_8062X 0x4347 |
| #define | DEVICEID_MRVL_8035 0x4350 |
| #define | DEVICEID_MRVL_8036 0x4351 |
| #define | DEVICEID_MRVL_8038 0x4352 |
| #define | DEVICEID_MRVL_8039 0x4353 |
| #define | DEVICEID_MRVL_8040 0x4354 |
| #define | DEVICEID_MRVL_8040T 0x4355 |
| #define | DEVICEID_MRVL_8042 0x4357 |
| #define | DEVICEID_MRVL_8048 0x435A |
| #define | DEVICEID_MRVL_4360 0x4360 |
| #define | DEVICEID_MRVL_4361 0x4361 |
| #define | DEVICEID_MRVL_4362 0x4362 |
| #define | DEVICEID_MRVL_4363 0x4363 |
| #define | DEVICEID_MRVL_4364 0x4364 |
| #define | DEVICEID_MRVL_4365 0x4365 |
| #define | DEVICEID_MRVL_436A 0x436A |
| #define | DEVICEID_MRVL_436B 0x436B |
| #define | DEVICEID_MRVL_436C 0x436C |
| #define | DEVICEID_MRVL_436D 0x436D |
| #define | DEVICEID_MRVL_4370 0x4370 |
| #define | DEVICEID_MRVL_4380 0x4380 |
| #define | DEVICEID_MRVL_4381 0x4381 |
| #define | DEVICEID_DLINK_DGE550SX 0x4001 |
| #define | DEVICEID_DLINK_DGE560SX 0x4002 |
| #define | DEVICEID_DLINK_DGE560T 0x4b00 |
| #define | BIT_31 (1U << 31) |
| #define | BIT_30 (1 << 30) |
| #define | BIT_29 (1 << 29) |
| #define | BIT_28 (1 << 28) |
| #define | BIT_27 (1 << 27) |
| #define | BIT_26 (1 << 26) |
| #define | BIT_25 (1 << 25) |
| #define | BIT_24 (1 << 24) |
| #define | BIT_23 (1 << 23) |
| #define | BIT_22 (1 << 22) |
| #define | BIT_21 (1 << 21) |
| #define | BIT_20 (1 << 20) |
| #define | BIT_19 (1 << 19) |
| #define | BIT_18 (1 << 18) |
| #define | BIT_17 (1 << 17) |
| #define | BIT_16 (1 << 16) |
| #define | BIT_15 (1 << 15) |
| #define | BIT_14 (1 << 14) |
| #define | BIT_13 (1 << 13) |
| #define | BIT_12 (1 << 12) |
| #define | BIT_11 (1 << 11) |
| #define | BIT_10 (1 << 10) |
| #define | BIT_9 (1 << 9) |
| #define | BIT_8 (1 << 8) |
| #define | BIT_7 (1 << 7) |
| #define | BIT_6 (1 << 6) |
| #define | BIT_5 (1 << 5) |
| #define | BIT_4 (1 << 4) |
| #define | BIT_3 (1 << 3) |
| #define | BIT_2 (1 << 2) |
| #define | BIT_1 (1 << 1) |
| #define | BIT_0 (1 << 0) |
| #define | SHIFT31(x) ((x) << 31) |
| #define | SHIFT30(x) ((x) << 30) |
| #define | SHIFT29(x) ((x) << 29) |
| #define | SHIFT28(x) ((x) << 28) |
| #define | SHIFT27(x) ((x) << 27) |
| #define | SHIFT26(x) ((x) << 26) |
| #define | SHIFT25(x) ((x) << 25) |
| #define | SHIFT24(x) ((x) << 24) |
| #define | SHIFT23(x) ((x) << 23) |
| #define | SHIFT22(x) ((x) << 22) |
| #define | SHIFT21(x) ((x) << 21) |
| #define | SHIFT20(x) ((x) << 20) |
| #define | SHIFT19(x) ((x) << 19) |
| #define | SHIFT18(x) ((x) << 18) |
| #define | SHIFT17(x) ((x) << 17) |
| #define | SHIFT16(x) ((x) << 16) |
| #define | SHIFT15(x) ((x) << 15) |
| #define | SHIFT14(x) ((x) << 14) |
| #define | SHIFT13(x) ((x) << 13) |
| #define | SHIFT12(x) ((x) << 12) |
| #define | SHIFT11(x) ((x) << 11) |
| #define | SHIFT10(x) ((x) << 10) |
| #define | SHIFT9(x) ((x) << 9) |
| #define | SHIFT8(x) ((x) << 8) |
| #define | SHIFT7(x) ((x) << 7) |
| #define | SHIFT6(x) ((x) << 6) |
| #define | SHIFT5(x) ((x) << 5) |
| #define | SHIFT4(x) ((x) << 4) |
| #define | SHIFT3(x) ((x) << 3) |
| #define | SHIFT2(x) ((x) << 2) |
| #define | SHIFT1(x) ((x) << 1) |
| #define | SHIFT0(x) ((x) << 0) |
| #define | PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ |
| #define | PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ |
| #define | PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ |
| #define | PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ |
| #define | PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */ |
| #define | PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */ |
| #define | PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */ |
| #define | PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */ |
| #define | PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */ |
| #define | PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */ |
| #define | PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */ |
| #define | PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */ |
| #define | PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */ |
| #define | PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */ |
| #define | PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */ |
| #define | PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */ |
| #define | PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */ |
| #define | PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */ |
| #define | PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */ |
| #define | PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */ |
| #define | PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */ |
| #define | PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */ |
| #define | PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */ |
| #define | PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */ |
| #define | PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */ |
| #define | PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */ |
| #define | PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */ |
| #define | PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */ |
| #define | PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */ |
| #define | PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */ |
| #define | PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */ |
| #define | PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */ |
| #define | PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */ |
| #define | PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ |
| #define | PCI_EN_IO BIT_23 /* Mapping to I/O space */ |
| #define | PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ |
| #define | PCI_PAGESIZE (3L<<20)/* Bit 21..20: FLASH Page Size */ |
| #define | PCI_PAGE_16 (0L<<20)/* 16 k pages */ |
| #define | PCI_PAGE_32K (1L<<20)/* 32 k pages */ |
| #define | PCI_PAGE_64K (2L<<20)/* 64 k pages */ |
| #define | PCI_PAGE_128K (3L<<20)/* 128 k pages */ |
| #define | PCI_PAGEREG (7L<<16)/* Bit 18..16: Page Register */ |
| #define | PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */ |
| #define | PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ |
| #define | PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ |
| #define | PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ |
| #define | PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */ |
| #define | PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */ |
| #define | PCI_BURST_DIS BIT_9 /* Burst Disable */ |
| #define | PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */ |
| #define | PCI_SKEW_DAS (0xfL<<4)/* Bit 7.. 4: Skew Ctrl, DAS Ext */ |
| #define | PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ |
| #define | PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */ |
| #define | PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */ |
| #define | PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */ |
| #define | PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */ |
| #define | PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ |
| #define | PCI_PATCH_DIR_3 BIT_11 |
| #define | PCI_PATCH_DIR_2 BIT_10 |
| #define | PCI_PATCH_DIR_1 BIT_9 |
| #define | PCI_PATCH_DIR_0 BIT_8 |
| #define | PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */ |
| #define | PCI_EXT_PATCH_3 BIT_7 |
| #define | PCI_EXT_PATCH_2 BIT_6 |
| #define | PCI_EXT_PATCH_1 BIT_5 |
| #define | PCI_EXT_PATCH_0 BIT_4 |
| #define | PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ |
| #define | PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ |
| #define | PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ |
| #define | PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */ |
| #define | PCI_OS_PCIX BIT_30 /* PCI-X Bus */ |
| #define | PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */ |
| #define | PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */ |
| #define | PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */ |
| #define | PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */ |
| #define | PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Counters Values */ |
| #define | PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Counters Values */ |
| #define | PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */ |
| #define | PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */ |
| #define | PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */ |
| #define | PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */ |
| #define | PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */ |
| #define | PCI_CLK_MACSEC_DIS BIT_17 /* Disable Clock MACSec. */ |
| #define | PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */ |
| #define | PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */ |
| #define | PCI_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */ |
| #define | PCI_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */ |
| #define | PCI_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */ |
| #define | PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */ |
| #define | PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */ |
| #define | PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */ |
| #define | PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */ |
| #define | PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */ |
| #define | PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */ |
| #define | PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */ |
| #define | PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */ |
| #define | PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */ |
| #define | PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */ |
| #define | PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27) |
| #define | PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */ |
| #define | PCI_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */ |
| #define | PCI_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */ |
| #define | PCI_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */ |
| #define | PCI_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */ |
| #define | PCI_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */ |
| #define | PCI_REL_PME_ASSERTED BIT_20 /* PME Asserted */ |
| #define | PCI_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */ |
| #define | PCI_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */ |
| #define | PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */ |
| #define | PCI_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */ |
| #define | PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */ |
| #define | PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */ |
| #define | PCI_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */ |
| #define | PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */ |
| #define | PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */ |
| #define | PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */ |
| #define | PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */ |
| #define | PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */ |
| #define | PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */ |
| #define | PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */ |
| #define | PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */ |
| #define | PCI_CF1_DIS_REL_EVT_RST BIT_24 /* Dis. Rel. Event during PCIE reset */ |
| #define | PCI_CF1_REL_LDR_NOT_FIN BIT_23 /* EEPROM Loader Not Finished */ |
| #define | PCI_CF1_REL_VMAIN_AVLBL BIT_22 /* Vmain available */ |
| #define | PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */ |
| #define | PCI_CF1_GAT_LDR_NOT_FIN BIT_20 /* EEPROM Loader Finished */ |
| #define | PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */ |
| #define | PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */ |
| #define | PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */ |
| #define | PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */ |
| #define | PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */ |
| #define | PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */ |
| #define | PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */ |
| #define | PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */ |
| #define | PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */ |
| #define | PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */ |
| #define | PEX_DC_EN_PHANTOM BIT_9 /* Enable Phantom Functions */ |
| #define | PEX_DC_EN_EXT_TAG BIT_8 /* Enable Extended Tag Field */ |
| #define | PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */ |
| #define | PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */ |
| #define | PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */ |
| #define | PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */ |
| #define | PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */ |
| #define | PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */ |
| #define | PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK) |
| #define | PEX_LS_SLOT_CLK_CFG BIT_12 /* Slot Clock Config */ |
| #define | PEX_LS_LINK_TRAIN BIT_11 /* Link Training */ |
| #define | PEX_LS_TRAIN_ERROR BIT_10 /* Training Error */ |
| #define | PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */ |
| #define | PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */ |
| #define | PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */ |
| #define | PEX_MALFOR_TLP BIT_18 /* Malformed TLP */ |
| #define | PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */ |
| #define | PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */ |
| #define | PEX_COMP_TO BIT_14 /* Completion Timeout */ |
| #define | PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */ |
| #define | PEX_POIS_TLP BIT_12 /* Poisoned TLP */ |
| #define | PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */ |
| #define | PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P) |
| #define | B0_RAP 0x0000 /* 8 bit Register Address Port */ |
| #define | B0_CTST 0x0004 /* 16 bit Control/Status register */ |
| #define | B0_LED 0x0006 /* 8 Bit LED register */ |
| #define | B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */ |
| #define | B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */ |
| #define | B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ |
| #define | B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ |
| #define | B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ |
| #define | B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */ |
| #define | B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */ |
| #define | B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */ |
| #define | B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */ |
| #define | B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */ |
| #define | B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */ |
| #define | B2_MAC_1 0x0100 /* NA reg MAC Address 1 */ |
| #define | B2_MAC_2 0x0108 /* NA reg MAC Address 2 */ |
| #define | B2_MAC_3 0x0110 /* NA reg MAC Address 3 */ |
| #define | B2_CONN_TYP 0x0118 /* 8 bit Connector type */ |
| #define | B2_PMD_TYP 0x0119 /* 8 bit PMD type */ |
| #define | B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ |
| #define | B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ |
| #define | B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ |
| #define | B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ |
| #define | B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */ |
| #define | B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ |
| #define | B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */ |
| #define | B2_TI_INI 0x0130 /* 32 bit Timer Init Value */ |
| #define | B2_TI_VAL 0x0134 /* 32 bit Timer Value */ |
| #define | B2_TI_CTRL 0x0138 /* 8 bit Timer Control */ |
| #define | B2_TI_TEST 0x0139 /* 8 Bit Timer Test */ |
| #define | B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/ |
| #define | B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */ |
| #define | B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */ |
| #define | B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */ |
| #define | B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ |
| #define | B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */ |
| #define | B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */ |
| #define | B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */ |
| #define | B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */ |
| #define | B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */ |
| #define | B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */ |
| #define | B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */ |
| #define | B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */ |
| #define | Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */ |
| #define | Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */ |
| #define | B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ |
| #define | B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ |
| #define | B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ |
| #define | SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */ |
| #define | B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */ |
| #define | B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */ |
| #define | B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */ |
| #define | B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */ |
| #define | B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */ |
| #define | B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */ |
| #define | B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */ |
| #define | B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */ |
| #define | B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */ |
| #define | B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */ |
| #define | B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/ |
| #define | B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/ |
| #define | B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */ |
| #define | B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */ |
| #define | B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */ |
| #define | TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/ |
| #define | TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */ |
| #define | TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */ |
| #define | TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */ |
| #define | TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ |
| #define | TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ |
| #define | TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ |
| #define | MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs)) |
| #define | B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */ |
| #define | KEY_IDX_0 0 /* offset for location of KEY 0 */ |
| #define | KEY_IDX_1 4 /* offset for location of KEY 1 */ |
| #define | KEY_IDX_2 8 /* offset for location of KEY 2 */ |
| #define | KEY_IDX_3 12 /* offset for location of KEY 3 */ |
| #define | RSS_KEY_ADDR(Port, KeyIndex) ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex)) |
| #define | B8_Q_REGS 0x0400 |
| #define | Q_D 0x00 /* 8*32 bit Current Descriptor */ |
| #define | Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */ |
| #define | Q_DONE 0x24 /* 16 bit Done Index */ |
| #define | Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */ |
| #define | Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */ |
| #define | Q_BC 0x30 /* 32 bit Current Byte Counter */ |
| #define | Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ |
| #define | Q_F 0x38 /* 32 bit Flag Register */ |
| #define | Q_T1 0x3c /* 32 bit Test Register 1 */ |
| #define | Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */ |
| #define | Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */ |
| #define | Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */ |
| #define | Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ |
| #define | Q_WM 0x40 /* 16 bit FIFO Watermark */ |
| #define | Q_AL 0x42 /* 8 bit FIFO Alignment */ |
| #define | Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */ |
| #define | Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */ |
| #define | Q_RP 0x48 /* 8 bit FIFO Read Pointer */ |
| #define | Q_RL 0x4a /* 8 bit FIFO Read Level */ |
| #define | Q_WP 0x4c /* 8 bit FIFO Write Pointer */ |
| #define | Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */ |
| #define | Q_WL 0x4e /* 8 bit FIFO Write Level */ |
| #define | Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */ |
| #define | Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs)) |
| #define | Y2_B8_PREF_REGS 0x0450 |
| #define | PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */ |
| #define | PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */ |
| #define | PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */ |
| #define | PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/ |
| #define | PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */ |
| #define | PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */ |
| #define | PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */ |
| #define | PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */ |
| #define | PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */ |
| #define | PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */ |
| #define | PREF_UNIT_MASK_IDX 0x0fff |
| #define | Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs)) |
| #define | B16_RAM_REGS 0x0800 |
| #define | RB_START 0x00 /* 32 bit RAM Buffer Start Address */ |
| #define | RB_END 0x04 /* 32 bit RAM Buffer End Address */ |
| #define | RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ |
| #define | RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ |
| #define | RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */ |
| #define | RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */ |
| #define | RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ |
| #define | RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ |
| #define | RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ |
| #define | RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ |
| #define | RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ |
| #define | RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ |
| #define | RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */ |
| #define | RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ |
| #define | RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ |
| #define | RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ |
| #define | RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ |
| #define | RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ |
| #define | RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ |
| #define | RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ |
| #define | RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ |
| #define | RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ |
| #define | RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ |
| #define | RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ |
| #define | RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ |
| #define | RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ |
| #define | TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ |
| #define | TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ |
| #define | TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ |
| #define | TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */ |
| #define | TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ |
| #define | TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */ |
| #define | TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ |
| #define | TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ |
| #define | TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ |
| #define | TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ |
| #define | B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */ |
| #define | B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */ |
| #define | B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */ |
| #define | B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */ |
| #define | GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */ |
| #define | GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ |
| #define | GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ |
| #define | POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */ |
| #define | POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */ |
| #define | POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */ |
| #define | POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */ |
| #define | B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */ |
| #define | B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */ |
| #define | B28_Y2_CPU_WDOG 0x0e48 /* 32 bit Watchdog Register */ |
| #define | B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */ |
| #define | B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */ |
| #define | B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */ |
| #define | B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */ |
| #define | B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */ |
| #define | B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */ |
| #define | B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */ |
| #define | B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */ |
| #define | STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */ |
| #define | STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */ |
| #define | STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */ |
| #define | STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */ |
| #define | STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */ |
| #define | STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */ |
| #define | STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */ |
| #define | STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */ |
| #define | STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */ |
| #define | STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */ |
| #define | STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */ |
| #define | STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */ |
| #define | STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */ |
| #define | STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */ |
| #define | STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */ |
| #define | STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */ |
| #define | STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */ |
| #define | STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */ |
| #define | STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */ |
| #define | STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */ |
| #define | STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */ |
| #define | STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */ |
| #define | STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */ |
| #define | STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */ |
| #define | STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */ |
| #define | STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */ |
| #define | STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */ |
| #define | STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */ |
| #define | STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */ |
| #define | ST_LAST_IDX_MASK 0x007f /* Last Index Mask */ |
| #define | ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */ |
| #define | ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */ |
| #define | ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */ |
| #define | GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */ |
| #define | GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */ |
| #define | GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */ |
| #define | GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */ |
| #define | GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */ |
| #define | WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */ |
| #define | WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */ |
| #define | WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */ |
| #define | WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ |
| #define | WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ |
| #define | WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ |
| #define | WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */ |
| #define | WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */ |
| #define | WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */ |
| #define | WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */ |
| #define | WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */ |
| #define | WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */ |
| #define | WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */ |
| #define | WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ |
| #define | WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */ |
| #define | Y2_CFG_SPC 0x1c00 |
| #define | BASE_GMAC_1 0x2800 /* GMAC 1 registers */ |
| #define | BASE_GMAC_2 0x3800 /* GMAC 2 registers */ |
| #define | Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */ |
| #define | Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */ |
| #define | Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */ |
| #define | Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */ |
| #define | Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */ |
| #define | Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */ |
| #define | Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */ |
| #define | Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */ |
| #define | Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */ |
| #define | Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */ |
| #define | CS_ST_SW_IRQ BIT_7 /* Set IRQ SW Request */ |
| #define | CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */ |
| #define | CS_STOP_DONE BIT_5 /* Stop Master is finished */ |
| #define | CS_STOP_MAST BIT_4 /* Command Bit to stop the master */ |
| #define | CS_MRST_CLR BIT_3 /* Clear Master Reset */ |
| #define | CS_MRST_SET BIT_2 /* Set Master Reset */ |
| #define | CS_RST_CLR BIT_1 /* Clear Software Reset */ |
| #define | CS_RST_SET BIT_0 /* Set Software Reset */ |
| #define | LED_STAT_ON BIT_1 /* Status LED On */ |
| #define | LED_STAT_OFF BIT_0 /* Status LED Off */ |
| #define | PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ |
| #define | PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ |
| #define | PC_VCC_ENA BIT_5 /* Switch VCC Enable */ |
| #define | PC_VCC_DIS BIT_4 /* Switch VCC Disable */ |
| #define | PC_VAUX_ON BIT_3 /* Switch VAUX On */ |
| #define | PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ |
| #define | PC_VCC_ON BIT_1 /* Switch VCC On */ |
| #define | PC_VCC_OFF BIT_0 /* Switch VCC Off */ |
| #define | Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8)) |
| #define | Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */ |
| #define | Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */ |
| #define | Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */ |
| #define | Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */ |
| #define | Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */ |
| #define | Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */ |
| #define | Y2_IS_TIMINT BIT_24 /* IRQ from Timer */ |
| #define | Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */ |
| #define | Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */ |
| #define | Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */ |
| #define | Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */ |
| #define | Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */ |
| #define | Y2_IS_PSM_ACK BIT_7 /* PSM Ack (Yukon Optima) */ |
| #define | Y2_IS_PTP_TIST BIT_6 /* PTP TIme Stamp (Yukon Optima) */ |
| #define | Y2_IS_PHY_QLNK BIT_5 /* PHY Quick Link (Yukon Optima) */ |
| #define | Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */ |
| #define | Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */ |
| #define | Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */ |
| #define | Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */ |
| #define | Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */ |
| #define | Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */ |
| #define | Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */ |
| #define | Y2_IS_ALL_MSK 0xef001f1f /* All Interrupt bits */ |
| #define | Y2_IS_PORT_A (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1) |
| #define | Y2_IS_PORT_B (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2) |
| #define | Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */ |
| #define | Y2_IS_SENSOR BIT_28 /* Sensor interrupt */ |
| #define | Y2_IS_MST_ERR BIT_27 /* Master error interrupt */ |
| #define | Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */ |
| #define | Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */ |
| #define | Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */ |
| #define | Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */ |
| #define | Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */ |
| #define | Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */ |
| #define | Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */ |
| #define | Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */ |
| #define | Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */ |
| #define | Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */ |
| #define | Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */ |
| #define | Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */ |
| #define | Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */ |
| #define | Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */ |
| #define | Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */ |
| #define | Y2_HWE_L1_MASK |
| #define | Y2_HWE_L2_MASK |
| #define | Y2_HWE_ALL_MSK |
| #define | CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */ |
| #define | CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */ |
| #define | CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */ |
| #define | CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ |
| #define | CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ |
| #define | CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */ |
| #define | CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */ |
| #define | CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */ |
| #define | CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */ |
| #define | CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */ |
| #define | CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ |
| #define | CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ |
| #define | CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */ |
| #define | CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */ |
| #define | CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */ |
| #define | CHIP_ID_YUKON_UNKNOWN 0xbb |
| #define | CHIP_ID_YUKON_OPT 0xbc /* Chip ID for YUKON-2 Optima */ |
| #define | CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ |
| #define | CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ |
| #define | CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */ |
| #define | CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */ |
| #define | CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */ |
| #define | CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */ |
| #define | CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */ |
| #define | CHIP_REV_YU_EC_U_A0 1 |
| #define | CHIP_REV_YU_EC_U_A1 2 |
| #define | CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */ |
| #define | CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */ |
| #define | CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */ |
| #define | CHIP_REV_YU_SU_A0 0 /* Chip Rev. for Yukon-2 SUPR A0 */ |
| #define | CHIP_REV_YU_SU_B0 1 /* Chip Rev. for Yukon-2 SUPR B0 */ |
| #define | CHIP_REV_YU_SU_B1 3 /* Chip Rev. for Yukon-2 SUPR B1 */ |
| #define | Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */ |
| #define | Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */ |
| #define | Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */ |
| #define | Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */ |
| #define | Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */ |
| #define | Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */ |
| #define | Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */ |
| #define | Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */ |
| #define | CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */ |
| #define | CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */ |
| #define | CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */ |
| #define | CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) |
| #define | CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) |
| #define | B2_E3_RES_MASK 0x0f |
| #define | Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */ |
| #define | Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK) |
| #define | Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */ |
| #define | Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */ |
| #define | Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK) |
| #define | Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK) |
| #define | Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */ |
| #define | Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */ |
| #define | TIM_START BIT_2 /* Start Timer */ |
| #define | TIM_STOP BIT_1 /* Stop Timer */ |
| #define | TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */ |
| #define | TIM_T_ON BIT_2 /* Test mode on */ |
| #define | TIM_T_OFF BIT_1 /* Test mode off */ |
| #define | TIM_T_STEP BIT_0 /* Test step */ |
| #define | DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */ |
| #define | DPT_START BIT_1 /* Start Descriptor Poll Timer */ |
| #define | DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */ |
| #define | TST_FRC_DPERR_MR BIT_7 /* force DATAPERR on MST RD */ |
| #define | TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */ |
| #define | TST_FRC_DPERR_TR BIT_5 /* force DATAPERR on TRG RD */ |
| #define | TST_FRC_DPERR_TW BIT_4 /* force DATAPERR on TRG WR */ |
| #define | TST_FRC_APERR_M BIT_3 /* force ADDRPERR on MST */ |
| #define | TST_FRC_APERR_T BIT_2 /* force ADDRPERR on TRG */ |
| #define | TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */ |
| #define | TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */ |
| #define | GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */ |
| #define | GLB_GPIO_CLK_DBG_MSK 0x3c000000 /* Clock Debug */ |
| #define | GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */ |
| #define | GLB_GPIO_LED_PAD_SPEED_UP BIT_14 /* LED PAD Speed Up */ |
| #define | GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */ |
| #define | GLB_GPIO_TEST_SEL_MSK 0x00001800 /* Testmode Select */ |
| #define | GLB_GPIO_TEST_SEL_BASE BIT_11 |
| #define | GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */ |
| #define | GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */ |
| #define | I2C_FLAG BIT_31 /* Start read/write if WR */ |
| #define | I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */ |
| #define | I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */ |
| #define | I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ |
| #define | I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */ |
| #define | I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */ |
| #define | I2C_05K_DEV (1<<1) /* 1: 512 Bytes */ |
| #define | I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */ |
| #define | I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */ |
| #define | I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */ |
| #define | I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */ |
| #define | I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */ |
| #define | I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */ |
| #define | I2C_STOP BIT_0 /* Interrupt I2C transfer */ |
| #define | I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ |
| #define | I2C_DATA_DIR BIT_2 /* direction of I2C_DATA */ |
| #define | I2C_DATA BIT_1 /* I2C Data Port */ |
| #define | I2C_CLK BIT_0 /* I2C Clock Port */ |
| #define | I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */ |
| #define | BSC_START BIT_1 /* Start Blink Source Counter */ |
| #define | BSC_STOP BIT_0 /* Stop Blink Source Counter */ |
| #define | BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */ |
| #define | BSC_T_ON BIT_2 /* Test mode on */ |
| #define | BSC_T_OFF BIT_1 /* Test mode off */ |
| #define | BSC_T_STEP BIT_0 /* Test step */ |
| #define | PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */ |
| #define | PEX_DB_ACCESS BIT_30 /* Access to debug register */ |
| #define | RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */ |
| #define | RI_CLR_RD_PERR BIT_9 /* Clear IRQ RAM Read Parity Err */ |
| #define | RI_CLR_WR_PERR BIT_8 /* Clear IRQ RAM Write Parity Err */ |
| #define | RI_RST_CLR BIT_1 /* Clear RAM Interface Reset */ |
| #define | RI_RST_SET BIT_0 /* Set RAM Interface Reset */ |
| #define | MSK_RI_TO_53 36 /* RAM interface timeout */ |
| #define | TXA_MAX_VAL 0x00ffffff/* Bit 23.. 0: Max TXA Timer/Cnt Val */ |
| #define | TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */ |
| #define | TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */ |
| #define | TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */ |
| #define | TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */ |
| #define | TXA_START_RC BIT_3 /* Start sync Rate Control */ |
| #define | TXA_STOP_RC BIT_2 /* Stop sync Rate Control */ |
| #define | TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */ |
| #define | TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */ |
| #define | TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */ |
| #define | TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */ |
| #define | TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */ |
| #define | TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */ |
| #define | TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */ |
| #define | TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */ |
| #define | TXA_PRIO_XS BIT_0 /* sync queue has prio to send */ |
| #define | BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ |
| #define | BMU_IDLE BIT_31 /* BMU Idle State */ |
| #define | BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */ |
| #define | BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */ |
| #define | BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */ |
| #define | BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */ |
| #define | BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */ |
| #define | BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */ |
| #define | BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */ |
| #define | BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */ |
| #define | BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */ |
| #define | BMU_STOP BIT_9 /* Stop Rx/Tx Queue */ |
| #define | BMU_START BIT_8 /* Start Rx/Tx Queue */ |
| #define | BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */ |
| #define | BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */ |
| #define | BMU_FIFO_ENA BIT_5 /* Enable FIFO */ |
| #define | BMU_FIFO_RST BIT_4 /* Reset FIFO */ |
| #define | BMU_OP_ON BIT_3 /* BMU Operational On */ |
| #define | BMU_OP_OFF BIT_2 /* BMU Operational Off */ |
| #define | BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */ |
| #define | BMU_RST_SET BIT_0 /* Set BMU Reset */ |
| #define | BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR) |
| #define | BMU_OPER_INIT |
| #define | BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */ |
| #define | BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */ |
| #define | BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */ |
| #define | F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/ |
| #define | F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/ |
| #define | F_ALM_FULL BIT_28 /* Rx FIFO: almost full */ |
| #define | F_EMPTY BIT_27 /* Tx FIFO: empty flag */ |
| #define | F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */ |
| #define | F_WM_REACHED BIT_25 /* Watermark reached */ |
| #define | F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */ |
| #define | F_FIFO_LEVEL (0x1f<<16) |
| #define | F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */ |
| #define | PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */ |
| #define | PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */ |
| #define | PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */ |
| #define | PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */ |
| #define | RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ |
| #define | RB_PC_DEC BIT_3 /* Packet Counter Decrement */ |
| #define | RB_PC_T_ON BIT_2 /* Packet Counter Test On */ |
| #define | RB_PC_T_OFF BIT_1 /* Packet Counter Test Off */ |
| #define | RB_PC_INC BIT_0 /* Packet Counter Increment */ |
| #define | RB_WP_T_ON BIT_6 /* Write Pointer Test On */ |
| #define | RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */ |
| #define | RB_WP_INC BIT_4 /* Write Pointer Increment */ |
| #define | RB_RP_T_ON BIT_2 /* Read Pointer Test On */ |
| #define | RB_RP_T_OFF BIT_1 /* Read Pointer Test Off */ |
| #define | RB_RP_INC BIT_0 /* Read Pointer Increment */ |
| #define | RB_ENA_STFWD BIT_5 /* Enable Store & Forward */ |
| #define | RB_DIS_STFWD BIT_4 /* Disable Store & Forward */ |
| #define | RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */ |
| #define | RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */ |
| #define | RB_RST_CLR BIT_1 /* Clear RAM Buf STM Reset */ |
| #define | RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */ |
| #define | MSK_RB_ULPP (8 * 1024) /* Upper Level in kB/8 */ |
| #define | MSK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */ |
| #define | MSK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ |
| #define | MSK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */ |
| #define | MSK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */ |
| #define | MSK_ECU_AE_THR 0x0070 /* Almost Empty Threshold */ |
| #define | MSK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */ |
| #define | MSK_ECU_JUMBO_WM 0x01 |
| #define | MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ |
| #define | MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ |
| #define | MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */ |
| #define | Q_R1 0x0000 /* Receive Queue 1 */ |
| #define | Q_R2 0x0080 /* Receive Queue 2 */ |
| #define | Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */ |
| #define | Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */ |
| #define | Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ |
| #define | Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ |
| #define | Q_ASF_R1 0x100 /* ASF Rx Queue 1 */ |
| #define | Q_ASF_R2 0x180 /* ASF Rx Queue 2 */ |
| #define | Q_ASF_T1 0x140 /* ASF Tx Queue 1 */ |
| #define | Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */ |
| #define | RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) |
| #define | MSK_MIN_RXQ_SIZE 10 |
| #define | MSK_MIN_TXQ_SIZE 10 |
| #define | MSK_RAM_QUOTA_RX 80 |
| #define | WOL_CTL_LINK_CHG_OCC BIT_15 |
| #define | WOL_CTL_MAGIC_PKT_OCC BIT_14 |
| #define | WOL_CTL_PATTERN_OCC BIT_13 |
| #define | WOL_CTL_CLEAR_RESULT BIT_12 |
| #define | WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11 |
| #define | WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10 |
| #define | WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9 |
| #define | WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8 |
| #define | WOL_CTL_ENA_PME_ON_PATTERN BIT_7 |
| #define | WOL_CTL_DIS_PME_ON_PATTERN BIT_6 |
| #define | WOL_CTL_ENA_LINK_CHG_UNIT BIT_5 |
| #define | WOL_CTL_DIS_LINK_CHG_UNIT BIT_4 |
| #define | WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3 |
| #define | WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2 |
| #define | WOL_CTL_ENA_PATTERN_UNIT BIT_1 |
| #define | WOL_CTL_DIS_PATTERN_UNIT BIT_0 |
| #define | WOL_CTL_DEFAULT |
| #define | WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) |
| #define | WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */ |
| #define | WOL_PATT_MATCH_PME_ALL 0x7f |
| #define | PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */ |
| #define | PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */ |
| #define | PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ |
| #define | PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ |
| #define | PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ |
| #define | PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ |
| #define | PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ |
| #define | PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ |
| #define | PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ |
| #define | PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ |
| #define | PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ |
| #define | PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ |
| #define | PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */ |
| #define | PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */ |
| #define | PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ |
| #define | PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ |
| #define | PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ |
| #define | PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ |
| #define | PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ |
| #define | PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */ |
| #define | PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ |
| #define | PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ |
| #define | PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ |
| #define | PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ |
| #define | PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ |
| #define | PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */ |
| #define | PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */ |
| #define | PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */ |
| #define | PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */ |
| #define | PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */ |
| #define | PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */ |
| #define | PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */ |
| #define | PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ |
| #define | PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ |
| #define | PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */ |
| #define | PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ |
| #define | PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */ |
| #define | PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */ |
| #define | PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ |
| #define | PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ |
| #define | PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */ |
| #define | PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */ |
| #define | PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ |
| #define | PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */ |
| #define | PHY_CT_SP10 (0) /* enable speed of 10 Mbps */ |
| #define | PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ |
| #define | PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */ |
| #define | PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ |
| #define | PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occurred */ |
| #define | PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ |
| #define | PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ |
| #define | PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */ |
| #define | PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ |
| #define | PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ |
| #define | PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ |
| #define | PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */ |
| #define | PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */ |
| #define | PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1011) */ |
| #define | PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */ |
| #define | PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */ |
| #define | PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */ |
| #define | PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */ |
| #define | PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */ |
| #define | PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ |
| #define | PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ |
| #define | PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ |
| #define | PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ |
| #define | PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ |
| #define | PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ |
| #define | PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ |
| #define | PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ |
| #define | PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ |
| #define | PHY_M_AN_RF BIT_13 /* Remote Fault */ |
| #define | PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ |
| #define | PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ |
| #define | PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */ |
| #define | PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ |
| #define | PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ |
| #define | PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ |
| #define | PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ |
| #define | PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */ |
| #define | PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ |
| #define | PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ |
| #define | PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ |
| #define | PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ |
| #define | PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ |
| #define | PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */ |
| #define | PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */ |
| #define | PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */ |
| #define | PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ |
| #define | PHY_M_1000C_MSE BIT_12 /* Manual Master/Slave Enable */ |
| #define | PHY_M_1000C_MSC BIT_11 /* M/S Configuration (1=Master) */ |
| #define | PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */ |
| #define | PHY_M_1000C_AFD BIT_9 /* Advertise Full Duplex */ |
| #define | PHY_M_1000C_AHD BIT_8 /* Advertise Half Duplex */ |
| #define | PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ |
| #define | PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ |
| #define | PHY_M_PC_ASS_CRS_TX BIT_11 /* Assert CRS on Transmit */ |
| #define | PHY_M_PC_FL_GOOD BIT_10 /* Force Link Good */ |
| #define | PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ |
| #define | PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */ |
| #define | PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ |
| #define | PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */ |
| #define | PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */ |
| #define | PHY_M_PC_SQE_T_ENA BIT_2 /* SQE Test Enabled */ |
| #define | PHY_M_PC_POL_R_DIS BIT_1 /* Polarity Reversal Disabled */ |
| #define | PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */ |
| #define | PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */ |
| #define | PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */ |
| #define | PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK) |
| #define | PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ |
| #define | PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ |
| #define | PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ |
| #define | PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */ |
| #define | PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */ |
| #define | PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */ |
| #define | PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK) |
| #define | PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */ |
| #define | PHY_M_PC_ENA_ENE_DT BIT_14 /* Enable Energy Detect (sense & pulse) */ |
| #define | PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */ |
| #define | PHY_M_PC_ENA_LIP_NP BIT_12 /* Enable Link Partner Next Page Reg. */ |
| #define | PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */ |
| #define | PHY_M_PC_DIS_SCRAMB BIT_9 /* Disable Scrambler */ |
| #define | PHY_M_PC_DIS_FEFI BIT_8 /* Disable Far End Fault Indic. (FEFI) */ |
| #define | PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */ |
| #define | PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */ |
| #define | PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ |
| #define | PHY_M_PS_SPEED_1000 BIT_15 /* 10 = 1000 Mbps */ |
| #define | PHY_M_PS_SPEED_100 BIT_14 /* 01 = 100 Mbps */ |
| #define | PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ |
| #define | PHY_M_PS_FULL_DUP BIT_13 /* Full Duplex */ |
| #define | PHY_M_PS_PAGE_REC BIT_12 /* Page Received */ |
| #define | PHY_M_PS_SPDUP_RES BIT_11 /* Speed & Duplex Resolved */ |
| #define | PHY_M_PS_LINK_UP BIT_10 /* Link Up */ |
| #define | PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */ |
| #define | PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */ |
| #define | PHY_M_PS_DOWNS_STAT BIT_5 /* Downshift Status (1=downsh.) */ |
| #define | PHY_M_PS_ENDET_STAT BIT_4 /* Energy Detect Status (1=act) */ |
| #define | PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */ |
| #define | PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */ |
| #define | PHY_M_PS_POL_REV BIT_1 /* Polarity Reversed */ |
| #define | PHY_M_PS_JABBER BIT_0 /* Jabber */ |
| #define | PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) |
| #define | PHY_M_PS_DTE_DETECT BIT_15 /* Data Terminal Equipment (DTE) Detected */ |
| #define | PHY_M_PS_RES_SPEED BIT_14 /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ |
| #define | PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */ |
| #define | PHY_M_IS_LSP_CHANGE BIT_14 /* Link Speed Changed */ |
| #define | PHY_M_IS_DUP_CHANGE BIT_13 /* Duplex Mode Changed */ |
| #define | PHY_M_IS_AN_PR BIT_12 /* Page Received */ |
| #define | PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */ |
| #define | PHY_M_IS_LST_CHANGE BIT_10 /* Link Status Changed */ |
| #define | PHY_M_IS_SYMB_ERROR BIT_9 /* Symbol Error */ |
| #define | PHY_M_IS_FALSE_CARR BIT_8 /* False Carrier */ |
| #define | PHY_M_IS_FIFO_ERROR BIT_7 /* FIFO Overflow/Underrun Error */ |
| #define | PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */ |
| #define | PHY_M_IS_DOWNSH_DET BIT_5 /* Downshift Detected */ |
| #define | PHY_M_IS_END_CHANGE BIT_4 /* Energy Detect Changed */ |
| #define | PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */ |
| #define | PHY_M_IS_POL_CHANGE BIT_1 /* Polarity Changed */ |
| #define | PHY_M_IS_JABBER BIT_0 /* Jabber */ |
| #define | PHY_M_DEF_MSK |
| #define | PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */ |
| #define | PHY_M_EC_ENA_LIN_LB BIT_14 /* Enable Line Loopback (88E1111 only) */ |
| #define | PHY_M_EC_DIS_LINK_P BIT_12 /* Disable Link Pulses (88E1111 only) */ |
| #define | PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */ |
| #define | PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */ |
| #define | PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */ |
| #define | PHY_M_EC_DOWN_S_ENA BIT_8 /* Downshift Enable (88E1111 only) */ |
| #define | PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/ |
| #define | PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ |
| #define | PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */ |
| #define | PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */ |
| #define | PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */ |
| #define | PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */ |
| #define | PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK) |
| #define | PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK) |
| #define | PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK) |
| #define | PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2) |
| #define | MAC_TX_CLK_0_MHZ 2 |
| #define | MAC_TX_CLK_2_5_MHZ 6 |
| #define | MAC_TX_CLK_25_MHZ 7 |
| #define | PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */ |
| #define | PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ |
| #define | PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */ |
| #define | PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ |
| #define | PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */ |
| #define | PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */ |
| #define | PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */ |
| #define | PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ |
| #define | PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */ |
| #define | PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */ |
| #define | PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */ |
| #define | PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */ |
| #define | PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */ |
| #define | PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK) |
| #define | PULS_NO_STR 0 /* no pulse stretching */ |
| #define | PULS_21MS 1 /* 21 ms to 42 ms */ |
| #define | PULS_42MS 2 /* 42 ms to 84 ms */ |
| #define | PULS_84MS 3 /* 84 ms to 170 ms */ |
| #define | PULS_170MS 4 /* 170 ms to 340 ms */ |
| #define | PULS_340MS 5 /* 340 ms to 670 ms */ |
| #define | PULS_670MS 6 /* 670 ms to 1.3 s */ |
| #define | PULS_1300MS 7 /* 1.3 s to 2.7 s */ |
| #define | PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK) |
| #define | BLINK_42MS 0 /* 42 ms */ |
| #define | BLINK_84MS 1 /* 84 ms */ |
| #define | BLINK_170MS 2 /* 170 ms */ |
| #define | BLINK_340MS 3 /* 340 ms */ |
| #define | BLINK_670MS 4 /* 670 ms */ |
| #define | PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */ |
| #define | PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ |
| #define | PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ |
| #define | PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ |
| #define | PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */ |
| #define | PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */ |
| #define | PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */ |
| #define | MO_LED_NORM 0 |
| #define | MO_LED_BLINK 1 |
| #define | MO_LED_OFF 2 |
| #define | MO_LED_ON 3 |
| #define | PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */ |
| #define | PHY_M_EC2_FO_IMPED BIT_5 /* Fiber Output Impedance */ |
| #define | PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */ |
| #define | PHY_M_EC2_FO_BOOST BIT_3 /* Fiber Output Boost */ |
| #define | PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ |
| #define | PHY_M_FC_AUTO_SEL BIT_15 /* Fiber/Copper Auto Sel. Dis. */ |
| #define | PHY_M_FC_AN_REG_ACC BIT_14 /* Fiber/Copper AN Reg. Access */ |
| #define | PHY_M_FC_RESOLUTION BIT_13 /* Fiber/Copper Resolution */ |
| #define | PHY_M_SER_IF_AN_BP BIT_12 /* Ser. IF AN Bypass Enable */ |
| #define | PHY_M_SER_IF_BP_ST BIT_11 /* Ser. IF AN Bypass Status */ |
| #define | PHY_M_IRQ_POLARITY BIT_10 /* IRQ polarity */ |
| #define | PHY_M_DIS_AUT_MED BIT_9 /* Disable Aut. Medium Reg. Selection */ |
| #define | PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */ |
| #define | PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */ |
| #define | PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ |
| #define | PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */ |
| #define | PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */ |
| #define | PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */ |
| #define | PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */ |
| #define | PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */ |
| #define | CABD_STAT_NORMAL 0 |
| #define | CABD_STAT_SHORT 1 |
| #define | CABD_STAT_OPEN 2 |
| #define | CABD_STAT_FAIL 3 |
| #define | PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */ |
| #define | PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */ |
| #define | PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */ |
| #define | PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK) |
| #define | PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK) |
| #define | PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK) |
| #define | LED_PAR_CTRL_COLX 0x00 |
| #define | LED_PAR_CTRL_ERROR 0x01 |
| #define | LED_PAR_CTRL_DUPLEX 0x02 |
| #define | LED_PAR_CTRL_DP_COL 0x03 |
| #define | LED_PAR_CTRL_SPEED 0x04 |
| #define | LED_PAR_CTRL_LINK 0x05 |
| #define | LED_PAR_CTRL_TX 0x06 |
| #define | LED_PAR_CTRL_RX 0x07 |
| #define | LED_PAR_CTRL_ACT 0x08 |
| #define | LED_PAR_CTRL_LNK_RX 0x09 |
| #define | LED_PAR_CTRL_LNK_AC 0x0a |
| #define | LED_PAR_CTRL_ACT_BL 0x0b |
| #define | LED_PAR_CTRL_TX_BL 0x0c |
| #define | LED_PAR_CTRL_RX_BL 0x0d |
| #define | LED_PAR_CTRL_COL_BL 0x0e |
| #define | LED_PAR_CTRL_INACT 0x0f |
| #define | PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */ |
| #define | PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */ |
| #define | PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */ |
| #define | PHY_M_FIB_FORCE_LNK BIT_10 /* Force Link Good */ |
| #define | PHY_M_FIB_SIGD_POL BIT_9 /* SIGDET Polarity */ |
| #define | PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */ |
| #define | PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */ |
| #define | PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */ |
| #define | PHY_M_MAC_MD_COPPER 5 /* Copper only */ |
| #define | PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */ |
| #define | PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK) |
| #define | PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */ |
| #define | PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */ |
| #define | PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */ |
| #define | PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ |
| #define | PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK) |
| #define | PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK) |
| #define | PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK) |
| #define | PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK) |
| #define | PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */ |
| #define | PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ |
| #define | PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ |
| #define | PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ |
| #define | PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ |
| #define | PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ |
| #define | PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK) |
| #define | PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK) |
| #define | PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK) |
| #define | PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK) |
| #define | PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK) |
| #define | PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK) |
| #define | GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */ |
| #define | GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ |
| #define | GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ |
| #define | GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ |
| #define | GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */ |
| #define | GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ |
| #define | GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ |
| #define | GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */ |
| #define | GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */ |
| #define | GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */ |
| #define | GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */ |
| #define | GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */ |
| #define | GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */ |
| #define | GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */ |
| #define | GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */ |
| #define | GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */ |
| #define | GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */ |
| #define | GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */ |
| #define | GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */ |
| #define | GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */ |
| #define | GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */ |
| #define | GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */ |
| #define | GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */ |
| #define | GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */ |
| #define | GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */ |
| #define | GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */ |
| #define | GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ |
| #define | GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ |
| #define | GM_RXF_UC_OK (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */ |
| #define | GM_RXF_BC_OK (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */ |
| #define | GM_RXF_MPAUSE (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */ |
| #define | GM_RXF_MC_OK (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */ |
| #define | GM_RXF_FCS_ERR (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */ |
| #define | GM_RXF_SPARE1 (GM_MIB_CNT_BASE + 40) /* Rx spare 1 */ |
| #define | GM_RXO_OK_LO (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */ |
| #define | GM_RXO_OK_HI (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */ |
| #define | GM_RXO_ERR_LO (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */ |
| #define | GM_RXO_ERR_HI (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */ |
| #define | GM_RXF_SHT (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ |
| #define | GM_RXE_FRAG (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */ |
| #define | GM_RXF_64B (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ |
| #define | GM_RXF_127B (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */ |
| #define | GM_RXF_255B (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */ |
| #define | GM_RXF_511B (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */ |
| #define | GM_RXF_1023B (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */ |
| #define | GM_RXF_1518B (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */ |
| #define | GM_RXF_MAX_SZ (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */ |
| #define | GM_RXF_LNG_ERR (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */ |
| #define | GM_RXF_JAB_PKT (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */ |
| #define | GM_RXF_SPARE2 (GM_MIB_CNT_BASE + 168) /* Rx spare 2 */ |
| #define | GM_RXE_FIFO_OV (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */ |
| #define | GM_RXF_SPARE3 (GM_MIB_CNT_BASE + 184) /* Rx spare 3 */ |
| #define | GM_TXF_UC_OK (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */ |
| #define | GM_TXF_BC_OK (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */ |
| #define | GM_TXF_MPAUSE (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */ |
| #define | GM_TXF_MC_OK (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */ |
| #define | GM_TXO_OK_LO (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */ |
| #define | GM_TXO_OK_HI (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */ |
| #define | GM_TXF_64B (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */ |
| #define | GM_TXF_127B (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */ |
| #define | GM_TXF_255B (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */ |
| #define | GM_TXF_511B (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */ |
| #define | GM_TXF_1023B (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */ |
| #define | GM_TXF_1518B (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */ |
| #define | GM_TXF_MAX_SZ (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */ |
| #define | GM_TXF_SPARE1 (GM_MIB_CNT_BASE + 296) /* Tx spare 1 */ |
| #define | GM_TXF_COL (GM_MIB_CNT_BASE + 304) /* Tx Collision */ |
| #define | GM_TXF_LAT_COL (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */ |
| #define | GM_TXF_ABO_COL (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */ |
| #define | GM_TXF_MUL_COL (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */ |
| #define | GM_TXF_SNG_COL (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */ |
| #define | GM_TXE_FIFO_UR (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */ |
| #define | GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */ |
| #define | GM_GPSR_DUPLEX BIT_14 /* Duplex Mode (1 = Full) */ |
| #define | GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */ |
| #define | GM_GPSR_LINK_UP BIT_12 /* Link Up Status */ |
| #define | GM_GPSR_PAUSE BIT_11 /* Pause State */ |
| #define | GM_GPSR_TX_ACTIVE BIT_10 /* Tx in Progress */ |
| #define | GM_GPSR_EXC_COL BIT_9 /* Excessive Collisions Occurred */ |
| #define | GM_GPSR_LAT_COL BIT_8 /* Late Collisions Occurred */ |
| #define | GM_GPSR_PHY_ST_CH BIT_5 /* PHY Status Change */ |
| #define | GM_GPSR_GIG_SPEED BIT_4 /* Gigabit Speed (1 = 1000 Mbps) */ |
| #define | GM_GPSR_PART_MODE BIT_3 /* Partition mode */ |
| #define | GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */ |
| #define | GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */ |
| #define | GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */ |
| #define | GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */ |
| #define | GM_GPCR_TX_ENA BIT_12 /* Enable Transmit */ |
| #define | GM_GPCR_RX_ENA BIT_11 /* Enable Receive */ |
| #define | GM_GPCR_LOOP_ENA BIT_9 /* Enable MAC Loopback Mode */ |
| #define | GM_GPCR_PART_ENA BIT_8 /* Enable Partition Mode */ |
| #define | GM_GPCR_GIGS_ENA BIT_7 /* Gigabit Speed (1000 Mbps) */ |
| #define | GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */ |
| #define | GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */ |
| #define | GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */ |
| #define | GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */ |
| #define | GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */ |
| #define | GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */ |
| #define | GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */ |
| #define | GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) |
| #define | GM_GPCR_AU_ALL_DIS |
| #define | GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */ |
| #define | GM_TXCR_CRC_DIS BIT_14 /* Disable insertion of CRC */ |
| #define | GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */ |
| #define | GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */ |
| #define | GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */ |
| #define | TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK) |
| #define | TX_COL_DEF 0x04 |
| #define | GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */ |
| #define | GM_RXCR_MCF_ENA BIT_14 /* Enable Multicast filtering */ |
| #define | GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */ |
| #define | GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */ |
| #define | GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */ |
| #define | GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */ |
| #define | GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */ |
| #define | GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */ |
| #define | TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK) |
| #define | TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK) |
| #define | TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK) |
| #define | TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) |
| #define | TX_JAM_LEN_DEF 0x03 |
| #define | TX_JAM_IPG_DEF 0x0b |
| #define | TX_IPG_JAM_DEF 0x1c |
| #define | TX_BOF_LIM_DEF 0x04 |
| #define | GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ |
| #define | GM_SMOD_LIMIT_4 BIT_10 /* 4 consecutive Tx trials */ |
| #define | GM_SMOD_VLAN_ENA BIT_9 /* Enable VLAN (Max. Frame Len) */ |
| #define | GM_SMOD_JUMBO_ENA BIT_8 /* Enable Jumbo (Max. Frame Len) */ |
| #define | GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */ |
| #define | DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK) |
| #define | IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK) |
| #define | DATA_BLIND_DEF 0x04 |
| #define | IPG_DATA_DEF 0x1e |
| #define | GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */ |
| #define | GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */ |
| #define | GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/ |
| #define | GM_SMI_CT_RD_VAL BIT_4 /* Read Valid (Read completed) */ |
| #define | GM_SMI_CT_BUSY BIT_3 /* Busy (Operation in progress) */ |
| #define | GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK) |
| #define | GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK) |
| #define | GM_PAR_MIB_CLR BIT_5 /* Set MIB Clear Counter Mode */ |
| #define | GM_PAR_MIB_TST BIT_4 /* MIB Load Counter (Test Mode) */ |
| #define | GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */ |
| #define | GMR_FS_VLAN BIT_13 /* VLAN Packet */ |
| #define | GMR_FS_JABBER BIT_12 /* Jabber Packet */ |
| #define | GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */ |
| #define | GMR_FS_MC BIT_10 /* Multicast Packet */ |
| #define | GMR_FS_BC BIT_9 /* Broadcast Packet */ |
| #define | GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */ |
| #define | GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */ |
| #define | GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */ |
| #define | GMR_FS_MII_ERR BIT_5 /* MII Error */ |
| #define | GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */ |
| #define | GMR_FS_FRAGMENT BIT_3 /* Fragment */ |
| #define | GMR_FS_CRC_ERR BIT_1 /* CRC Error */ |
| #define | GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */ |
| #define | GMR_FS_LEN_SHIFT 16 |
| #define | GMR_FS_ANY_ERR |
| #define | RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR |
| #define | RX_TRUNC_ON BIT_27 /* enable packet truncation */ |
| #define | RX_TRUNC_OFF BIT_26 /* disable packet truncation */ |
| #define | RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ |
| #define | RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ |
| #define | GMF_RX_MACSEC_FLUSH_ON BIT_23 |
| #define | GMF_RX_MACSEC_FLUSH_OFF BIT_22 |
| #define | GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */ |
| #define | GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */ |
| #define | GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */ |
| #define | GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */ |
| #define | GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ |
| #define | GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ |
| #define | GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ |
| #define | GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ |
| #define | GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ |
| #define | GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ |
| #define | GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ |
| #define | GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ |
| #define | GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ |
| #define | GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ |
| #define | GMF_OPER_ON BIT_3 /* Operational Mode On */ |
| #define | GMF_OPER_OFF BIT_2 /* Operational Mode Off */ |
| #define | GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ |
| #define | GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ |
| #define | TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */ |
| #define | TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */ |
| #define | TX_VLAN_TAG_ON BIT_25 /* enable VLAN tagging */ |
| #define | TX_VLAN_TAG_OFF BIT_24 /* disable VLAN tagging */ |
| #define | TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */ |
| #define | TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */ |
| #define | GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ |
| #define | GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ |
| #define | GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ |
| #define | GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ |
| #define | GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ |
| #define | GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ |
| #define | GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) |
| #define | GMF_TX_CTRL_DEF GMF_OPER_ON |
| #define | RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */ |
| #define | RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ |
| #define | GMT_ST_START BIT_2 /* Start Time Stamp Timer */ |
| #define | GMT_ST_STOP BIT_1 /* Stop Time Stamp Timer */ |
| #define | GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */ |
| #define | PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */ |
| #define | PC_POLL_RQ BIT_4 /* Poll Request Start */ |
| #define | PC_POLL_OP_ON BIT_3 /* Operational Mode On */ |
| #define | PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */ |
| #define | PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */ |
| #define | PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */ |
| #define | Y2_ASF_OS_PRES BIT_4 /* ASF operation system present */ |
| #define | Y2_ASF_RESET BIT_3 /* ASF system in reset state */ |
| #define | Y2_ASF_RUNNING BIT_2 /* ASF system operational */ |
| #define | Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */ |
| #define | Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */ |
| #define | Y2_ASF_UC_STATE (3<<2) /* ASF uC State */ |
| #define | Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */ |
| #define | Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27 /* SMBALERT pin monitor */ |
| #define | Y2_ASF_HCU_CCSR_CPU_SLEEP BIT_26 /* CPU sleep status */ |
| #define | Y2_ASF_HCU_CCSR_CS_TO BIT_25 /* Clock Stretching Timeout */ |
| #define | Y2_ASF_HCU_CCSR_WDOG BIT_24 /* Watchdog Reset */ |
| #define | Y2_ASF_HCU_CCSR_CLR_IRQ_HOST BIT_17 /* Clear IRQ_HOST */ |
| #define | Y2_ASF_HCU_CCSR_SET_IRQ_HCU BIT_16 /* Set IRQ_HCU */ |
| #define | Y2_ASF_HCU_CCSR_AHB_RST BIT_9 /* Reset AHB bridge */ |
| #define | Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8 /* CPU Reset Mode */ |
| #define | Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5 |
| #define | Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4 |
| #define | Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3 |
| #define | Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */ |
| #define | Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3 |
| #define | Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */ |
| #define | Y2_ASF_HCU_CCSR_UC_STATE_MSK 3 |
| #define | Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0 |
| #define | Y2_ASF_HCU_CCSR_ASF_RESET 0 |
| #define | Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1 |
| #define | Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0 |
| #define | Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */ |
| #define | Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */ |
| #define | SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */ |
| #define | SC_STAT_OP_ON BIT_3 /* Operational Mode On */ |
| #define | SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */ |
| #define | SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */ |
| #define | SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */ |
| #define | GMC_SEC_RST BIT_15 /* MAC SEC RST */ |
| #define | GMC_SEC_RST_OFF BIT_14 /* MAC SEC RST Off */ |
| #define | GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */ |
| #define | GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */ |
| #define | GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */ |
| #define | GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */ |
| #define | GMC_BYP_RETR_ON BIT_9 /* Bypass MAC retransmit FIFO On */ |
| #define | GMC_BYP_RETR_OFF BIT_8 /* Bypass MAC retransmit FIFO Off */ |
| #define | GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ |
| #define | GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ |
| #define | GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ |
| #define | GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ |
| #define | GMC_PAUSE_ON BIT_3 /* Pause On */ |
| #define | GMC_PAUSE_OFF BIT_2 /* Pause Off */ |
| #define | GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ |
| #define | GMC_RST_SET BIT_0 /* Set GMAC Reset */ |
| #define | GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ |
| #define | GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */ |
| #define | GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ |
| #define | GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ |
| #define | GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ |
| #define | GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */ |
| #define | GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */ |
| #define | GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */ |
| #define | GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */ |
| #define | GPC_ANEG_0 BIT_19 /* ANEG[0] */ |
| #define | GPC_ENA_XC BIT_18 /* Enable MDI crossover */ |
| #define | GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */ |
| #define | GPC_ANEG_3 BIT_16 /* ANEG[3] */ |
| #define | GPC_ANEG_2 BIT_15 /* ANEG[2] */ |
| #define | GPC_ANEG_1 BIT_14 /* ANEG[1] */ |
| #define | GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ |
| #define | GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */ |
| #define | GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */ |
| #define | GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */ |
| #define | GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */ |
| #define | GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */ |
| #define | GPC_RST_CLR BIT_1 /* Clear GPHY Reset */ |
| #define | GPC_RST_SET BIT_0 /* Set GPHY Reset */ |
| #define | GM_IS_RX_CO_OV BIT_5 /* Receive Counter Overflow IRQ */ |
| #define | GM_IS_TX_CO_OV BIT_4 /* Transmit Counter Overflow IRQ */ |
| #define | GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ |
| #define | GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ |
| #define | GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ |
| #define | GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ |
| #define | GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR) |
| #define | GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */ |
| #define | GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */ |
| #define | MSK_PORT_A 0 |
| #define | MSK_PORT_B 1 |
| #define | CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->msk_res[0], (reg), (val)) |
| #define | CSR_WRITE_2(sc, reg, val) bus_write_2((sc)->msk_res[0], (reg), (val)) |
| #define | CSR_WRITE_1(sc, reg, val) bus_write_1((sc)->msk_res[0], (reg), (val)) |
| #define | CSR_READ_4(sc, reg) bus_read_4((sc)->msk_res[0], (reg)) |
| #define | CSR_READ_2(sc, reg) bus_read_2((sc)->msk_res[0], (reg)) |
| #define | CSR_READ_1(sc, reg) bus_read_1((sc)->msk_res[0], (reg)) |
| #define | CSR_PCI_WRITE_4(sc, reg, val) bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) |
| #define | CSR_PCI_WRITE_2(sc, reg, val) bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) |
| #define | CSR_PCI_WRITE_1(sc, reg, val) bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) |
| #define | CSR_PCI_READ_4(sc, reg) bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg)) |
| #define | CSR_PCI_READ_2(sc, reg) bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg)) |
| #define | CSR_PCI_READ_1(sc, reg) bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg)) |
| #define | MSK_IF_READ_4(sc_if, reg) CSR_READ_4((sc_if)->msk_softc, (reg)) |
| #define | MSK_IF_READ_2(sc_if, reg) CSR_READ_2((sc_if)->msk_softc, (reg)) |
| #define | MSK_IF_READ_1(sc_if, reg) CSR_READ_1((sc_if)->msk_softc, (reg)) |
| #define | MSK_IF_WRITE_4(sc_if, reg, val) CSR_WRITE_4((sc_if)->msk_softc, (reg), (val)) |
| #define | MSK_IF_WRITE_2(sc_if, reg, val) CSR_WRITE_2((sc_if)->msk_softc, (reg), (val)) |
| #define | MSK_IF_WRITE_1(sc_if, reg, val) CSR_WRITE_1((sc_if)->msk_softc, (reg), (val)) |
| #define | GMAC_REG(port, reg) ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg)) |
| #define | GMAC_WRITE_2(sc, port, reg, val) CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val)) |
| #define | GMAC_READ_2(sc, port, reg) CSR_READ_2((sc), GMAC_REG((port), (reg))) |
| #define | PHY_ADDR_MARV 0 |
| #define | MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) |
| #define | MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) |
| #define | MSK_RING_ALIGN 32768 |
| #define | MSK_STAT_ALIGN 32768 |
| #define | STLE_TXA1_MSKL 0x00000fff |
| #define | STLE_TXA1_SHIFTL 0 |
| #define | STLE_TXS1_MSKL 0x00fff000 |
| #define | STLE_TXS1_SHIFTL 12 |
| #define | STLE_TXA2_MSKL 0xff000000 |
| #define | STLE_TXA2_SHIFTL 24 |
| #define | STLE_TXA2_MSKH 0x000f |
| #define | STLE_TXA2_SHIFTH 8 |
| #define | STLE_TXS2_MSKL 0x00000000 |
| #define | STLE_TXS2_SHIFTL 0 |
| #define | STLE_TXS2_MSKH 0xfff0 |
| #define | STLE_TXS2_SHIFTH 4 |
| #define | HW_OWNER 0x80000000 |
| #define | SW_OWNER 0x00000000 |
| #define | PU_PUTIDX_VALID 0x10000000 |
| #define | UDPTCP 0x00010000 |
| #define | CALSUM 0x00020000 |
| #define | WR_SUM 0x00040000 |
| #define | INIT_SUM 0x00080000 |
| #define | LOCK_SUM 0x00100000 |
| #define | INS_VLAN 0x00200000 |
| #define | FRC_STAT 0x00400000 |
| #define | EOP 0x00800000 |
| #define | TX_LOCK 0x01000000 |
| #define | BUF_SEND 0x02000000 |
| #define | PACKET_SEND 0x04000000 |
| #define | NO_WARNING 0x40000000 |
| #define | NO_UPDATE 0x80000000 |
| #define | OP_TCPWRITE 0x11000000 |
| #define | OP_TCPSTART 0x12000000 |
| #define | OP_TCPINIT 0x14000000 |
| #define | OP_TCPLCK 0x18000000 |
| #define | OP_TCPCHKSUM OP_TCPSTART |
| #define | OP_TCPIS (OP_TCPINIT | OP_TCPSTART) |
| #define | OP_TCPLW (OP_TCPLCK | OP_TCPWRITE) |
| #define | OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE) |
| #define | OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE) |
| #define | OP_ADDR64 0x21000000 |
| #define | OP_VLAN 0x22000000 |
| #define | OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN) |
| #define | OP_LRGLEN 0x24000000 |
| #define | OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN) |
| #define | OP_MSS 0x28000000 |
| #define | OP_MSSVLAN (OP_MSS | OP_VLAN) |
| #define | OP_BUFFER 0x40000000 |
| #define | OP_PACKET 0x41000000 |
| #define | OP_LARGESEND 0x43000000 |
| #define | OP_RXSTAT 0x60000000 |
| #define | OP_RXTIMESTAMP 0x61000000 |
| #define | OP_RXVLAN 0x62000000 |
| #define | OP_RXCHKS 0x64000000 |
| #define | OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN) |
| #define | OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN) |
| #define | OP_RSS_HASH 0x65000000 |
| #define | OP_TXINDEXLE 0x68000000 |
| #define | OP_PUTIDX 0x70000000 |
| #define | STLE_OP_MASK 0xff000000 |
| #define | STLE_CSS_MASK 0x00ff0000 |
| #define | STLE_LEN_MASK 0x0000ffff |
| #define | CSS_TCPUDP_CSUM_OK 0x00800000 |
| #define | CSS_UDP 0x00400000 |
| #define | CSS_TCP 0x00200000 |
| #define | CSS_IPFRAG 0x00100000 |
| #define | CSS_IPV6 0x00080000 |
| #define | CSS_IPV4_CSUM_OK 0x00040000 |
| #define | CSS_IPV4 0x00020000 |
| #define | CSS_PORT 0x00010000 |
| #define | BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */ |
| #define | BMU_STF BIT_30 /* Start of Frame */ |
| #define | BMU_EOF BIT_29 /* End of Frame */ |
| #define | BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */ |
| #define | BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */ |
| #define | BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */ |
| #define | BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */ |
| #define | BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */ |
| #define | BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */ |
| #define | BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */ |
| #define | BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */ |
| #define | BMU_CHECK (0x55<<16) /* Default BMU check */ |
| #define | BMU_TCP_CHECK (0x56<<16) /* Descr with TCP ext */ |
| #define | BMU_UDP_CHECK (0x57<<16) /* Descr with UDP ext (YUKON only) */ |
| #define | BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */ |
| #define | MSK_TX_RING_CNT 256 |
| #define | MSK_RX_RING_CNT 256 |
| #define | MSK_RX_BUF_ALIGN 8 |
| #define | MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT |
| #define | MSK_MAXTXSEGS 35 |
| #define | MSK_TSO_MAXSGSIZE 4096 |
| #define | MSK_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) |
| #define | MSK_RESERVED_TX_DESC_CNT 3 |
| #define | MSK_JUMBO_FRAMELEN 9022 |
| #define | MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) |
| #define | MSK_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) |
| #define | MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) |
| #define | MSK_TX_RING_ADDR(sc, i) ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i)) |
| #define | MSK_RX_RING_ADDR(sc, i) ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) |
| #define | MSK_JUMBO_RX_RING_ADDR(sc, i) ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) |
| #define | MSK_TX_RING_SZ (sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT) |
| #define | MSK_RX_RING_SZ (sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT) |
| #define | MSK_JUMBO_RX_RING_SZ (sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT) |
| #define | MSK_INC(x, y) (x) = (x + 1) % y |
| #define | MSK_RX_INC(x, y) (x) = (x + 1) % y |
| #define | MSK_RX_BUF_CNT MSK_RX_RING_CNT |
| #define | MSK_JUMBO_RX_BUF_CNT MSK_JUMBO_RX_RING_CNT |
| #define | MSK_PCI_BUS 0 |
| #define | MSK_PCIX_BUS 1 |
| #define | MSK_PEX_BUS 2 |
| #define | MSK_PROC_DEFAULT (MSK_RX_RING_CNT / 2) |
| #define | MSK_PROC_MIN 30 |
| #define | MSK_PROC_MAX (MSK_RX_RING_CNT - 1) |
| #define | MSK_INT_HOLDOFF_DEFAULT 100 |
| #define | MSK_TX_TIMEOUT 5 |
| #define | MSK_PUT_WM 10 |
| #define | MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx) |
| #define | MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx) |
| #define | MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED) |
| #define | MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc) |
| #define | MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc) |
| #define | MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc) |
| #define | MSK_USECS(sc, us) ((sc)->msk_clock * (us)) |
| #define | MSK_FLAG_MSI 0x0001 |
| #define | MSK_FLAG_FASTETHER 0x0004 |
| #define | MSK_FLAG_JUMBO 0x0008 |
| #define | MSK_FLAG_JUMBO_NOCSUM 0x0010 |
| #define | MSK_FLAG_RAMBUF 0x0020 |
| #define | MSK_FLAG_DESCV2 0x0040 |
| #define | MSK_FLAG_AUTOTX_CSUM 0x0080 |
| #define | MSK_FLAG_NOHWVLAN 0x0100 |
| #define | MSK_FLAG_NORXCHK 0x0200 |
| #define | MSK_FLAG_NORX_CSUM 0x0400 |
| #define | MSK_FLAG_SUSPEND 0x2000 |
| #define | MSK_FLAG_DETACH 0x4000 |
| #define | MSK_FLAG_LINK 0x8000 |
| #define | MSK_TIMEOUT 1000 |
| #define | MSK_PHY_POWERUP 1 |
| #define | MSK_PHY_POWERDOWN 0 |
Macro Definition Documentation
◆ B0_CTST
| #define B0_CTST 0x0004 /* 16 bit Control/Status register */ |
Definition at line 433 of file if_mskreg.h.
◆ B0_HWE_IMSK
| #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ |
Definition at line 439 of file if_mskreg.h.
◆ B0_HWE_ISRC
| #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ |
Definition at line 438 of file if_mskreg.h.
◆ B0_IMSK
| #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ |
Definition at line 437 of file if_mskreg.h.
◆ B0_ISRC
| #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */ |
Definition at line 436 of file if_mskreg.h.
◆ B0_LED
| #define B0_LED 0x0006 /* 8 Bit LED register */ |
Definition at line 434 of file if_mskreg.h.
◆ B0_POWER_CTRL
| #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */ |
Definition at line 435 of file if_mskreg.h.
◆ B0_RAP
| #define B0_RAP 0x0000 /* 8 bit Register Address Port */ |
Definition at line 432 of file if_mskreg.h.
◆ B0_SP_ISRC
| #define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */ |
Definition at line 440 of file if_mskreg.h.
◆ B0_Y2_SP_EISR
| #define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */ |
Definition at line 445 of file if_mskreg.h.
◆ B0_Y2_SP_ICR
| #define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */ |
Definition at line 447 of file if_mskreg.h.
◆ B0_Y2_SP_ISRC2
| #define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */ |
Definition at line 443 of file if_mskreg.h.
◆ B0_Y2_SP_ISRC3
| #define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */ |
Definition at line 444 of file if_mskreg.h.
◆ B0_Y2_SP_LISR
| #define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */ |
Definition at line 446 of file if_mskreg.h.
◆ B16_RAM_REGS
| #define B16_RAM_REGS 0x0800 |
Definition at line 605 of file if_mskreg.h.
◆ B28_DPT_CTRL
| #define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */ |
Definition at line 673 of file if_mskreg.h.
◆ B28_DPT_INI
| #define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */ |
Definition at line 671 of file if_mskreg.h.
◆ B28_DPT_TST
| #define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */ |
Definition at line 674 of file if_mskreg.h.
◆ B28_DPT_VAL
| #define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */ |
Definition at line 672 of file if_mskreg.h.
◆ B28_Y2_ASF_HCU_CCSR
| #define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */ |
Definition at line 690 of file if_mskreg.h.
◆ B28_Y2_ASF_HOST_COM
| #define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */ |
Definition at line 691 of file if_mskreg.h.
◆ B28_Y2_ASF_IRQ_V_BASE
| #define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */ |
Definition at line 688 of file if_mskreg.h.
◆ B28_Y2_ASF_STAT_CMD
| #define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */ |
Definition at line 689 of file if_mskreg.h.
◆ B28_Y2_CPU_WDOG
| #define B28_Y2_CPU_WDOG 0x0e48 /* 32 bit Watchdog Register */ |
Definition at line 687 of file if_mskreg.h.
◆ B28_Y2_DATA_REG_1
| #define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */ |
Definition at line 692 of file if_mskreg.h.
◆ B28_Y2_DATA_REG_2
| #define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */ |
Definition at line 693 of file if_mskreg.h.
◆ B28_Y2_DATA_REG_3
| #define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */ |
Definition at line 694 of file if_mskreg.h.
◆ B28_Y2_DATA_REG_4
| #define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */ |
Definition at line 695 of file if_mskreg.h.
◆ B28_Y2_SMB_CONFIG
| #define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */ |
Definition at line 685 of file if_mskreg.h.
◆ B28_Y2_SMB_CSD_REG
| #define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */ |
Definition at line 686 of file if_mskreg.h.
◆ B2_CHIP_ID
| #define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ |
Definition at line 465 of file if_mskreg.h.
◆ B2_CONN_TYP
| #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */ |
Definition at line 462 of file if_mskreg.h.
◆ B2_E3_RES_MASK
| #define B2_E3_RES_MASK 0x0f |
Definition at line 952 of file if_mskreg.h.
◆ B2_E_0
| #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ |
Definition at line 466 of file if_mskreg.h.
◆ B2_E_3
| #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ |
Definition at line 469 of file if_mskreg.h.
◆ B2_GP_IO
| #define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */ |
Definition at line 483 of file if_mskreg.h.
◆ B2_I2C_CTRL
| #define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */ |
Definition at line 484 of file if_mskreg.h.
◆ B2_I2C_DATA
| #define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */ |
Definition at line 485 of file if_mskreg.h.
◆ B2_I2C_IRQ
| #define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */ |
Definition at line 486 of file if_mskreg.h.
◆ B2_I2C_SW
| #define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */ |
Definition at line 487 of file if_mskreg.h.
◆ B2_IRQM_CTRL
| #define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */ |
Definition at line 477 of file if_mskreg.h.
◆ B2_IRQM_HWE_MSK
| #define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */ |
Definition at line 480 of file if_mskreg.h.
◆ B2_IRQM_INI
| #define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/ |
Definition at line 475 of file if_mskreg.h.
◆ B2_IRQM_MSK
| #define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ |
Definition at line 479 of file if_mskreg.h.
◆ B2_IRQM_TEST
| #define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */ |
Definition at line 478 of file if_mskreg.h.
◆ B2_IRQM_VAL
| #define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */ |
Definition at line 476 of file if_mskreg.h.
◆ B2_MAC_1
| #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */ |
Definition at line 459 of file if_mskreg.h.
◆ B2_MAC_2
| #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */ |
Definition at line 460 of file if_mskreg.h.
◆ B2_MAC_3
| #define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */ |
Definition at line 461 of file if_mskreg.h.
◆ B2_MAC_CFG
| #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ |
Definition at line 464 of file if_mskreg.h.
◆ B2_PMD_TYP
| #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ |
Definition at line 463 of file if_mskreg.h.
◆ B2_TI_CTRL
| #define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */ |
Definition at line 473 of file if_mskreg.h.
◆ B2_TI_INI
| #define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */ |
Definition at line 471 of file if_mskreg.h.
◆ B2_TI_TEST
| #define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */ |
Definition at line 474 of file if_mskreg.h.
◆ B2_TI_VAL
| #define B2_TI_VAL 0x0134 /* 32 bit Timer Value */ |
Definition at line 472 of file if_mskreg.h.
◆ B2_TST_CTRL1
| #define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */ |
Definition at line 481 of file if_mskreg.h.
◆ B2_TST_CTRL2
| #define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */ |
Definition at line 482 of file if_mskreg.h.
◆ B2_Y2_CLK_CTRL
| #define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */ |
Definition at line 470 of file if_mskreg.h.
◆ B2_Y2_CLK_GATE
| #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ |
Definition at line 467 of file if_mskreg.h.
◆ B2_Y2_HW_RES
| #define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */ |
Definition at line 468 of file if_mskreg.h.
◆ B3_RAM_ADDR
| #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ |
Definition at line 496 of file if_mskreg.h.
◆ B3_RAM_DATA_HI
| #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ |
Definition at line 498 of file if_mskreg.h.
◆ B3_RAM_DATA_LO
| #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ |
Definition at line 497 of file if_mskreg.h.
◆ B3_RI_CTRL
| #define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */ |
Definition at line 522 of file if_mskreg.h.
◆ B3_RI_RTO_R1
| #define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */ |
Definition at line 512 of file if_mskreg.h.
◆ B3_RI_RTO_R2
| #define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */ |
Definition at line 518 of file if_mskreg.h.
◆ B3_RI_RTO_XA1
| #define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */ |
Definition at line 513 of file if_mskreg.h.
◆ B3_RI_RTO_XA2
| #define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/ |
Definition at line 519 of file if_mskreg.h.
◆ B3_RI_RTO_XS1
| #define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */ |
Definition at line 514 of file if_mskreg.h.
◆ B3_RI_RTO_XS2
| #define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/ |
Definition at line 520 of file if_mskreg.h.
◆ B3_RI_TEST
| #define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */ |
Definition at line 523 of file if_mskreg.h.
◆ B3_RI_TO_VAL
| #define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */ |
Definition at line 521 of file if_mskreg.h.
◆ B3_RI_WTO_R1
| #define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */ |
Definition at line 509 of file if_mskreg.h.
◆ B3_RI_WTO_R2
| #define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */ |
Definition at line 515 of file if_mskreg.h.
◆ B3_RI_WTO_XA1
| #define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */ |
Definition at line 510 of file if_mskreg.h.
◆ B3_RI_WTO_XA2
| #define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */ |
Definition at line 516 of file if_mskreg.h.
◆ B3_RI_WTO_XS1
| #define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */ |
Definition at line 511 of file if_mskreg.h.
◆ B3_RI_WTO_XS2
| #define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */ |
Definition at line 517 of file if_mskreg.h.
◆ B4_RSS_KEY
| #define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */ |
Definition at line 540 of file if_mskreg.h.
◆ B8_Q_REGS
| #define B8_Q_REGS 0x0400 |
Definition at line 554 of file if_mskreg.h.
◆ BASE_GMAC_1
| #define BASE_GMAC_1 0x2800 /* GMAC 1 registers */ |
Definition at line 780 of file if_mskreg.h.
◆ BASE_GMAC_2
| #define BASE_GMAC_2 0x3800 /* GMAC 2 registers */ |
Definition at line 781 of file if_mskreg.h.
◆ BC_MAX
| #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ |
Definition at line 1094 of file if_mskreg.h.
◆ BIT_0
| #define BIT_0 (1 << 0) |
Definition at line 192 of file if_mskreg.h.
◆ BIT_1
| #define BIT_1 (1 << 1) |
Definition at line 191 of file if_mskreg.h.
◆ BIT_10
| #define BIT_10 (1 << 10) |
Definition at line 182 of file if_mskreg.h.
◆ BIT_11
| #define BIT_11 (1 << 11) |
Definition at line 181 of file if_mskreg.h.
◆ BIT_12
| #define BIT_12 (1 << 12) |
Definition at line 180 of file if_mskreg.h.
◆ BIT_13
| #define BIT_13 (1 << 13) |
Definition at line 179 of file if_mskreg.h.
◆ BIT_14
| #define BIT_14 (1 << 14) |
Definition at line 178 of file if_mskreg.h.
◆ BIT_15
| #define BIT_15 (1 << 15) |
Definition at line 177 of file if_mskreg.h.
◆ BIT_16
| #define BIT_16 (1 << 16) |
Definition at line 176 of file if_mskreg.h.
◆ BIT_17
| #define BIT_17 (1 << 17) |
Definition at line 175 of file if_mskreg.h.
◆ BIT_18
| #define BIT_18 (1 << 18) |
Definition at line 174 of file if_mskreg.h.
◆ BIT_19
| #define BIT_19 (1 << 19) |
Definition at line 173 of file if_mskreg.h.
◆ BIT_2
| #define BIT_2 (1 << 2) |
Definition at line 190 of file if_mskreg.h.
◆ BIT_20
| #define BIT_20 (1 << 20) |
Definition at line 172 of file if_mskreg.h.
◆ BIT_21
| #define BIT_21 (1 << 21) |
Definition at line 171 of file if_mskreg.h.
◆ BIT_22
| #define BIT_22 (1 << 22) |
Definition at line 170 of file if_mskreg.h.
◆ BIT_23
| #define BIT_23 (1 << 23) |
Definition at line 169 of file if_mskreg.h.
◆ BIT_24
| #define BIT_24 (1 << 24) |
Definition at line 168 of file if_mskreg.h.
◆ BIT_25
| #define BIT_25 (1 << 25) |
Definition at line 167 of file if_mskreg.h.
◆ BIT_26
| #define BIT_26 (1 << 26) |
Definition at line 166 of file if_mskreg.h.
◆ BIT_27
| #define BIT_27 (1 << 27) |
Definition at line 165 of file if_mskreg.h.
◆ BIT_28
| #define BIT_28 (1 << 28) |
Definition at line 164 of file if_mskreg.h.
◆ BIT_29
| #define BIT_29 (1 << 29) |
Definition at line 163 of file if_mskreg.h.
◆ BIT_3
| #define BIT_3 (1 << 3) |
Definition at line 189 of file if_mskreg.h.
◆ BIT_30
| #define BIT_30 (1 << 30) |
Definition at line 162 of file if_mskreg.h.
◆ BIT_31
| #define BIT_31 (1U << 31) |
Definition at line 161 of file if_mskreg.h.
◆ BIT_4
| #define BIT_4 (1 << 4) |
Definition at line 188 of file if_mskreg.h.
◆ BIT_5
| #define BIT_5 (1 << 5) |
Definition at line 187 of file if_mskreg.h.
◆ BIT_6
| #define BIT_6 (1 << 6) |
Definition at line 186 of file if_mskreg.h.
◆ BIT_7
| #define BIT_7 (1 << 7) |
Definition at line 185 of file if_mskreg.h.
◆ BIT_8
| #define BIT_8 (1 << 8) |
Definition at line 184 of file if_mskreg.h.
◆ BIT_9
| #define BIT_9 (1 << 9) |
Definition at line 183 of file if_mskreg.h.
◆ BLINK_170MS
| #define BLINK_170MS 2 /* 170 ms */ |
Definition at line 1531 of file if_mskreg.h.
◆ BLINK_340MS
| #define BLINK_340MS 3 /* 340 ms */ |
Definition at line 1532 of file if_mskreg.h.
◆ BLINK_42MS
| #define BLINK_42MS 0 /* 42 ms */ |
Definition at line 1529 of file if_mskreg.h.
◆ BLINK_670MS
| #define BLINK_670MS 4 /* 670 ms */ |
Definition at line 1533 of file if_mskreg.h.
◆ BLINK_84MS
| #define BLINK_84MS 1 /* 84 ms */ |
Definition at line 1530 of file if_mskreg.h.
◆ BMU_BBC
| #define BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */ |
Definition at line 2313 of file if_mskreg.h.
◆ BMU_CHECK
| #define BMU_CHECK (0x55<<16) /* Default BMU check */ |
Definition at line 2310 of file if_mskreg.h.
◆ BMU_CLR_IRQ_CHK
| #define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */ |
Definition at line 1106 of file if_mskreg.h.
◆ BMU_CLR_IRQ_PAR
| #define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */ |
Definition at line 1104 of file if_mskreg.h.
◆ BMU_CLR_IRQ_TCP
| #define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */ |
Definition at line 1105 of file if_mskreg.h.
◆ BMU_CLR_RESET
| #define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR) |
Definition at line 1118 of file if_mskreg.h.
◆ BMU_DEV_0
| #define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */ |
Definition at line 2306 of file if_mskreg.h.
◆ BMU_DIS_RX_CHKSUM
| #define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */ |
Definition at line 1103 of file if_mskreg.h.
◆ BMU_DIS_RX_RSS_HASH
| #define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */ |
Definition at line 1101 of file if_mskreg.h.
◆ BMU_ENA_RX_CHKSUM
| #define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */ |
Definition at line 1102 of file if_mskreg.h.
◆ BMU_ENA_RX_RSS_HASH
| #define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */ |
Definition at line 1100 of file if_mskreg.h.
◆ BMU_EOF
| #define BMU_EOF BIT_29 /* End of Frame */ |
Definition at line 2298 of file if_mskreg.h.
◆ BMU_FIFO_ENA
| #define BMU_FIFO_ENA BIT_5 /* Enable FIFO */ |
Definition at line 1111 of file if_mskreg.h.
◆ BMU_FIFO_OP_OFF
| #define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */ |
Definition at line 1110 of file if_mskreg.h.
◆ BMU_FIFO_OP_ON
| #define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */ |
Definition at line 1109 of file if_mskreg.h.
◆ BMU_FIFO_RST
| #define BMU_FIFO_RST BIT_4 /* Reset FIFO */ |
Definition at line 1112 of file if_mskreg.h.
◆ BMU_IDLE
| #define BMU_IDLE BIT_31 /* BMU Idle State */ |
Definition at line 1097 of file if_mskreg.h.
◆ BMU_IRQ_EOB
| #define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */ |
Definition at line 2299 of file if_mskreg.h.
◆ BMU_IRQ_EOF
| #define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */ |
Definition at line 2300 of file if_mskreg.h.
◆ BMU_NO_FCS
| #define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */ |
Definition at line 2303 of file if_mskreg.h.
◆ BMU_OP_OFF
| #define BMU_OP_OFF BIT_2 /* BMU Operational Off */ |
Definition at line 1114 of file if_mskreg.h.
◆ BMU_OP_ON
| #define BMU_OP_ON BIT_3 /* BMU Operational On */ |
Definition at line 1113 of file if_mskreg.h.
◆ BMU_OPER_INIT
| #define BMU_OPER_INIT |
Definition at line 1119 of file if_mskreg.h.
◆ BMU_OWN
| #define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */ |
Definition at line 2296 of file if_mskreg.h.
◆ BMU_RST_CLR
| #define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */ |
Definition at line 1115 of file if_mskreg.h.
◆ BMU_RST_SET
| #define BMU_RST_SET BIT_0 /* Set BMU Reset */ |
Definition at line 1116 of file if_mskreg.h.
◆ BMU_RX_IP_PKT
| #define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */ |
Definition at line 1099 of file if_mskreg.h.
◆ BMU_RX_TCP_PKT
| #define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */ |
Definition at line 1098 of file if_mskreg.h.
◆ BMU_START
| #define BMU_START BIT_8 /* Start Rx/Tx Queue */ |
Definition at line 1108 of file if_mskreg.h.
◆ BMU_STAT_VAL
| #define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */ |
Definition at line 2307 of file if_mskreg.h.
◆ BMU_STF
| #define BMU_STF BIT_30 /* Start of Frame */ |
Definition at line 2297 of file if_mskreg.h.
◆ BMU_STFWD
| #define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */ |
Definition at line 2302 of file if_mskreg.h.
◆ BMU_STOP
| #define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */ |
Definition at line 1107 of file if_mskreg.h.
◆ BMU_SW
| #define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */ |
Definition at line 2304 of file if_mskreg.h.
◆ BMU_TCP_CHECK
| #define BMU_TCP_CHECK (0x56<<16) /* Descr with TCP ext */ |
Definition at line 2311 of file if_mskreg.h.
◆ BMU_TIST_VAL
| #define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */ |
Definition at line 2308 of file if_mskreg.h.
◆ BMU_TX_CLR_IRQ_TCP
| #define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */ |
Definition at line 1126 of file if_mskreg.h.
◆ BMU_TX_IPIDINCR_OFF
| #define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */ |
Definition at line 1125 of file if_mskreg.h.
◆ BMU_TX_IPIDINCR_ON
| #define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */ |
Definition at line 1124 of file if_mskreg.h.
◆ BMU_UDP_CHECK
| #define BMU_UDP_CHECK (0x57<<16) /* Descr with UDP ext (YUKON only) */ |
Definition at line 2312 of file if_mskreg.h.
◆ BSC_SRC
| #define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */ |
Definition at line 1042 of file if_mskreg.h.
◆ BSC_START
| #define BSC_START BIT_1 /* Start Blink Source Counter */ |
Definition at line 1038 of file if_mskreg.h.
◆ BSC_STOP
| #define BSC_STOP BIT_0 /* Stop Blink Source Counter */ |
Definition at line 1039 of file if_mskreg.h.
◆ BSC_T_OFF
| #define BSC_T_OFF BIT_1 /* Test mode off */ |
Definition at line 1046 of file if_mskreg.h.
◆ BSC_T_ON
| #define BSC_T_ON BIT_2 /* Test mode on */ |
Definition at line 1045 of file if_mskreg.h.
◆ BSC_T_STEP
| #define BSC_T_STEP BIT_0 /* Test step */ |
Definition at line 1047 of file if_mskreg.h.
◆ BUF_SEND
| #define BUF_SEND 0x02000000 |
Definition at line 2239 of file if_mskreg.h.
◆ CABD_STAT_FAIL
| #define CABD_STAT_FAIL 3 |
Definition at line 1582 of file if_mskreg.h.
◆ CABD_STAT_NORMAL
| #define CABD_STAT_NORMAL 0 |
Definition at line 1579 of file if_mskreg.h.
◆ CABD_STAT_OPEN
| #define CABD_STAT_OPEN 2 |
Definition at line 1581 of file if_mskreg.h.
◆ CABD_STAT_SHORT
| #define CABD_STAT_SHORT 1 |
Definition at line 1580 of file if_mskreg.h.
◆ CALSUM
| #define CALSUM 0x00020000 |
Definition at line 2230 of file if_mskreg.h.
◆ CFG_CHIP_R_MSK
| #define CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */ |
Definition at line 892 of file if_mskreg.h.
◆ CFG_DIS_M2_CLK
| #define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */ |
Definition at line 893 of file if_mskreg.h.
◆ CFG_DUAL_MAC_MSK
| #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) |
Definition at line 949 of file if_mskreg.h.
◆ CFG_LED_MODE
| #define CFG_LED_MODE | ( | x | ) | (((x) & CFG_LED_MODE_MSK) >> 2) |
Definition at line 948 of file if_mskreg.h.
◆ CFG_LED_MODE_MSK
| #define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */ |
Definition at line 944 of file if_mskreg.h.
◆ CFG_LINK_1_AVAIL
| #define CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */ |
Definition at line 946 of file if_mskreg.h.
◆ CFG_LINK_2_AVAIL
| #define CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */ |
Definition at line 945 of file if_mskreg.h.
◆ CFG_SNG_MAC
| #define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */ |
Definition at line 894 of file if_mskreg.h.
◆ CHIP_ID_GENESIS
| #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ |
Definition at line 897 of file if_mskreg.h.
◆ CHIP_ID_YUKON
| #define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ |
Definition at line 898 of file if_mskreg.h.
◆ CHIP_ID_YUKON_EC
| #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ |
Definition at line 904 of file if_mskreg.h.
◆ CHIP_ID_YUKON_EC_U
| #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */ |
Definition at line 902 of file if_mskreg.h.
◆ CHIP_ID_YUKON_EX
| #define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */ |
Definition at line 903 of file if_mskreg.h.
◆ CHIP_ID_YUKON_FE
| #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ |
Definition at line 905 of file if_mskreg.h.
◆ CHIP_ID_YUKON_FE_P
| #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */ |
Definition at line 906 of file if_mskreg.h.
◆ CHIP_ID_YUKON_LITE
| #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */ |
Definition at line 899 of file if_mskreg.h.
◆ CHIP_ID_YUKON_LP
| #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */ |
Definition at line 900 of file if_mskreg.h.
◆ CHIP_ID_YUKON_OPT
| #define CHIP_ID_YUKON_OPT 0xbc /* Chip ID for YUKON-2 Optima */ |
Definition at line 910 of file if_mskreg.h.
◆ CHIP_ID_YUKON_SUPR
| #define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */ |
Definition at line 907 of file if_mskreg.h.
◆ CHIP_ID_YUKON_UL_2
| #define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */ |
Definition at line 908 of file if_mskreg.h.
◆ CHIP_ID_YUKON_UNKNOWN
| #define CHIP_ID_YUKON_UNKNOWN 0xbb |
Definition at line 909 of file if_mskreg.h.
◆ CHIP_ID_YUKON_XL
| #define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */ |
Definition at line 901 of file if_mskreg.h.
◆ CHIP_REV_YU_EC_A1
| #define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */ |
Definition at line 917 of file if_mskreg.h.
◆ CHIP_REV_YU_EC_A2
| #define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */ |
Definition at line 918 of file if_mskreg.h.
◆ CHIP_REV_YU_EC_A3
| #define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */ |
Definition at line 919 of file if_mskreg.h.
◆ CHIP_REV_YU_EC_U_A0
| #define CHIP_REV_YU_EC_U_A0 1 |
Definition at line 921 of file if_mskreg.h.
◆ CHIP_REV_YU_EC_U_A1
| #define CHIP_REV_YU_EC_U_A1 2 |
Definition at line 922 of file if_mskreg.h.
◆ CHIP_REV_YU_EX_A0
| #define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */ |
Definition at line 926 of file if_mskreg.h.
◆ CHIP_REV_YU_EX_B0
| #define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */ |
Definition at line 927 of file if_mskreg.h.
◆ CHIP_REV_YU_FE_P_A0
| #define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */ |
Definition at line 924 of file if_mskreg.h.
◆ CHIP_REV_YU_SU_A0
| #define CHIP_REV_YU_SU_A0 0 /* Chip Rev. for Yukon-2 SUPR A0 */ |
Definition at line 929 of file if_mskreg.h.
◆ CHIP_REV_YU_SU_B0
| #define CHIP_REV_YU_SU_B0 1 /* Chip Rev. for Yukon-2 SUPR B0 */ |
Definition at line 930 of file if_mskreg.h.
◆ CHIP_REV_YU_SU_B1
| #define CHIP_REV_YU_SU_B1 3 /* Chip Rev. for Yukon-2 SUPR B1 */ |
Definition at line 931 of file if_mskreg.h.
◆ CHIP_REV_YU_XL_A0
| #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ |
Definition at line 912 of file if_mskreg.h.
◆ CHIP_REV_YU_XL_A1
| #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ |
Definition at line 913 of file if_mskreg.h.
◆ CHIP_REV_YU_XL_A2
| #define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */ |
Definition at line 914 of file if_mskreg.h.
◆ CHIP_REV_YU_XL_A3
| #define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */ |
Definition at line 915 of file if_mskreg.h.
◆ CS_CL_SW_IRQ
| #define CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */ |
Definition at line 798 of file if_mskreg.h.
◆ CS_MRST_CLR
| #define CS_MRST_CLR BIT_3 /* Clear Master Reset */ |
Definition at line 801 of file if_mskreg.h.
◆ CS_MRST_SET
| #define CS_MRST_SET BIT_2 /* Set Master Reset */ |
Definition at line 802 of file if_mskreg.h.
◆ CS_RST_CLR
| #define CS_RST_CLR BIT_1 /* Clear Software Reset */ |
Definition at line 803 of file if_mskreg.h.
◆ CS_RST_SET
| #define CS_RST_SET BIT_0 /* Set Software Reset */ |
Definition at line 804 of file if_mskreg.h.
◆ CS_ST_SW_IRQ
| #define CS_ST_SW_IRQ BIT_7 /* Set IRQ SW Request */ |
Definition at line 797 of file if_mskreg.h.
◆ CS_STOP_DONE
| #define CS_STOP_DONE BIT_5 /* Stop Master is finished */ |
Definition at line 799 of file if_mskreg.h.
◆ CS_STOP_MAST
| #define CS_STOP_MAST BIT_4 /* Command Bit to stop the master */ |
Definition at line 800 of file if_mskreg.h.
◆ CSR_PCI_READ_1
| #define CSR_PCI_READ_1 | ( | sc, | |
| reg | |||
| ) | bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg)) |
Definition at line 2150 of file if_mskreg.h.
◆ CSR_PCI_READ_2
| #define CSR_PCI_READ_2 | ( | sc, | |
| reg | |||
| ) | bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg)) |
Definition at line 2148 of file if_mskreg.h.
◆ CSR_PCI_READ_4
| #define CSR_PCI_READ_4 | ( | sc, | |
| reg | |||
| ) | bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg)) |
Definition at line 2146 of file if_mskreg.h.
◆ CSR_PCI_WRITE_1
| #define CSR_PCI_WRITE_1 | ( | sc, | |
| reg, | |||
| val | |||
| ) | bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) |
Definition at line 2143 of file if_mskreg.h.
◆ CSR_PCI_WRITE_2
| #define CSR_PCI_WRITE_2 | ( | sc, | |
| reg, | |||
| val | |||
| ) | bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) |
Definition at line 2141 of file if_mskreg.h.
◆ CSR_PCI_WRITE_4
| #define CSR_PCI_WRITE_4 | ( | sc, | |
| reg, | |||
| val | |||
| ) | bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) |
Definition at line 2139 of file if_mskreg.h.
◆ CSR_READ_1
| #define CSR_READ_1 | ( | sc, | |
| reg | |||
| ) | bus_read_1((sc)->msk_res[0], (reg)) |
Definition at line 2136 of file if_mskreg.h.
◆ CSR_READ_2
| #define CSR_READ_2 | ( | sc, | |
| reg | |||
| ) | bus_read_2((sc)->msk_res[0], (reg)) |
Definition at line 2134 of file if_mskreg.h.
◆ CSR_READ_4
| #define CSR_READ_4 | ( | sc, | |
| reg | |||
| ) | bus_read_4((sc)->msk_res[0], (reg)) |
Definition at line 2132 of file if_mskreg.h.
◆ CSR_WRITE_1
| #define CSR_WRITE_1 | ( | sc, | |
| reg, | |||
| val | |||
| ) | bus_write_1((sc)->msk_res[0], (reg), (val)) |
Definition at line 2129 of file if_mskreg.h.
◆ CSR_WRITE_2
| #define CSR_WRITE_2 | ( | sc, | |
| reg, | |||
| val | |||
| ) | bus_write_2((sc)->msk_res[0], (reg), (val)) |
Definition at line 2127 of file if_mskreg.h.
◆ CSR_WRITE_4
| #define CSR_WRITE_4 | ( | sc, | |
| reg, | |||
| val | |||
| ) | bus_write_4((sc)->msk_res[0], (reg), (val)) |
Definition at line 2125 of file if_mskreg.h.
◆ CSS_IPFRAG
| #define CSS_IPFRAG 0x00100000 |
Definition at line 2287 of file if_mskreg.h.
◆ CSS_IPV4
| #define CSS_IPV4 0x00020000 |
Definition at line 2290 of file if_mskreg.h.
◆ CSS_IPV4_CSUM_OK
| #define CSS_IPV4_CSUM_OK 0x00040000 |
Definition at line 2289 of file if_mskreg.h.
◆ CSS_IPV6
| #define CSS_IPV6 0x00080000 |
Definition at line 2288 of file if_mskreg.h.
◆ CSS_PORT
| #define CSS_PORT 0x00010000 |
Definition at line 2291 of file if_mskreg.h.
◆ CSS_TCP
| #define CSS_TCP 0x00200000 |
Definition at line 2286 of file if_mskreg.h.
◆ CSS_TCPUDP_CSUM_OK
| #define CSS_TCPUDP_CSUM_OK 0x00800000 |
Definition at line 2284 of file if_mskreg.h.
◆ CSS_UDP
| #define CSS_UDP 0x00400000 |
Definition at line 2285 of file if_mskreg.h.
◆ DATA_BLIND_DEF
| #define DATA_BLIND_DEF 0x04 |
Definition at line 1891 of file if_mskreg.h.
◆ DATA_BLIND_VAL
| #define DATA_BLIND_VAL | ( | x | ) | (SHIFT11(x) & GM_SMOD_DATABL_MSK) |
Definition at line 1888 of file if_mskreg.h.
◆ DEVICEID_DLINK_DGE550SX
| #define DEVICEID_DLINK_DGE550SX 0x4001 |
Definition at line 157 of file if_mskreg.h.
◆ DEVICEID_DLINK_DGE560SX
| #define DEVICEID_DLINK_DGE560SX 0x4002 |
Definition at line 158 of file if_mskreg.h.
◆ DEVICEID_DLINK_DGE560T
| #define DEVICEID_DLINK_DGE560T 0x4b00 |
Definition at line 159 of file if_mskreg.h.
◆ DEVICEID_MRVL_4360
| #define DEVICEID_MRVL_4360 0x4360 |
Definition at line 140 of file if_mskreg.h.
◆ DEVICEID_MRVL_4361
| #define DEVICEID_MRVL_4361 0x4361 |
Definition at line 141 of file if_mskreg.h.
◆ DEVICEID_MRVL_4362
| #define DEVICEID_MRVL_4362 0x4362 |
Definition at line 142 of file if_mskreg.h.
◆ DEVICEID_MRVL_4363
| #define DEVICEID_MRVL_4363 0x4363 |
Definition at line 143 of file if_mskreg.h.
◆ DEVICEID_MRVL_4364
| #define DEVICEID_MRVL_4364 0x4364 |
Definition at line 144 of file if_mskreg.h.
◆ DEVICEID_MRVL_4365
| #define DEVICEID_MRVL_4365 0x4365 |
Definition at line 145 of file if_mskreg.h.
◆ DEVICEID_MRVL_436A
| #define DEVICEID_MRVL_436A 0x436A |
Definition at line 146 of file if_mskreg.h.
◆ DEVICEID_MRVL_436B
| #define DEVICEID_MRVL_436B 0x436B |
Definition at line 147 of file if_mskreg.h.
◆ DEVICEID_MRVL_436C
| #define DEVICEID_MRVL_436C 0x436C |
Definition at line 148 of file if_mskreg.h.
◆ DEVICEID_MRVL_436D
| #define DEVICEID_MRVL_436D 0x436D |
Definition at line 149 of file if_mskreg.h.
◆ DEVICEID_MRVL_4370
| #define DEVICEID_MRVL_4370 0x4370 |
Definition at line 150 of file if_mskreg.h.
◆ DEVICEID_MRVL_4380
| #define DEVICEID_MRVL_4380 0x4380 |
Definition at line 151 of file if_mskreg.h.
◆ DEVICEID_MRVL_4381
| #define DEVICEID_MRVL_4381 0x4381 |
Definition at line 152 of file if_mskreg.h.
◆ DEVICEID_MRVL_8021CU
| #define DEVICEID_MRVL_8021CU 0x4340 |
Definition at line 124 of file if_mskreg.h.
◆ DEVICEID_MRVL_8021X
| #define DEVICEID_MRVL_8021X 0x4344 |
Definition at line 128 of file if_mskreg.h.
◆ DEVICEID_MRVL_8022CU
| #define DEVICEID_MRVL_8022CU 0x4341 |
Definition at line 125 of file if_mskreg.h.
◆ DEVICEID_MRVL_8022X
| #define DEVICEID_MRVL_8022X 0x4345 |
Definition at line 129 of file if_mskreg.h.
◆ DEVICEID_MRVL_8035
| #define DEVICEID_MRVL_8035 0x4350 |
Definition at line 132 of file if_mskreg.h.
◆ DEVICEID_MRVL_8036
| #define DEVICEID_MRVL_8036 0x4351 |
Definition at line 133 of file if_mskreg.h.
◆ DEVICEID_MRVL_8038
| #define DEVICEID_MRVL_8038 0x4352 |
Definition at line 134 of file if_mskreg.h.
◆ DEVICEID_MRVL_8039
| #define DEVICEID_MRVL_8039 0x4353 |
Definition at line 135 of file if_mskreg.h.
◆ DEVICEID_MRVL_8040
| #define DEVICEID_MRVL_8040 0x4354 |
Definition at line 136 of file if_mskreg.h.
◆ DEVICEID_MRVL_8040T
| #define DEVICEID_MRVL_8040T 0x4355 |
Definition at line 137 of file if_mskreg.h.
◆ DEVICEID_MRVL_8042
| #define DEVICEID_MRVL_8042 0x4357 |
Definition at line 138 of file if_mskreg.h.
◆ DEVICEID_MRVL_8048
| #define DEVICEID_MRVL_8048 0x435A |
Definition at line 139 of file if_mskreg.h.
◆ DEVICEID_MRVL_8061CU
| #define DEVICEID_MRVL_8061CU 0x4342 |
Definition at line 126 of file if_mskreg.h.
◆ DEVICEID_MRVL_8061X
| #define DEVICEID_MRVL_8061X 0x4346 |
Definition at line 130 of file if_mskreg.h.
◆ DEVICEID_MRVL_8062CU
| #define DEVICEID_MRVL_8062CU 0x4343 |
Definition at line 127 of file if_mskreg.h.
◆ DEVICEID_MRVL_8062X
| #define DEVICEID_MRVL_8062X 0x4347 |
Definition at line 131 of file if_mskreg.h.
◆ DEVICEID_SK_YUKON2
| #define DEVICEID_SK_YUKON2 0x9000 |
Definition at line 118 of file if_mskreg.h.
◆ DEVICEID_SK_YUKON2_EXPR
| #define DEVICEID_SK_YUKON2_EXPR 0x9e00 |
Definition at line 119 of file if_mskreg.h.
◆ DPT_MSK
| #define DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */ |
Definition at line 981 of file if_mskreg.h.
◆ DPT_START
| #define DPT_START BIT_1 /* Start Descriptor Poll Timer */ |
Definition at line 984 of file if_mskreg.h.
◆ DPT_STOP
| #define DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */ |
Definition at line 985 of file if_mskreg.h.
◆ EOP
| #define EOP 0x00800000 |
Definition at line 2236 of file if_mskreg.h.
◆ F_ALM_FULL
| #define F_ALM_FULL BIT_28 /* Rx FIFO: almost full */ |
Definition at line 1132 of file if_mskreg.h.
◆ F_EMPTY
| #define F_EMPTY BIT_27 /* Tx FIFO: empty flag */ |
Definition at line 1133 of file if_mskreg.h.
◆ F_FIFO_EOF
| #define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */ |
Definition at line 1134 of file if_mskreg.h.
◆ F_FIFO_LEVEL
| #define F_FIFO_LEVEL (0x1f<<16) |
Definition at line 1137 of file if_mskreg.h.
◆ F_M_RX_RAM_DIS
| #define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */ |
Definition at line 1136 of file if_mskreg.h.
◆ F_TX_CHK_AUTO_OFF
| #define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/ |
Definition at line 1130 of file if_mskreg.h.
◆ F_TX_CHK_AUTO_ON
| #define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/ |
Definition at line 1131 of file if_mskreg.h.
◆ F_WATER_MARK
| #define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */ |
Definition at line 1139 of file if_mskreg.h.
◆ F_WM_REACHED
| #define F_WM_REACHED BIT_25 /* Watermark reached */ |
Definition at line 1135 of file if_mskreg.h.
◆ FRC_STAT
| #define FRC_STAT 0x00400000 |
Definition at line 2235 of file if_mskreg.h.
◆ GLB_GPIO_CLK_DBG_MSK
| #define GLB_GPIO_CLK_DBG_MSK 0x3c000000 /* Clock Debug */ |
Definition at line 999 of file if_mskreg.h.
◆ GLB_GPIO_CLK_DEB_ENA
| #define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */ |
Definition at line 998 of file if_mskreg.h.
◆ GLB_GPIO_INT_RST_D3_DIS
| #define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */ |
Definition at line 1001 of file if_mskreg.h.
◆ GLB_GPIO_LED_PAD_SPEED_UP
| #define GLB_GPIO_LED_PAD_SPEED_UP BIT_14 /* LED PAD Speed Up */ |
Definition at line 1002 of file if_mskreg.h.
◆ GLB_GPIO_RAND_BIT_1
| #define GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */ |
Definition at line 1007 of file if_mskreg.h.
◆ GLB_GPIO_RAND_ENA
| #define GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */ |
Definition at line 1006 of file if_mskreg.h.
◆ GLB_GPIO_STAT_RACE_DIS
| #define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */ |
Definition at line 1003 of file if_mskreg.h.
◆ GLB_GPIO_TEST_SEL_BASE
| #define GLB_GPIO_TEST_SEL_BASE BIT_11 |
Definition at line 1005 of file if_mskreg.h.
◆ GLB_GPIO_TEST_SEL_MSK
| #define GLB_GPIO_TEST_SEL_MSK 0x00001800 /* Testmode Select */ |
Definition at line 1004 of file if_mskreg.h.
◆ GM_GP_CTRL
| #define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ |
Definition at line 1667 of file if_mskreg.h.
◆ GM_GP_STAT
| #define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */ |
Definition at line 1666 of file if_mskreg.h.
◆ GM_GPCR_AU_ALL_DIS
| #define GM_GPCR_AU_ALL_DIS |
Definition at line 1843 of file if_mskreg.h.
◆ GM_GPCR_AU_DUP_DIS
| #define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */ |
Definition at line 1838 of file if_mskreg.h.
◆ GM_GPCR_AU_FCT_DIS
| #define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */ |
Definition at line 1839 of file if_mskreg.h.
◆ GM_GPCR_AU_SPD_DIS
| #define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */ |
Definition at line 1840 of file if_mskreg.h.
◆ GM_GPCR_DUP_FULL
| #define GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */ |
Definition at line 1835 of file if_mskreg.h.
◆ GM_GPCR_FC_RX_DIS
| #define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */ |
Definition at line 1836 of file if_mskreg.h.
◆ GM_GPCR_FC_TX_DIS
| #define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */ |
Definition at line 1828 of file if_mskreg.h.
◆ GM_GPCR_FL_PASS
| #define GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */ |
Definition at line 1834 of file if_mskreg.h.
◆ GM_GPCR_GIGS_ENA
| #define GM_GPCR_GIGS_ENA BIT_7 /* Gigabit Speed (1000 Mbps) */ |
Definition at line 1833 of file if_mskreg.h.
◆ GM_GPCR_LOOP_ENA
| #define GM_GPCR_LOOP_ENA BIT_9 /* Enable MAC Loopback Mode */ |
Definition at line 1831 of file if_mskreg.h.
◆ GM_GPCR_PART_ENA
| #define GM_GPCR_PART_ENA BIT_8 /* Enable Partition Mode */ |
Definition at line 1832 of file if_mskreg.h.
◆ GM_GPCR_RMII_LB_ENA
| #define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */ |
Definition at line 1827 of file if_mskreg.h.
◆ GM_GPCR_RMII_PH_ENA
| #define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */ |
Definition at line 1826 of file if_mskreg.h.
◆ GM_GPCR_RX_ENA
| #define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */ |
Definition at line 1830 of file if_mskreg.h.
◆ GM_GPCR_SPEED_100
| #define GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */ |
Definition at line 1837 of file if_mskreg.h.
◆ GM_GPCR_SPEED_1000
| #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) |
Definition at line 1842 of file if_mskreg.h.
◆ GM_GPCR_TX_ENA
| #define GM_GPCR_TX_ENA BIT_12 /* Enable Transmit */ |
Definition at line 1829 of file if_mskreg.h.
◆ GM_GPSR_DUPLEX
| #define GM_GPSR_DUPLEX BIT_14 /* Duplex Mode (1 = Full) */ |
Definition at line 1813 of file if_mskreg.h.
◆ GM_GPSR_EXC_COL
| #define GM_GPSR_EXC_COL BIT_9 /* Excessive Collisions Occurred */ |
Definition at line 1818 of file if_mskreg.h.
◆ GM_GPSR_FC_RX_DIS
| #define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */ |
Definition at line 1823 of file if_mskreg.h.
◆ GM_GPSR_FC_TX_DIS
| #define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */ |
Definition at line 1814 of file if_mskreg.h.
◆ GM_GPSR_GIG_SPEED
| #define GM_GPSR_GIG_SPEED BIT_4 /* Gigabit Speed (1 = 1000 Mbps) */ |
Definition at line 1821 of file if_mskreg.h.
◆ GM_GPSR_LAT_COL
| #define GM_GPSR_LAT_COL BIT_8 /* Late Collisions Occurred */ |
Definition at line 1819 of file if_mskreg.h.
◆ GM_GPSR_LINK_UP
| #define GM_GPSR_LINK_UP BIT_12 /* Link Up Status */ |
Definition at line 1815 of file if_mskreg.h.
◆ GM_GPSR_PART_MODE
| #define GM_GPSR_PART_MODE BIT_3 /* Partition mode */ |
Definition at line 1822 of file if_mskreg.h.
◆ GM_GPSR_PAUSE
| #define GM_GPSR_PAUSE BIT_11 /* Pause State */ |
Definition at line 1816 of file if_mskreg.h.
◆ GM_GPSR_PHY_ST_CH
| #define GM_GPSR_PHY_ST_CH BIT_5 /* PHY Status Change */ |
Definition at line 1820 of file if_mskreg.h.
◆ GM_GPSR_SPEED
| #define GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */ |
Definition at line 1812 of file if_mskreg.h.
◆ GM_GPSR_TX_ACTIVE
| #define GM_GPSR_TX_ACTIVE BIT_10 /* Tx in Progress */ |
Definition at line 1817 of file if_mskreg.h.
◆ GM_IS_RX_CO_OV
| #define GM_IS_RX_CO_OV BIT_5 /* Receive Counter Overflow IRQ */ |
Definition at line 2108 of file if_mskreg.h.
◆ GM_IS_RX_COMPL
| #define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ |
Definition at line 2113 of file if_mskreg.h.
◆ GM_IS_RX_FF_OR
| #define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ |
Definition at line 2112 of file if_mskreg.h.
◆ GM_IS_TX_CO_OV
| #define GM_IS_TX_CO_OV BIT_4 /* Transmit Counter Overflow IRQ */ |
Definition at line 2109 of file if_mskreg.h.
◆ GM_IS_TX_COMPL
| #define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ |
Definition at line 2111 of file if_mskreg.h.
◆ GM_IS_TX_FF_UR
| #define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ |
Definition at line 2110 of file if_mskreg.h.
◆ GM_MC_ADDR_H1
| #define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */ |
Definition at line 1683 of file if_mskreg.h.
◆ GM_MC_ADDR_H2
| #define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */ |
Definition at line 1684 of file if_mskreg.h.
◆ GM_MC_ADDR_H3
| #define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */ |
Definition at line 1685 of file if_mskreg.h.
◆ GM_MC_ADDR_H4
| #define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */ |
Definition at line 1686 of file if_mskreg.h.
◆ GM_MIB_CNT_BASE
| #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ |
Definition at line 1704 of file if_mskreg.h.
◆ GM_MIB_CNT_SIZE
| #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ |
Definition at line 1705 of file if_mskreg.h.
◆ GM_PAR_MIB_CLR
| #define GM_PAR_MIB_CLR BIT_5 /* Set MIB Clear Counter Mode */ |
Definition at line 1905 of file if_mskreg.h.
◆ GM_PAR_MIB_TST
| #define GM_PAR_MIB_TST BIT_4 /* MIB Load Counter (Test Mode) */ |
Definition at line 1906 of file if_mskreg.h.
◆ GM_PHY_ADDR
| #define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */ |
Definition at line 1701 of file if_mskreg.h.
◆ GM_RX_CTRL
| #define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ |
Definition at line 1669 of file if_mskreg.h.
◆ GM_RX_IRQ_MSK
| #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */ |
Definition at line 1695 of file if_mskreg.h.
◆ GM_RX_IRQ_SRC
| #define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */ |
Definition at line 1690 of file if_mskreg.h.
◆ GM_RXCR_CRC_DIS
| #define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */ |
Definition at line 1860 of file if_mskreg.h.
◆ GM_RXCR_MCF_ENA
| #define GM_RXCR_MCF_ENA BIT_14 /* Enable Multicast filtering */ |
Definition at line 1859 of file if_mskreg.h.
◆ GM_RXCR_PASS_FC
| #define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */ |
Definition at line 1861 of file if_mskreg.h.
◆ GM_RXCR_UCF_ENA
| #define GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */ |
Definition at line 1858 of file if_mskreg.h.
◆ GM_RXE_FIFO_OV
| #define GM_RXE_FIFO_OV (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */ |
Definition at line 1755 of file if_mskreg.h.
◆ GM_RXE_FRAG
| #define GM_RXE_FRAG (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */ |
Definition at line 1733 of file if_mskreg.h.
◆ GM_RXF_1023B
| #define GM_RXF_1023B (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */ |
Definition at line 1743 of file if_mskreg.h.
◆ GM_RXF_127B
| #define GM_RXF_127B (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */ |
Definition at line 1737 of file if_mskreg.h.
◆ GM_RXF_1518B
| #define GM_RXF_1518B (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */ |
Definition at line 1745 of file if_mskreg.h.
◆ GM_RXF_255B
| #define GM_RXF_255B (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */ |
Definition at line 1739 of file if_mskreg.h.
◆ GM_RXF_511B
| #define GM_RXF_511B (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */ |
Definition at line 1741 of file if_mskreg.h.
◆ GM_RXF_64B
| #define GM_RXF_64B (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ |
Definition at line 1735 of file if_mskreg.h.
◆ GM_RXF_BC_OK
| #define GM_RXF_BC_OK (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */ |
Definition at line 1713 of file if_mskreg.h.
◆ GM_RXF_FCS_ERR
| #define GM_RXF_FCS_ERR (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */ |
Definition at line 1719 of file if_mskreg.h.
◆ GM_RXF_JAB_PKT
| #define GM_RXF_JAB_PKT (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */ |
Definition at line 1751 of file if_mskreg.h.
◆ GM_RXF_LNG_ERR
| #define GM_RXF_LNG_ERR (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */ |
Definition at line 1749 of file if_mskreg.h.
◆ GM_RXF_MAX_SZ
| #define GM_RXF_MAX_SZ (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */ |
Definition at line 1747 of file if_mskreg.h.
◆ GM_RXF_MC_OK
| #define GM_RXF_MC_OK (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */ |
Definition at line 1717 of file if_mskreg.h.
◆ GM_RXF_MPAUSE
| #define GM_RXF_MPAUSE (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */ |
Definition at line 1715 of file if_mskreg.h.
◆ GM_RXF_SHT
| #define GM_RXF_SHT (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ |
Definition at line 1731 of file if_mskreg.h.
◆ GM_RXF_SPARE1
| #define GM_RXF_SPARE1 (GM_MIB_CNT_BASE + 40) /* Rx spare 1 */ |
Definition at line 1721 of file if_mskreg.h.
◆ GM_RXF_SPARE2
| #define GM_RXF_SPARE2 (GM_MIB_CNT_BASE + 168) /* Rx spare 2 */ |
Definition at line 1753 of file if_mskreg.h.
◆ GM_RXF_SPARE3
| #define GM_RXF_SPARE3 (GM_MIB_CNT_BASE + 184) /* Rx spare 3 */ |
Definition at line 1757 of file if_mskreg.h.
◆ GM_RXF_UC_OK
| #define GM_RXF_UC_OK (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */ |
Definition at line 1711 of file if_mskreg.h.
◆ GM_RXO_ERR_HI
| #define GM_RXO_ERR_HI (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */ |
Definition at line 1729 of file if_mskreg.h.
◆ GM_RXO_ERR_LO
| #define GM_RXO_ERR_LO (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */ |
Definition at line 1727 of file if_mskreg.h.
◆ GM_RXO_OK_HI
| #define GM_RXO_OK_HI (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */ |
Definition at line 1725 of file if_mskreg.h.
◆ GM_RXO_OK_LO
| #define GM_RXO_OK_LO (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */ |
Definition at line 1723 of file if_mskreg.h.
◆ GM_SERIAL_MODE
| #define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ |
Definition at line 1672 of file if_mskreg.h.
◆ GM_SMI_CT_BUSY
| #define GM_SMI_CT_BUSY BIT_3 /* Busy (Operation in progress) */ |
Definition at line 1899 of file if_mskreg.h.
◆ GM_SMI_CT_OP_RD
| #define GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/ |
Definition at line 1897 of file if_mskreg.h.
◆ GM_SMI_CT_PHY_A_MSK
| #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */ |
Definition at line 1895 of file if_mskreg.h.
◆ GM_SMI_CT_PHY_AD
| #define GM_SMI_CT_PHY_AD | ( | x | ) | (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK) |
Definition at line 1901 of file if_mskreg.h.
◆ GM_SMI_CT_RD_VAL
| #define GM_SMI_CT_RD_VAL BIT_4 /* Read Valid (Read completed) */ |
Definition at line 1898 of file if_mskreg.h.
◆ GM_SMI_CT_REG_A_MSK
| #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */ |
Definition at line 1896 of file if_mskreg.h.
◆ GM_SMI_CT_REG_AD
| #define GM_SMI_CT_REG_AD | ( | x | ) | (SHIFT6(x) & GM_SMI_CT_REG_A_MSK) |
Definition at line 1902 of file if_mskreg.h.
◆ GM_SMI_CTRL
| #define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */ |
Definition at line 1699 of file if_mskreg.h.
◆ GM_SMI_DATA
| #define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */ |
Definition at line 1700 of file if_mskreg.h.
◆ GM_SMOD_DATABL_MSK
| #define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ |
Definition at line 1881 of file if_mskreg.h.
◆ GM_SMOD_IPG_MSK
| #define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */ |
Definition at line 1886 of file if_mskreg.h.
◆ GM_SMOD_JUMBO_ENA
| #define GM_SMOD_JUMBO_ENA BIT_8 /* Enable Jumbo (Max. Frame Len) */ |
Definition at line 1885 of file if_mskreg.h.
◆ GM_SMOD_LIMIT_4
| #define GM_SMOD_LIMIT_4 BIT_10 /* 4 consecutive Tx trials */ |
Definition at line 1883 of file if_mskreg.h.
◆ GM_SMOD_VLAN_ENA
| #define GM_SMOD_VLAN_ENA BIT_9 /* Enable VLAN (Max. Frame Len) */ |
Definition at line 1884 of file if_mskreg.h.
◆ GM_SRC_ADDR_1H
| #define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */ |
Definition at line 1677 of file if_mskreg.h.
◆ GM_SRC_ADDR_1L
| #define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */ |
Definition at line 1675 of file if_mskreg.h.
◆ GM_SRC_ADDR_1M
| #define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */ |
Definition at line 1676 of file if_mskreg.h.
◆ GM_SRC_ADDR_2H
| #define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */ |
Definition at line 1680 of file if_mskreg.h.
◆ GM_SRC_ADDR_2L
| #define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */ |
Definition at line 1678 of file if_mskreg.h.
◆ GM_SRC_ADDR_2M
| #define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */ |
Definition at line 1679 of file if_mskreg.h.
◆ GM_TR_IRQ_MSK
| #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */ |
Definition at line 1696 of file if_mskreg.h.
◆ GM_TR_IRQ_SRC
| #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */ |
Definition at line 1691 of file if_mskreg.h.
◆ GM_TX_CTRL
| #define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ |
Definition at line 1668 of file if_mskreg.h.
◆ GM_TX_FLOW_CTRL
| #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */ |
Definition at line 1670 of file if_mskreg.h.
◆ GM_TX_IRQ_MSK
| #define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */ |
Definition at line 1694 of file if_mskreg.h.
◆ GM_TX_IRQ_SRC
| #define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */ |
Definition at line 1689 of file if_mskreg.h.
◆ GM_TX_PARAM
| #define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ |
Definition at line 1671 of file if_mskreg.h.
◆ GM_TXCR_COL_THR_MSK
| #define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */ |
Definition at line 1850 of file if_mskreg.h.
◆ GM_TXCR_CRC_DIS
| #define GM_TXCR_CRC_DIS BIT_14 /* Disable insertion of CRC */ |
Definition at line 1848 of file if_mskreg.h.
◆ GM_TXCR_FORCE_JAM
| #define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */ |
Definition at line 1847 of file if_mskreg.h.
◆ GM_TXCR_PAD_DIS
| #define GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */ |
Definition at line 1849 of file if_mskreg.h.
◆ GM_TXCR_PAD_PAT_MSK
| #define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */ |
Definition at line 1851 of file if_mskreg.h.
◆ GM_TXE_FIFO_UR
| #define GM_TXE_FIFO_UR (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */ |
Definition at line 1797 of file if_mskreg.h.
◆ GM_TXF_1023B
| #define GM_TXF_1023B (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */ |
Definition at line 1779 of file if_mskreg.h.
◆ GM_TXF_127B
| #define GM_TXF_127B (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */ |
Definition at line 1773 of file if_mskreg.h.
◆ GM_TXF_1518B
| #define GM_TXF_1518B (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */ |
Definition at line 1781 of file if_mskreg.h.
◆ GM_TXF_255B
| #define GM_TXF_255B (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */ |
Definition at line 1775 of file if_mskreg.h.
◆ GM_TXF_511B
| #define GM_TXF_511B (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */ |
Definition at line 1777 of file if_mskreg.h.
◆ GM_TXF_64B
| #define GM_TXF_64B (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */ |
Definition at line 1771 of file if_mskreg.h.
◆ GM_TXF_ABO_COL
| #define GM_TXF_ABO_COL (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */ |
Definition at line 1791 of file if_mskreg.h.
◆ GM_TXF_BC_OK
| #define GM_TXF_BC_OK (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */ |
Definition at line 1761 of file if_mskreg.h.
◆ GM_TXF_COL
| #define GM_TXF_COL (GM_MIB_CNT_BASE + 304) /* Tx Collision */ |
Definition at line 1787 of file if_mskreg.h.
◆ GM_TXF_LAT_COL
| #define GM_TXF_LAT_COL (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */ |
Definition at line 1789 of file if_mskreg.h.
◆ GM_TXF_MAX_SZ
| #define GM_TXF_MAX_SZ (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */ |
Definition at line 1783 of file if_mskreg.h.
◆ GM_TXF_MC_OK
| #define GM_TXF_MC_OK (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */ |
Definition at line 1765 of file if_mskreg.h.
◆ GM_TXF_MPAUSE
| #define GM_TXF_MPAUSE (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */ |
Definition at line 1763 of file if_mskreg.h.
◆ GM_TXF_MUL_COL
| #define GM_TXF_MUL_COL (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */ |
Definition at line 1793 of file if_mskreg.h.
◆ GM_TXF_SNG_COL
| #define GM_TXF_SNG_COL (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */ |
Definition at line 1795 of file if_mskreg.h.
◆ GM_TXF_SPARE1
| #define GM_TXF_SPARE1 (GM_MIB_CNT_BASE + 296) /* Tx spare 1 */ |
Definition at line 1785 of file if_mskreg.h.
◆ GM_TXF_UC_OK
| #define GM_TXF_UC_OK (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */ |
Definition at line 1759 of file if_mskreg.h.
◆ GM_TXO_OK_HI
| #define GM_TXO_OK_HI (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */ |
Definition at line 1769 of file if_mskreg.h.
◆ GM_TXO_OK_LO
| #define GM_TXO_OK_LO (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */ |
Definition at line 1767 of file if_mskreg.h.
◆ GM_TXPA_BO_LIM_MSK
| #define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */ |
Definition at line 1867 of file if_mskreg.h.
◆ GM_TXPA_JAMDAT_MSK
| #define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */ |
Definition at line 1866 of file if_mskreg.h.
◆ GM_TXPA_JAMIPG_MSK
| #define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */ |
Definition at line 1865 of file if_mskreg.h.
◆ GM_TXPA_JAMLEN_MSK
| #define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */ |
Definition at line 1864 of file if_mskreg.h.
◆ GMAC_CTRL
| #define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */ |
Definition at line 743 of file if_mskreg.h.
◆ GMAC_DEF_MSK
| #define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR) |
Definition at line 2115 of file if_mskreg.h.
◆ GMAC_IRQ_MSK
| #define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */ |
Definition at line 746 of file if_mskreg.h.
◆ GMAC_IRQ_SRC
| #define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */ |
Definition at line 745 of file if_mskreg.h.
◆ GMAC_LINK_CTRL
| #define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */ |
Definition at line 747 of file if_mskreg.h.
◆ GMAC_READ_2
| #define GMAC_READ_2 | ( | sc, | |
| port, | |||
| reg | |||
| ) | CSR_READ_2((sc), GMAC_REG((port), (reg))) |
Definition at line 2171 of file if_mskreg.h.
◆ GMAC_REG
| #define GMAC_REG | ( | port, | |
| reg | |||
| ) | ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg)) |
Definition at line 2167 of file if_mskreg.h.
◆ GMAC_TI_ST_CTRL
| #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ |
Definition at line 677 of file if_mskreg.h.
◆ GMAC_TI_ST_TST
| #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ |
Definition at line 678 of file if_mskreg.h.
◆ GMAC_TI_ST_VAL
| #define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */ |
Definition at line 676 of file if_mskreg.h.
◆ GMAC_WRITE_2
| #define GMAC_WRITE_2 | ( | sc, | |
| port, | |||
| reg, | |||
| val | |||
| ) | CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val)) |
Definition at line 2169 of file if_mskreg.h.
◆ GMC_BYP_MACSECRX_OFF
| #define GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */ |
Definition at line 2067 of file if_mskreg.h.
◆ GMC_BYP_MACSECRX_ON
| #define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */ |
Definition at line 2066 of file if_mskreg.h.
◆ GMC_BYP_MACSECTX_OFF
| #define GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */ |
Definition at line 2069 of file if_mskreg.h.
◆ GMC_BYP_MACSECTX_ON
| #define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */ |
Definition at line 2068 of file if_mskreg.h.
◆ GMC_BYP_RETR_OFF
| #define GMC_BYP_RETR_OFF BIT_8 /* Bypass MAC retransmit FIFO Off */ |
Definition at line 2071 of file if_mskreg.h.
◆ GMC_BYP_RETR_ON
| #define GMC_BYP_RETR_ON BIT_9 /* Bypass MAC retransmit FIFO On */ |
Definition at line 2070 of file if_mskreg.h.
◆ GMC_F_LOOPB_OFF
| #define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ |
Definition at line 2075 of file if_mskreg.h.
◆ GMC_F_LOOPB_ON
| #define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ |
Definition at line 2074 of file if_mskreg.h.
◆ GMC_H_BURST_OFF
| #define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ |
Definition at line 2073 of file if_mskreg.h.
◆ GMC_H_BURST_ON
| #define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ |
Definition at line 2072 of file if_mskreg.h.
◆ GMC_PAUSE_OFF
| #define GMC_PAUSE_OFF BIT_2 /* Pause Off */ |
Definition at line 2077 of file if_mskreg.h.
◆ GMC_PAUSE_ON
| #define GMC_PAUSE_ON BIT_3 /* Pause On */ |
Definition at line 2076 of file if_mskreg.h.
◆ GMC_RST_CLR
| #define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ |
Definition at line 2078 of file if_mskreg.h.
◆ GMC_RST_SET
| #define GMC_RST_SET BIT_0 /* Set GMAC Reset */ |
Definition at line 2079 of file if_mskreg.h.
◆ GMC_SEC_RST
| #define GMC_SEC_RST BIT_15 /* MAC SEC RST */ |
Definition at line 2064 of file if_mskreg.h.
◆ GMC_SEC_RST_OFF
| #define GMC_SEC_RST_OFF BIT_14 /* MAC SEC RST Off */ |
Definition at line 2065 of file if_mskreg.h.
◆ GMF_ASF_RX_OVER_OFF
| #define GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */ |
Definition at line 1967 of file if_mskreg.h.
◆ GMF_ASF_RX_OVER_ON
| #define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */ |
Definition at line 1966 of file if_mskreg.h.
◆ GMF_CLI_RX_FC
| #define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ |
Definition at line 1977 of file if_mskreg.h.
◆ GMF_CLI_RX_FO
| #define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ |
Definition at line 1976 of file if_mskreg.h.
◆ GMF_CLI_TX_FC
| #define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ |
Definition at line 1995 of file if_mskreg.h.
◆ GMF_CLI_TX_FU
| #define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ |
Definition at line 1994 of file if_mskreg.h.
◆ GMF_CLI_TX_PE
| #define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ |
Definition at line 1996 of file if_mskreg.h.
◆ GMF_OPER_OFF
| #define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ |
Definition at line 1979 of file if_mskreg.h.
◆ GMF_OPER_ON
| #define GMF_OPER_ON BIT_3 /* Operational Mode On */ |
Definition at line 1978 of file if_mskreg.h.
◆ GMF_RP_STEP
| #define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ |
Definition at line 1973 of file if_mskreg.h.
◆ GMF_RP_TST_OFF
| #define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ |
Definition at line 1972 of file if_mskreg.h.
◆ GMF_RP_TST_ON
| #define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ |
Definition at line 1971 of file if_mskreg.h.
◆ GMF_RST_CLR
| #define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ |
Definition at line 1980 of file if_mskreg.h.
◆ GMF_RST_SET
| #define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ |
Definition at line 1981 of file if_mskreg.h.
◆ GMF_RX_CTRL_DEF
| #define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) |
Definition at line 1999 of file if_mskreg.h.
◆ GMF_RX_F_FL_OFF
| #define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ |
Definition at line 1975 of file if_mskreg.h.
◆ GMF_RX_F_FL_ON
| #define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ |
Definition at line 1974 of file if_mskreg.h.
◆ GMF_RX_MACSEC_FLUSH_OFF
| #define GMF_RX_MACSEC_FLUSH_OFF BIT_22 |
Definition at line 1963 of file if_mskreg.h.
◆ GMF_RX_MACSEC_FLUSH_ON
| #define GMF_RX_MACSEC_FLUSH_ON BIT_23 |
Definition at line 1962 of file if_mskreg.h.
◆ GMF_RX_OVER_OFF
| #define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */ |
Definition at line 1965 of file if_mskreg.h.
◆ GMF_RX_OVER_ON
| #define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */ |
Definition at line 1964 of file if_mskreg.h.
◆ GMF_TX_CTRL_DEF
| #define GMF_TX_CTRL_DEF GMF_OPER_ON |
Definition at line 2000 of file if_mskreg.h.
◆ GMF_WP_STEP
| #define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ |
Definition at line 1970 of file if_mskreg.h.
◆ GMF_WP_TST_OFF
| #define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ |
Definition at line 1969 of file if_mskreg.h.
◆ GMF_WP_TST_ON
| #define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ |
Definition at line 1968 of file if_mskreg.h.
◆ GMF_WSP_STEP
| #define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ |
Definition at line 1992 of file if_mskreg.h.
◆ GMF_WSP_TST_OFF
| #define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ |
Definition at line 1991 of file if_mskreg.h.
◆ GMF_WSP_TST_ON
| #define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ |
Definition at line 1990 of file if_mskreg.h.
◆ GMLC_RST_CLR
| #define GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */ |
Definition at line 2118 of file if_mskreg.h.
◆ GMLC_RST_SET
| #define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */ |
Definition at line 2119 of file if_mskreg.h.
◆ GMR_FS_ANY_ERR
| #define GMR_FS_ANY_ERR |
Definition at line 1926 of file if_mskreg.h.
◆ GMR_FS_BAD_FC
| #define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */ |
Definition at line 1917 of file if_mskreg.h.
◆ GMR_FS_BC
| #define GMR_FS_BC BIT_9 /* Broadcast Packet */ |
Definition at line 1914 of file if_mskreg.h.
◆ GMR_FS_CRC_ERR
| #define GMR_FS_CRC_ERR BIT_1 /* CRC Error */ |
Definition at line 1921 of file if_mskreg.h.
◆ GMR_FS_FRAGMENT
| #define GMR_FS_FRAGMENT BIT_3 /* Fragment */ |
Definition at line 1920 of file if_mskreg.h.
◆ GMR_FS_GOOD_FC
| #define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */ |
Definition at line 1916 of file if_mskreg.h.
◆ GMR_FS_JABBER
| #define GMR_FS_JABBER BIT_12 /* Jabber Packet */ |
Definition at line 1911 of file if_mskreg.h.
◆ GMR_FS_LEN_MSK
| #define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */ |
Definition at line 1909 of file if_mskreg.h.
◆ GMR_FS_LEN_SHIFT
| #define GMR_FS_LEN_SHIFT 16 |
Definition at line 1924 of file if_mskreg.h.
◆ GMR_FS_LONG_ERR
| #define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */ |
Definition at line 1919 of file if_mskreg.h.
◆ GMR_FS_MC
| #define GMR_FS_MC BIT_10 /* Multicast Packet */ |
Definition at line 1913 of file if_mskreg.h.
◆ GMR_FS_MII_ERR
| #define GMR_FS_MII_ERR BIT_5 /* MII Error */ |
Definition at line 1918 of file if_mskreg.h.
◆ GMR_FS_RX_FF_OV
| #define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */ |
Definition at line 1922 of file if_mskreg.h.
◆ GMR_FS_RX_OK
| #define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */ |
Definition at line 1915 of file if_mskreg.h.
◆ GMR_FS_UN_SIZE
| #define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */ |
Definition at line 1912 of file if_mskreg.h.
◆ GMR_FS_VLAN
| #define GMR_FS_VLAN BIT_13 /* VLAN Packet */ |
Definition at line 1910 of file if_mskreg.h.
◆ GMT_ST_CLR_IRQ
| #define GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */ |
Definition at line 2008 of file if_mskreg.h.
◆ GMT_ST_START
| #define GMT_ST_START BIT_2 /* Start Time Stamp Timer */ |
Definition at line 2006 of file if_mskreg.h.
◆ GMT_ST_STOP
| #define GMT_ST_STOP BIT_1 /* Stop Time Stamp Timer */ |
Definition at line 2007 of file if_mskreg.h.
◆ GPC_75_OHM
| #define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ |
Definition at line 2084 of file if_mskreg.h.
◆ GPC_ANEG_0
| #define GPC_ANEG_0 BIT_19 /* ANEG[0] */ |
Definition at line 2091 of file if_mskreg.h.
◆ GPC_ANEG_1
| #define GPC_ANEG_1 BIT_14 /* ANEG[1] */ |
Definition at line 2096 of file if_mskreg.h.
◆ GPC_ANEG_2
| #define GPC_ANEG_2 BIT_15 /* ANEG[2] */ |
Definition at line 2095 of file if_mskreg.h.
◆ GPC_ANEG_3
| #define GPC_ANEG_3 BIT_16 /* ANEG[3] */ |
Definition at line 2094 of file if_mskreg.h.
◆ GPC_DIS_125
| #define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */ |
Definition at line 2093 of file if_mskreg.h.
◆ GPC_DIS_FC
| #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ |
Definition at line 2085 of file if_mskreg.h.
◆ GPC_DIS_SLEEP
| #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ |
Definition at line 2086 of file if_mskreg.h.
◆ GPC_ENA_PAUSE
| #define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ |
Definition at line 2097 of file if_mskreg.h.
◆ GPC_ENA_XC
| #define GPC_ENA_XC BIT_18 /* Enable MDI crossover */ |
Definition at line 2092 of file if_mskreg.h.
◆ GPC_HWCFG_M_0
| #define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */ |
Definition at line 2090 of file if_mskreg.h.
◆ GPC_HWCFG_M_1
| #define GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */ |
Definition at line 2089 of file if_mskreg.h.
◆ GPC_HWCFG_M_2
| #define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */ |
Definition at line 2088 of file if_mskreg.h.
◆ GPC_HWCFG_M_3
| #define GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */ |
Definition at line 2087 of file if_mskreg.h.
◆ GPC_INT_POL
| #define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */ |
Definition at line 2083 of file if_mskreg.h.
◆ GPC_PHYADDR_0
| #define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */ |
Definition at line 2102 of file if_mskreg.h.
◆ GPC_PHYADDR_1
| #define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */ |
Definition at line 2101 of file if_mskreg.h.
◆ GPC_PHYADDR_2
| #define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */ |
Definition at line 2100 of file if_mskreg.h.
◆ GPC_PHYADDR_3
| #define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */ |
Definition at line 2099 of file if_mskreg.h.
◆ GPC_PHYADDR_4
| #define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */ |
Definition at line 2098 of file if_mskreg.h.
◆ GPC_RST_CLR
| #define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */ |
Definition at line 2103 of file if_mskreg.h.
◆ GPC_RST_SET
| #define GPC_RST_SET BIT_0 /* Set GPHY Reset */ |
Definition at line 2104 of file if_mskreg.h.
◆ GPC_SEL_BDT
| #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ |
Definition at line 2082 of file if_mskreg.h.
◆ GPHY_CTRL
| #define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */ |
Definition at line 744 of file if_mskreg.h.
◆ HW_OWNER
| #define HW_OWNER 0x80000000 |
Definition at line 2223 of file if_mskreg.h.
◆ I2C_025K_DEV
| #define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */ |
Definition at line 1015 of file if_mskreg.h.
◆ I2C_05K_DEV
| #define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */ |
Definition at line 1016 of file if_mskreg.h.
◆ I2C_16K_DEV
| #define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */ |
Definition at line 1021 of file if_mskreg.h.
◆ I2C_1K_DEV
| #define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */ |
Definition at line 1017 of file if_mskreg.h.
◆ I2C_2K_DEV
| #define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */ |
Definition at line 1018 of file if_mskreg.h.
◆ I2C_32K_DEV
| #define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */ |
Definition at line 1022 of file if_mskreg.h.
◆ I2C_4K_DEV
| #define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */ |
Definition at line 1019 of file if_mskreg.h.
◆ I2C_8K_DEV
| #define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */ |
Definition at line 1020 of file if_mskreg.h.
◆ I2C_ADDR
| #define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */ |
Definition at line 1011 of file if_mskreg.h.
◆ I2C_BURST_LEN
| #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ |
Definition at line 1013 of file if_mskreg.h.
◆ I2C_CLK
| #define I2C_CLK BIT_0 /* I2C Clock Port */ |
Definition at line 1031 of file if_mskreg.h.
◆ I2C_CLR_IRQ
| #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ |
Definition at line 1026 of file if_mskreg.h.
◆ I2C_DATA
| #define I2C_DATA BIT_1 /* I2C Data Port */ |
Definition at line 1030 of file if_mskreg.h.
◆ I2C_DATA_DIR
Definition at line 1029 of file if_mskreg.h.
◆ I2C_DEV_SEL
| #define I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */ |
Definition at line 1012 of file if_mskreg.h.
◆ I2C_DEV_SIZE
| #define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */ |
Definition at line 1014 of file if_mskreg.h.
◆ I2C_FLAG
| #define I2C_FLAG BIT_31 /* Start read/write if WR */ |
Definition at line 1010 of file if_mskreg.h.
◆ I2C_SENS_ADDR
| #define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */ |
Definition at line 1034 of file if_mskreg.h.
◆ I2C_STOP
| #define I2C_STOP BIT_0 /* Interrupt I2C transfer */ |
Definition at line 1023 of file if_mskreg.h.
◆ INIT_SUM
| #define INIT_SUM 0x00080000 |
Definition at line 2232 of file if_mskreg.h.
◆ INS_VLAN
| #define INS_VLAN 0x00200000 |
Definition at line 2234 of file if_mskreg.h.
◆ IPG_DATA_DEF
| #define IPG_DATA_DEF 0x1e |
Definition at line 1892 of file if_mskreg.h.
◆ IPG_DATA_VAL
| #define IPG_DATA_VAL | ( | x | ) | ((x) & GM_SMOD_IPG_MSK) |
Definition at line 1889 of file if_mskreg.h.
◆ KEY_IDX_0
| #define KEY_IDX_0 0 /* offset for location of KEY 0 */ |
Definition at line 542 of file if_mskreg.h.
◆ KEY_IDX_1
| #define KEY_IDX_1 4 /* offset for location of KEY 1 */ |
Definition at line 543 of file if_mskreg.h.
◆ KEY_IDX_2
| #define KEY_IDX_2 8 /* offset for location of KEY 2 */ |
Definition at line 544 of file if_mskreg.h.
◆ KEY_IDX_3
| #define KEY_IDX_3 12 /* offset for location of KEY 3 */ |
Definition at line 545 of file if_mskreg.h.
◆ LED_PAR_CTRL_ACT
| #define LED_PAR_CTRL_ACT 0x08 |
Definition at line 1602 of file if_mskreg.h.
◆ LED_PAR_CTRL_ACT_BL
| #define LED_PAR_CTRL_ACT_BL 0x0b |
Definition at line 1605 of file if_mskreg.h.
◆ LED_PAR_CTRL_COL_BL
| #define LED_PAR_CTRL_COL_BL 0x0e |
Definition at line 1608 of file if_mskreg.h.
◆ LED_PAR_CTRL_COLX
| #define LED_PAR_CTRL_COLX 0x00 |
Definition at line 1594 of file if_mskreg.h.
◆ LED_PAR_CTRL_DP_COL
| #define LED_PAR_CTRL_DP_COL 0x03 |
Definition at line 1597 of file if_mskreg.h.
◆ LED_PAR_CTRL_DUPLEX
| #define LED_PAR_CTRL_DUPLEX 0x02 |
Definition at line 1596 of file if_mskreg.h.
◆ LED_PAR_CTRL_ERROR
| #define LED_PAR_CTRL_ERROR 0x01 |
Definition at line 1595 of file if_mskreg.h.
◆ LED_PAR_CTRL_INACT
| #define LED_PAR_CTRL_INACT 0x0f |
Definition at line 1609 of file if_mskreg.h.
◆ LED_PAR_CTRL_LINK
| #define LED_PAR_CTRL_LINK 0x05 |
Definition at line 1599 of file if_mskreg.h.
◆ LED_PAR_CTRL_LNK_AC
| #define LED_PAR_CTRL_LNK_AC 0x0a |
Definition at line 1604 of file if_mskreg.h.
◆ LED_PAR_CTRL_LNK_RX
| #define LED_PAR_CTRL_LNK_RX 0x09 |
Definition at line 1603 of file if_mskreg.h.
◆ LED_PAR_CTRL_RX
| #define LED_PAR_CTRL_RX 0x07 |
Definition at line 1601 of file if_mskreg.h.
◆ LED_PAR_CTRL_RX_BL
| #define LED_PAR_CTRL_RX_BL 0x0d |
Definition at line 1607 of file if_mskreg.h.
◆ LED_PAR_CTRL_SPEED
| #define LED_PAR_CTRL_SPEED 0x04 |
Definition at line 1598 of file if_mskreg.h.
◆ LED_PAR_CTRL_TX
| #define LED_PAR_CTRL_TX 0x06 |
Definition at line 1600 of file if_mskreg.h.
◆ LED_PAR_CTRL_TX_BL
| #define LED_PAR_CTRL_TX_BL 0x0c |
Definition at line 1606 of file if_mskreg.h.
◆ LED_STAT_OFF
| #define LED_STAT_OFF BIT_0 /* Status LED Off */ |
Definition at line 807 of file if_mskreg.h.
◆ LED_STAT_ON
| #define LED_STAT_ON BIT_1 /* Status LED On */ |
Definition at line 806 of file if_mskreg.h.
◆ LOCK_SUM
| #define LOCK_SUM 0x00100000 |
Definition at line 2233 of file if_mskreg.h.
◆ MAC_TX_CLK_0_MHZ
| #define MAC_TX_CLK_0_MHZ 2 |
Definition at line 1495 of file if_mskreg.h.
◆ MAC_TX_CLK_25_MHZ
| #define MAC_TX_CLK_25_MHZ 7 |
Definition at line 1497 of file if_mskreg.h.
◆ MAC_TX_CLK_2_5_MHZ
| #define MAC_TX_CLK_2_5_MHZ 6 |
Definition at line 1496 of file if_mskreg.h.
◆ MO_LED_BLINK
| #define MO_LED_BLINK 1 |
Definition at line 1545 of file if_mskreg.h.
◆ MO_LED_NORM
| #define MO_LED_NORM 0 |
Definition at line 1544 of file if_mskreg.h.
◆ MO_LED_OFF
| #define MO_LED_OFF 2 |
Definition at line 1546 of file if_mskreg.h.
◆ MO_LED_ON
| #define MO_LED_ON 3 |
Definition at line 1547 of file if_mskreg.h.
◆ MR_ADDR
| #define MR_ADDR | ( | Mac, | |
| Offs | |||
| ) | (((Mac) << 7) + (Offs)) |
Definition at line 537 of file if_mskreg.h.
◆ MSK_ADDR_HI
| #define MSK_ADDR_HI | ( | x | ) | ((uint64_t) (x) >> 32) |
Definition at line 2178 of file if_mskreg.h.
◆ MSK_ADDR_LO
| #define MSK_ADDR_LO | ( | x | ) | ((uint64_t) (x) & 0xffffffffUL) |
Definition at line 2177 of file if_mskreg.h.
◆ MSK_BMU_RX_WM
| #define MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ |
Definition at line 1195 of file if_mskreg.h.
◆ MSK_BMU_RX_WM_PEX
| #define MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */ |
Definition at line 1198 of file if_mskreg.h.
◆ MSK_BMU_TX_WM
| #define MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ |
Definition at line 1196 of file if_mskreg.h.
◆ MSK_ECU_AE_THR
| #define MSK_ECU_AE_THR 0x0070 /* Almost Empty Threshold */ |
Definition at line 1191 of file if_mskreg.h.
◆ MSK_ECU_JUMBO_WM
| #define MSK_ECU_JUMBO_WM 0x01 |
Definition at line 1193 of file if_mskreg.h.
◆ MSK_ECU_LLPP
| #define MSK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */ |
Definition at line 1190 of file if_mskreg.h.
◆ MSK_ECU_TXFF_LEV
| #define MSK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */ |
Definition at line 1192 of file if_mskreg.h.
◆ MSK_ECU_ULPP
| #define MSK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */ |
Definition at line 1189 of file if_mskreg.h.
◆ MSK_FLAG_AUTOTX_CSUM
| #define MSK_FLAG_AUTOTX_CSUM 0x0080 |
Definition at line 2569 of file if_mskreg.h.
◆ MSK_FLAG_DESCV2
| #define MSK_FLAG_DESCV2 0x0040 |
Definition at line 2568 of file if_mskreg.h.
◆ MSK_FLAG_DETACH
| #define MSK_FLAG_DETACH 0x4000 |
Definition at line 2574 of file if_mskreg.h.
◆ MSK_FLAG_FASTETHER
| #define MSK_FLAG_FASTETHER 0x0004 |
Definition at line 2564 of file if_mskreg.h.
◆ MSK_FLAG_JUMBO
| #define MSK_FLAG_JUMBO 0x0008 |
Definition at line 2565 of file if_mskreg.h.
◆ MSK_FLAG_JUMBO_NOCSUM
| #define MSK_FLAG_JUMBO_NOCSUM 0x0010 |
Definition at line 2566 of file if_mskreg.h.
◆ MSK_FLAG_LINK
| #define MSK_FLAG_LINK 0x8000 |
Definition at line 2575 of file if_mskreg.h.
◆ MSK_FLAG_MSI
| #define MSK_FLAG_MSI 0x0001 |
Definition at line 2563 of file if_mskreg.h.
◆ MSK_FLAG_NOHWVLAN
| #define MSK_FLAG_NOHWVLAN 0x0100 |
Definition at line 2570 of file if_mskreg.h.
◆ MSK_FLAG_NORX_CSUM
| #define MSK_FLAG_NORX_CSUM 0x0400 |
Definition at line 2572 of file if_mskreg.h.
◆ MSK_FLAG_NORXCHK
| #define MSK_FLAG_NORXCHK 0x0200 |
Definition at line 2571 of file if_mskreg.h.
◆ MSK_FLAG_RAMBUF
| #define MSK_FLAG_RAMBUF 0x0020 |
Definition at line 2567 of file if_mskreg.h.
◆ MSK_FLAG_SUSPEND
| #define MSK_FLAG_SUSPEND 0x2000 |
Definition at line 2573 of file if_mskreg.h.
◆ MSK_IF_LOCK
Definition at line 2547 of file if_mskreg.h.
◆ MSK_IF_LOCK_ASSERT
| #define MSK_IF_LOCK_ASSERT | ( | _sc | ) | MSK_LOCK_ASSERT((_sc)->msk_softc) |
Definition at line 2549 of file if_mskreg.h.
◆ MSK_IF_READ_1
| #define MSK_IF_READ_1 | ( | sc_if, | |
| reg | |||
| ) | CSR_READ_1((sc_if)->msk_softc, (reg)) |
Definition at line 2157 of file if_mskreg.h.
◆ MSK_IF_READ_2
| #define MSK_IF_READ_2 | ( | sc_if, | |
| reg | |||
| ) | CSR_READ_2((sc_if)->msk_softc, (reg)) |
Definition at line 2155 of file if_mskreg.h.
◆ MSK_IF_READ_4
| #define MSK_IF_READ_4 | ( | sc_if, | |
| reg | |||
| ) | CSR_READ_4((sc_if)->msk_softc, (reg)) |
Definition at line 2153 of file if_mskreg.h.
◆ MSK_IF_UNLOCK
| #define MSK_IF_UNLOCK | ( | _sc | ) | MSK_UNLOCK((_sc)->msk_softc) |
Definition at line 2548 of file if_mskreg.h.
◆ MSK_IF_WRITE_1
| #define MSK_IF_WRITE_1 | ( | sc_if, | |
| reg, | |||
| val | |||
| ) | CSR_WRITE_1((sc_if)->msk_softc, (reg), (val)) |
Definition at line 2164 of file if_mskreg.h.
◆ MSK_IF_WRITE_2
| #define MSK_IF_WRITE_2 | ( | sc_if, | |
| reg, | |||
| val | |||
| ) | CSR_WRITE_2((sc_if)->msk_softc, (reg), (val)) |
Definition at line 2162 of file if_mskreg.h.
◆ MSK_IF_WRITE_4
| #define MSK_IF_WRITE_4 | ( | sc_if, | |
| reg, | |||
| val | |||
| ) | CSR_WRITE_4((sc_if)->msk_softc, (reg), (val)) |
Definition at line 2160 of file if_mskreg.h.
◆ MSK_INC
| #define MSK_INC | ( | x, | |
| y | |||
| ) | (x) = (x + 1) % y |
Definition at line 2426 of file if_mskreg.h.
◆ MSK_INT_HOLDOFF_DEFAULT
| #define MSK_INT_HOLDOFF_DEFAULT 100 |
Definition at line 2445 of file if_mskreg.h.
◆ MSK_JUMBO_FRAMELEN
| #define MSK_JUMBO_FRAMELEN 9022 |
Definition at line 2357 of file if_mskreg.h.
◆ MSK_JUMBO_MTU
| #define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) |
Definition at line 2358 of file if_mskreg.h.
◆ MSK_JUMBO_RX_BUF_CNT
| #define MSK_JUMBO_RX_BUF_CNT MSK_JUMBO_RX_RING_CNT |
Definition at line 2434 of file if_mskreg.h.
◆ MSK_JUMBO_RX_RING_ADDR
| #define MSK_JUMBO_RX_RING_ADDR | ( | sc, | |
| i | |||
| ) | ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) |
Definition at line 2416 of file if_mskreg.h.
◆ MSK_JUMBO_RX_RING_CNT
| #define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT |
Definition at line 2337 of file if_mskreg.h.
◆ MSK_JUMBO_RX_RING_SZ
| #define MSK_JUMBO_RX_RING_SZ (sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT) |
Definition at line 2423 of file if_mskreg.h.
◆ MSK_LOCK
| #define MSK_LOCK | ( | _sc | ) | mtx_lock(&(_sc)->msk_mtx) |
Definition at line 2544 of file if_mskreg.h.
◆ MSK_LOCK_ASSERT
| #define MSK_LOCK_ASSERT | ( | _sc | ) | mtx_assert(&(_sc)->msk_mtx, MA_OWNED) |
Definition at line 2546 of file if_mskreg.h.
◆ MSK_MAX_FRAMELEN
| #define MSK_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) |
Definition at line 2359 of file if_mskreg.h.
◆ MSK_MAXTXSEGS
| #define MSK_MAXTXSEGS 35 |
Definition at line 2338 of file if_mskreg.h.
◆ MSK_MIN_FRAMELEN
| #define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) |
Definition at line 2361 of file if_mskreg.h.
◆ MSK_MIN_RXQ_SIZE
| #define MSK_MIN_RXQ_SIZE 10 |
Definition at line 1216 of file if_mskreg.h.
◆ MSK_MIN_TXQ_SIZE
| #define MSK_MIN_TXQ_SIZE 10 |
Definition at line 1218 of file if_mskreg.h.
◆ MSK_PCI_BUS
| #define MSK_PCI_BUS 0 |
Definition at line 2437 of file if_mskreg.h.
◆ MSK_PCIX_BUS
| #define MSK_PCIX_BUS 1 |
Definition at line 2438 of file if_mskreg.h.
◆ MSK_PEX_BUS
| #define MSK_PEX_BUS 2 |
Definition at line 2439 of file if_mskreg.h.
◆ MSK_PHY_POWERDOWN
| #define MSK_PHY_POWERDOWN 0 |
Definition at line 2592 of file if_mskreg.h.
◆ MSK_PHY_POWERUP
| #define MSK_PHY_POWERUP 1 |
Definition at line 2591 of file if_mskreg.h.
◆ MSK_PORT_A
| #define MSK_PORT_A 0 |
Definition at line 2121 of file if_mskreg.h.
◆ MSK_PORT_B
| #define MSK_PORT_B 1 |
Definition at line 2122 of file if_mskreg.h.
◆ MSK_PROC_DEFAULT
| #define MSK_PROC_DEFAULT (MSK_RX_RING_CNT / 2) |
Definition at line 2441 of file if_mskreg.h.
◆ MSK_PROC_MAX
| #define MSK_PROC_MAX (MSK_RX_RING_CNT - 1) |
Definition at line 2443 of file if_mskreg.h.
◆ MSK_PROC_MIN
| #define MSK_PROC_MIN 30 |
Definition at line 2442 of file if_mskreg.h.
◆ MSK_PUT_WM
| #define MSK_PUT_WM 10 |
Definition at line 2448 of file if_mskreg.h.
◆ MSK_RAM_QUOTA_RX
| #define MSK_RAM_QUOTA_RX 80 |
Definition at line 1220 of file if_mskreg.h.
◆ MSK_RB_LLPP_B
| #define MSK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ |
Definition at line 1186 of file if_mskreg.h.
◆ MSK_RB_LLPP_S
| #define MSK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */ |
Definition at line 1185 of file if_mskreg.h.
◆ MSK_RB_ULPP
| #define MSK_RB_ULPP (8 * 1024) /* Upper Level in kB/8 */ |
Definition at line 1184 of file if_mskreg.h.
◆ MSK_RESERVED_TX_DESC_CNT
| #define MSK_RESERVED_TX_DESC_CNT 3 |
Definition at line 2354 of file if_mskreg.h.
◆ MSK_RI_TO_53
| #define MSK_RI_TO_53 36 /* RAM interface timeout */ |
Definition at line 1063 of file if_mskreg.h.
◆ MSK_RING_ALIGN
| #define MSK_RING_ALIGN 32768 |
Definition at line 2180 of file if_mskreg.h.
◆ MSK_RX_BUF_ALIGN
| #define MSK_RX_BUF_ALIGN 8 |
Definition at line 2336 of file if_mskreg.h.
◆ MSK_RX_BUF_CNT
| #define MSK_RX_BUF_CNT MSK_RX_RING_CNT |
Definition at line 2433 of file if_mskreg.h.
◆ MSK_RX_INC
| #define MSK_RX_INC | ( | x, | |
| y | |||
| ) | (x) = (x + 1) % y |
Definition at line 2432 of file if_mskreg.h.
◆ MSK_RX_RING_ADDR
| #define MSK_RX_RING_ADDR | ( | sc, | |
| i | |||
| ) | ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) |
Definition at line 2414 of file if_mskreg.h.
◆ MSK_RX_RING_CNT
| #define MSK_RX_RING_CNT 256 |
Definition at line 2334 of file if_mskreg.h.
◆ MSK_RX_RING_SZ
| #define MSK_RX_RING_SZ (sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT) |
Definition at line 2421 of file if_mskreg.h.
◆ MSK_STAT_ALIGN
| #define MSK_STAT_ALIGN 32768 |
Definition at line 2181 of file if_mskreg.h.
◆ MSK_TIMEOUT
| #define MSK_TIMEOUT 1000 |
Definition at line 2590 of file if_mskreg.h.
◆ MSK_TSO_MAXSGSIZE
| #define MSK_TSO_MAXSGSIZE 4096 |
Definition at line 2339 of file if_mskreg.h.
◆ MSK_TSO_MAXSIZE
| #define MSK_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) |
Definition at line 2340 of file if_mskreg.h.
◆ MSK_TX_RING_ADDR
| #define MSK_TX_RING_ADDR | ( | sc, | |
| i | |||
| ) | ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i)) |
Definition at line 2412 of file if_mskreg.h.
◆ MSK_TX_RING_CNT
| #define MSK_TX_RING_CNT 256 |
Definition at line 2333 of file if_mskreg.h.
◆ MSK_TX_RING_SZ
| #define MSK_TX_RING_SZ (sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT) |
Definition at line 2419 of file if_mskreg.h.
◆ MSK_TX_TIMEOUT
| #define MSK_TX_TIMEOUT 5 |
Definition at line 2447 of file if_mskreg.h.
◆ MSK_UNLOCK
| #define MSK_UNLOCK | ( | _sc | ) | mtx_unlock(&(_sc)->msk_mtx) |
Definition at line 2545 of file if_mskreg.h.
◆ MSK_USECS
| #define MSK_USECS | ( | sc, | |
| us | |||
| ) | ((sc)->msk_clock * (us)) |
Definition at line 2551 of file if_mskreg.h.
◆ NO_UPDATE
| #define NO_UPDATE 0x80000000 |
Definition at line 2243 of file if_mskreg.h.
◆ NO_WARNING
| #define NO_WARNING 0x40000000 |
Definition at line 2242 of file if_mskreg.h.
◆ OP_ADDR64
| #define OP_ADDR64 0x21000000 |
Definition at line 2255 of file if_mskreg.h.
◆ OP_ADDR64VLAN
Definition at line 2257 of file if_mskreg.h.
◆ OP_BUFFER
| #define OP_BUFFER 0x40000000 |
Definition at line 2262 of file if_mskreg.h.
◆ OP_LARGESEND
| #define OP_LARGESEND 0x43000000 |
Definition at line 2264 of file if_mskreg.h.
◆ OP_LRGLEN
| #define OP_LRGLEN 0x24000000 |
Definition at line 2258 of file if_mskreg.h.
◆ OP_LRGLENVLAN
Definition at line 2259 of file if_mskreg.h.
◆ OP_MSS
| #define OP_MSS 0x28000000 |
Definition at line 2260 of file if_mskreg.h.
◆ OP_MSSVLAN
Definition at line 2261 of file if_mskreg.h.
◆ OP_PACKET
| #define OP_PACKET 0x41000000 |
Definition at line 2263 of file if_mskreg.h.
◆ OP_PUTIDX
| #define OP_PUTIDX 0x70000000 |
Definition at line 2277 of file if_mskreg.h.
◆ OP_RSS_HASH
| #define OP_RSS_HASH 0x65000000 |
Definition at line 2273 of file if_mskreg.h.
◆ OP_RXCHKS
| #define OP_RXCHKS 0x64000000 |
Definition at line 2270 of file if_mskreg.h.
◆ OP_RXCHKSVLAN
Definition at line 2271 of file if_mskreg.h.
◆ OP_RXSTAT
| #define OP_RXSTAT 0x60000000 |
Definition at line 2267 of file if_mskreg.h.
◆ OP_RXTIMESTAMP
| #define OP_RXTIMESTAMP 0x61000000 |
Definition at line 2268 of file if_mskreg.h.
◆ OP_RXTIMEVLAN
| #define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN) |
Definition at line 2272 of file if_mskreg.h.
◆ OP_RXVLAN
| #define OP_RXVLAN 0x62000000 |
Definition at line 2269 of file if_mskreg.h.
◆ OP_TCPCHKSUM
| #define OP_TCPCHKSUM OP_TCPSTART |
Definition at line 2250 of file if_mskreg.h.
◆ OP_TCPINIT
| #define OP_TCPINIT 0x14000000 |
Definition at line 2248 of file if_mskreg.h.
◆ OP_TCPIS
| #define OP_TCPIS (OP_TCPINIT | OP_TCPSTART) |
Definition at line 2251 of file if_mskreg.h.
◆ OP_TCPLCK
| #define OP_TCPLCK 0x18000000 |
Definition at line 2249 of file if_mskreg.h.
◆ OP_TCPLISW
| #define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE) |
Definition at line 2254 of file if_mskreg.h.
◆ OP_TCPLSW
| #define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE) |
Definition at line 2253 of file if_mskreg.h.
◆ OP_TCPLW
| #define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE) |
Definition at line 2252 of file if_mskreg.h.
◆ OP_TCPSTART
| #define OP_TCPSTART 0x12000000 |
Definition at line 2247 of file if_mskreg.h.
◆ OP_TCPWRITE
| #define OP_TCPWRITE 0x11000000 |
Definition at line 2246 of file if_mskreg.h.
◆ OP_TXINDEXLE
| #define OP_TXINDEXLE 0x68000000 |
Definition at line 2274 of file if_mskreg.h.
◆ OP_VLAN
| #define OP_VLAN 0x22000000 |
Definition at line 2256 of file if_mskreg.h.
◆ PACKET_SEND
| #define PACKET_SEND 0x04000000 |
Definition at line 2240 of file if_mskreg.h.
◆ PC_CLR_IRQ_CHK
| #define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */ |
Definition at line 2011 of file if_mskreg.h.
◆ PC_POLL_OP_OFF
| #define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */ |
Definition at line 2014 of file if_mskreg.h.
◆ PC_POLL_OP_ON
| #define PC_POLL_OP_ON BIT_3 /* Operational Mode On */ |
Definition at line 2013 of file if_mskreg.h.
◆ PC_POLL_RQ
| #define PC_POLL_RQ BIT_4 /* Poll Request Start */ |
Definition at line 2012 of file if_mskreg.h.
◆ PC_POLL_RST_CLR
| #define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */ |
Definition at line 2015 of file if_mskreg.h.
◆ PC_POLL_RST_SET
| #define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */ |
Definition at line 2016 of file if_mskreg.h.
◆ PC_VAUX_DIS
| #define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ |
Definition at line 811 of file if_mskreg.h.
◆ PC_VAUX_ENA
| #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ |
Definition at line 810 of file if_mskreg.h.
◆ PC_VAUX_OFF
| #define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ |
Definition at line 815 of file if_mskreg.h.
◆ PC_VAUX_ON
| #define PC_VAUX_ON BIT_3 /* Switch VAUX On */ |
Definition at line 814 of file if_mskreg.h.
◆ PC_VCC_DIS
| #define PC_VCC_DIS BIT_4 /* Switch VCC Disable */ |
Definition at line 813 of file if_mskreg.h.
◆ PC_VCC_ENA
| #define PC_VCC_ENA BIT_5 /* Switch VCC Enable */ |
Definition at line 812 of file if_mskreg.h.
◆ PC_VCC_OFF
| #define PC_VCC_OFF BIT_0 /* Switch VCC Off */ |
Definition at line 817 of file if_mskreg.h.
◆ PC_VCC_ON
| #define PC_VCC_ON BIT_1 /* Switch VCC On */ |
Definition at line 816 of file if_mskreg.h.
◆ PCI_ASPM_A1_MODE_SELECT
| #define PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */ |
Definition at line 339 of file if_mskreg.h.
◆ PCI_ASPM_CLKREQ_PAD_CTL
| #define PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */ |
Definition at line 338 of file if_mskreg.h.
◆ PCI_ASPM_CLKRUN_REQUEST
| #define PCI_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */ |
Definition at line 336 of file if_mskreg.h.
◆ PCI_ASPM_FORCE_CLKREQ_ENA
| #define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */ |
Definition at line 337 of file if_mskreg.h.
◆ PCI_ASPM_GPHY_LINK_DOWN
| #define PCI_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */ |
Definition at line 334 of file if_mskreg.h.
◆ PCI_ASPM_INT_FIFO_EMPTY
| #define PCI_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */ |
Definition at line 335 of file if_mskreg.h.
◆ PCI_BASE_1ST
| #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ |
Definition at line 230 of file if_mskreg.h.
◆ PCI_BASE_2ND
| #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ |
Definition at line 231 of file if_mskreg.h.
◆ PCI_BURST_DIS
| #define PCI_BURST_DIS BIT_9 /* Burst Disable */ |
Definition at line 286 of file if_mskreg.h.
◆ PCI_CF1_DIS_REL_EVT_RST
| #define PCI_CF1_DIS_REL_EVT_RST BIT_24 /* Dis. Rel. Event during PCIE reset */ |
Definition at line 377 of file if_mskreg.h.
◆ PCI_CF1_ENA_CFG_LDR_DONE
| #define PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */ |
Definition at line 389 of file if_mskreg.h.
◆ PCI_CF1_ENA_TXBMU_RD_IDLE
| #define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */ |
Definition at line 390 of file if_mskreg.h.
◆ PCI_CF1_ENA_TXBMU_WR_IDLE
| #define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */ |
Definition at line 391 of file if_mskreg.h.
◆ PCI_CF1_GAT_LDR_NOT_FIN
| #define PCI_CF1_GAT_LDR_NOT_FIN BIT_20 /* EEPROM Loader Finished */ |
Definition at line 383 of file if_mskreg.h.
◆ PCI_CF1_GAT_PCIE_RESET
| #define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */ |
Definition at line 385 of file if_mskreg.h.
◆ PCI_CF1_GAT_PCIE_RX_IDLE
| #define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */ |
Definition at line 384 of file if_mskreg.h.
◆ PCI_CF1_PCIE_RST_CLKREQ
| #define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */ |
Definition at line 387 of file if_mskreg.h.
◆ PCI_CF1_PRST_PHY_CLKREQ
| #define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */ |
Definition at line 386 of file if_mskreg.h.
◆ PCI_CF1_REL_LDR_NOT_FIN
| #define PCI_CF1_REL_LDR_NOT_FIN BIT_23 /* EEPROM Loader Not Finished */ |
Definition at line 379 of file if_mskreg.h.
◆ PCI_CF1_REL_PCIE_RESET
| #define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */ |
Definition at line 381 of file if_mskreg.h.
◆ PCI_CF1_REL_VMAIN_AVLBL
| #define PCI_CF1_REL_VMAIN_AVLBL BIT_22 /* Vmain available */ |
Definition at line 380 of file if_mskreg.h.
◆ PCI_CFG_REG_0
| #define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */ |
Definition at line 238 of file if_mskreg.h.
◆ PCI_CFG_REG_1
| #define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */ |
Definition at line 239 of file if_mskreg.h.
◆ PCI_CLK_GATE_PEX_UNIT_ENA
| #define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */ |
Definition at line 340 of file if_mskreg.h.
◆ PCI_CLK_GATE_ROOT_COR_ENA
| #define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */ |
Definition at line 341 of file if_mskreg.h.
◆ PCI_CLK_MACSEC_DIS
| #define PCI_CLK_MACSEC_DIS BIT_17 /* Disable Clock MACSec. */ |
Definition at line 329 of file if_mskreg.h.
◆ PCI_CLS_OPT
| #define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */ |
Definition at line 290 of file if_mskreg.h.
◆ PCI_CTL_BYPASS_VMAIN_AV
| #define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */ |
Definition at line 347 of file if_mskreg.h.
◆ PCI_CTL_DIV_CORE_CLK_ENA
| #define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */ |
Definition at line 345 of file if_mskreg.h.
◆ PCI_CTL_SRESET_VMAIN_AV
| #define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */ |
Definition at line 346 of file if_mskreg.h.
◆ PCI_CTL_TIM_VMAIN_AV0
| #define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */ |
Definition at line 349 of file if_mskreg.h.
◆ PCI_CTL_TIM_VMAIN_AV1
| #define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */ |
Definition at line 348 of file if_mskreg.h.
◆ PCI_CTL_TIM_VMAIN_AV_MSK
Definition at line 350 of file if_mskreg.h.
◆ PCI_DEV_SEL
| #define PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */ |
Definition at line 294 of file if_mskreg.h.
◆ PCI_DIS_BOOT
| #define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ |
Definition at line 269 of file if_mskreg.h.
◆ PCI_DIS_MRL
| #define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ |
Definition at line 282 of file if_mskreg.h.
◆ PCI_DIS_MRM
| #define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ |
Definition at line 283 of file if_mskreg.h.
◆ PCI_DIS_MWI
| #define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */ |
Definition at line 284 of file if_mskreg.h.
◆ PCI_DIS_PCI_CLK
| #define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */ |
Definition at line 287 of file if_mskreg.h.
◆ PCI_DISC_CLS
| #define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */ |
Definition at line 285 of file if_mskreg.h.
◆ PCI_EN_DUMMY_RD
| #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ |
Definition at line 307 of file if_mskreg.h.
◆ PCI_EN_FPROM
| #define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ |
Definition at line 271 of file if_mskreg.h.
◆ PCI_EN_IO
| #define PCI_EN_IO BIT_23 /* Mapping to I/O space */ |
Definition at line 270 of file if_mskreg.h.
◆ PCI_EXT_PATCH_0
| #define PCI_EXT_PATCH_0 BIT_4 |
Definition at line 306 of file if_mskreg.h.
◆ PCI_EXT_PATCH_1
| #define PCI_EXT_PATCH_1 BIT_5 |
Definition at line 305 of file if_mskreg.h.
◆ PCI_EXT_PATCH_2
| #define PCI_EXT_PATCH_2 BIT_6 |
Definition at line 304 of file if_mskreg.h.
◆ PCI_EXT_PATCH_3
| #define PCI_EXT_PATCH_3 BIT_7 |
Definition at line 303 of file if_mskreg.h.
◆ PCI_EXT_PATCHS
| #define PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */ |
Definition at line 302 of file if_mskreg.h.
◆ PCI_FORCE_ASPM_REQUEST
| #define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */ |
Definition at line 333 of file if_mskreg.h.
◆ PCI_FORCE_BE
| #define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ |
Definition at line 281 of file if_mskreg.h.
◆ PCI_GAT_CLKRUN_REQ_REL
| #define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */ |
Definition at line 368 of file if_mskreg.h.
◆ PCI_GAT_GPHY_LINK_DOWN
| #define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */ |
Definition at line 374 of file if_mskreg.h.
◆ PCI_GAT_GPHY_N_REC_PACKET
| #define PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */ |
Definition at line 365 of file if_mskreg.h.
◆ PCI_GAT_INT_FIFO_EMPTY
| #define PCI_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */ |
Definition at line 366 of file if_mskreg.h.
◆ PCI_GAT_LOADER_FINISHED
| #define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */ |
Definition at line 372 of file if_mskreg.h.
◆ PCI_GAT_MAIN_PWR_N_AVAIL
| #define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */ |
Definition at line 367 of file if_mskreg.h.
◆ PCI_GAT_PCIE_ENTER_L1_ST
| #define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */ |
Definition at line 371 of file if_mskreg.h.
◆ PCI_GAT_PCIE_RESET_ASS
| #define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */ |
Definition at line 369 of file if_mskreg.h.
◆ PCI_GAT_PCIE_RST_ASSERTED
| #define PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */ |
Definition at line 364 of file if_mskreg.h.
◆ PCI_GAT_PCIE_RX_EL_IDLE
| #define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */ |
Definition at line 373 of file if_mskreg.h.
◆ PCI_GAT_PME_DE_ASSERTED
| #define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */ |
Definition at line 370 of file if_mskreg.h.
◆ PCI_OS_DLLC_MSK
| #define PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Counters Values */ |
Definition at line 319 of file if_mskreg.h.
◆ PCI_OS_DLLE_MSK
| #define PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */ |
Definition at line 317 of file if_mskreg.h.
◆ PCI_OS_DLLR_MSK
| #define PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Counters Values */ |
Definition at line 318 of file if_mskreg.h.
◆ PCI_OS_MODE_MSK
| #define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */ |
Definition at line 314 of file if_mskreg.h.
◆ PCI_OS_PCI64B
| #define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */ |
Definition at line 312 of file if_mskreg.h.
◆ PCI_OS_PCI66M
| #define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */ |
Definition at line 315 of file if_mskreg.h.
◆ PCI_OS_PCI_X
| #define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */ |
Definition at line 316 of file if_mskreg.h.
◆ PCI_OS_PCIX
| #define PCI_OS_PCIX BIT_30 /* PCI-X Bus */ |
Definition at line 313 of file if_mskreg.h.
◆ PCI_OS_SPD_PCI
| #define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */ |
Definition at line 323 of file if_mskreg.h.
◆ PCI_OS_SPD_X100
| #define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */ |
Definition at line 325 of file if_mskreg.h.
◆ PCI_OS_SPD_X133
| #define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */ |
Definition at line 326 of file if_mskreg.h.
◆ PCI_OS_SPD_X66
| #define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */ |
Definition at line 324 of file if_mskreg.h.
◆ PCI_OS_SPEED
| #define PCI_OS_SPEED | ( | val | ) | ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */ |
Definition at line 321 of file if_mskreg.h.
◆ PCI_OUR_REG_1
| #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ |
Definition at line 232 of file if_mskreg.h.
◆ PCI_OUR_REG_2
| #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ |
Definition at line 233 of file if_mskreg.h.
◆ PCI_OUR_REG_3
| #define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */ |
Definition at line 235 of file if_mskreg.h.
◆ PCI_OUR_REG_4
| #define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */ |
Definition at line 236 of file if_mskreg.h.
◆ PCI_OUR_REG_5
| #define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */ |
Definition at line 237 of file if_mskreg.h.
◆ PCI_OUR_STATUS
| #define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */ |
Definition at line 234 of file if_mskreg.h.
◆ PCI_PAGE_128K
| #define PCI_PAGE_128K (3L<<20)/* 128 k pages */ |
Definition at line 278 of file if_mskreg.h.
◆ PCI_PAGE_16
| #define PCI_PAGE_16 (0L<<20)/* 16 k pages */ |
Definition at line 275 of file if_mskreg.h.
◆ PCI_PAGE_32K
| #define PCI_PAGE_32K (1L<<20)/* 32 k pages */ |
Definition at line 276 of file if_mskreg.h.
◆ PCI_PAGE_64K
| #define PCI_PAGE_64K (2L<<20)/* 64 k pages */ |
Definition at line 277 of file if_mskreg.h.
◆ PCI_PAGEREG
| #define PCI_PAGEREG (7L<<16)/* Bit 18..16: Page Register */ |
Definition at line 279 of file if_mskreg.h.
◆ PCI_PAGESIZE
| #define PCI_PAGESIZE (3L<<20)/* Bit 21..20: FLASH Page Size */ |
Definition at line 274 of file if_mskreg.h.
◆ PCI_PATCH_DIR
| #define PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ |
Definition at line 297 of file if_mskreg.h.
◆ PCI_PATCH_DIR_0
| #define PCI_PATCH_DIR_0 BIT_8 |
Definition at line 301 of file if_mskreg.h.
◆ PCI_PATCH_DIR_1
| #define PCI_PATCH_DIR_1 BIT_9 |
Definition at line 300 of file if_mskreg.h.
◆ PCI_PATCH_DIR_2
| #define PCI_PATCH_DIR_2 BIT_10 |
Definition at line 299 of file if_mskreg.h.
◆ PCI_PATCH_DIR_3
| #define PCI_PATCH_DIR_3 BIT_11 |
Definition at line 298 of file if_mskreg.h.
◆ PCI_PEX_LEGNAT
| #define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */ |
Definition at line 280 of file if_mskreg.h.
◆ PCI_REL_CLKRUN_REQ_REL
| #define PCI_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */ |
Definition at line 356 of file if_mskreg.h.
◆ PCI_REL_GPHY_LINK_UP
| #define PCI_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */ |
Definition at line 362 of file if_mskreg.h.
◆ PCI_REL_GPHY_REC_PACKET
| #define PCI_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */ |
Definition at line 353 of file if_mskreg.h.
◆ PCI_REL_INT_FIFO_N_EMPTY
| #define PCI_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */ |
Definition at line 354 of file if_mskreg.h.
◆ PCI_REL_LOADER_NOT_FIN
| #define PCI_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */ |
Definition at line 360 of file if_mskreg.h.
◆ PCI_REL_MAIN_PWR_AVAIL
| #define PCI_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */ |
Definition at line 355 of file if_mskreg.h.
◆ PCI_REL_PCIE_EXIT_L1_ST
| #define PCI_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */ |
Definition at line 359 of file if_mskreg.h.
◆ PCI_REL_PCIE_RESET_ASS
| #define PCI_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */ |
Definition at line 357 of file if_mskreg.h.
◆ PCI_REL_PCIE_RST_DE_ASS
| #define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */ |
Definition at line 352 of file if_mskreg.h.
◆ PCI_REL_PCIE_RX_EX_IDLE
| #define PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */ |
Definition at line 361 of file if_mskreg.h.
◆ PCI_REL_PME_ASSERTED
| #define PCI_REL_PME_ASSERTED BIT_20 /* PME Asserted */ |
Definition at line 358 of file if_mskreg.h.
◆ PCI_REV_DESC
| #define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ |
Definition at line 308 of file if_mskreg.h.
◆ PCI_SKEW_BASE
| #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ |
Definition at line 289 of file if_mskreg.h.
◆ PCI_SKEW_DAS
| #define PCI_SKEW_DAS (0xfL<<4)/* Bit 7.. 4: Skew Ctrl, DAS Ext */ |
Definition at line 288 of file if_mskreg.h.
◆ PCI_TIMER_VALUE_MSK
| #define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */ |
Definition at line 332 of file if_mskreg.h.
◆ PCI_USEDATA64
| #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ |
Definition at line 309 of file if_mskreg.h.
◆ PCI_VPD_ROM_SZ
| #define PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */ |
Definition at line 295 of file if_mskreg.h.
◆ PCI_VPD_WR_THR
| #define PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */ |
Definition at line 293 of file if_mskreg.h.
◆ PCI_Y2_DLL_DIS
| #define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */ |
Definition at line 264 of file if_mskreg.h.
◆ PCI_Y2_PHY1_COMA
| #define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */ |
Definition at line 266 of file if_mskreg.h.
◆ PCI_Y2_PHY1_POWD
| #define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */ |
Definition at line 268 of file if_mskreg.h.
◆ PCI_Y2_PHY2_COMA
| #define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */ |
Definition at line 265 of file if_mskreg.h.
◆ PCI_Y2_PHY2_POWD
| #define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */ |
Definition at line 267 of file if_mskreg.h.
◆ PCI_Y2_PIG_ENA
| #define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */ |
Definition at line 263 of file if_mskreg.h.
◆ PEX_ADV_ERR_CAP_C
| #define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */ |
Definition at line 259 of file if_mskreg.h.
◆ PEX_ADV_ERR_REP
| #define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */ |
Definition at line 253 of file if_mskreg.h.
◆ PEX_CAP_ID
| #define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */ |
Definition at line 242 of file if_mskreg.h.
◆ PEX_CAP_REG
| #define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */ |
Definition at line 244 of file if_mskreg.h.
◆ PEX_COMP_TO
| #define PEX_COMP_TO BIT_14 /* Completion Timeout */ |
Definition at line 420 of file if_mskreg.h.
◆ PEX_COR_ERR_MASK
| #define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */ |
Definition at line 258 of file if_mskreg.h.
◆ PEX_COR_ERR_STAT
| #define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */ |
Definition at line 257 of file if_mskreg.h.
◆ PEX_DATA_LINK_P
| #define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */ |
Definition at line 423 of file if_mskreg.h.
◆ PEX_DB_ACCESS
| #define PEX_DB_ACCESS BIT_30 /* Access to debug register */ |
Definition at line 1051 of file if_mskreg.h.
◆ PEX_DC_EN_AUX_POW
| #define PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */ |
Definition at line 396 of file if_mskreg.h.
◆ PEX_DC_EN_COR_ER_RP
| #define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */ |
Definition at line 404 of file if_mskreg.h.
◆ PEX_DC_EN_EXT_TAG
| #define PEX_DC_EN_EXT_TAG BIT_8 /* Enable Extended Tag Field */ |
Definition at line 398 of file if_mskreg.h.
◆ PEX_DC_EN_FAT_ER_RP
| #define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */ |
Definition at line 402 of file if_mskreg.h.
◆ PEX_DC_EN_NFA_ER_RP
| #define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */ |
Definition at line 403 of file if_mskreg.h.
◆ PEX_DC_EN_NO_SNOOP
| #define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */ |
Definition at line 395 of file if_mskreg.h.
◆ PEX_DC_EN_PHANTOM
| #define PEX_DC_EN_PHANTOM BIT_9 /* Enable Phantom Functions */ |
Definition at line 397 of file if_mskreg.h.
◆ PEX_DC_EN_REL_ORD
| #define PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */ |
Definition at line 400 of file if_mskreg.h.
◆ PEX_DC_EN_UNS_RQ_RP
| #define PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */ |
Definition at line 401 of file if_mskreg.h.
◆ PEX_DC_MAX_PLS_MSK
| #define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */ |
Definition at line 399 of file if_mskreg.h.
◆ PEX_DC_MAX_RD_RQ_SIZE
| #define PEX_DC_MAX_RD_RQ_SIZE | ( | x | ) | (SHIFT12(x) & PEX_DC_MAX_RRS_MSK) |
Definition at line 406 of file if_mskreg.h.
◆ PEX_DC_MAX_RRS_MSK
| #define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */ |
Definition at line 394 of file if_mskreg.h.
◆ PEX_DEV_CAP
| #define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */ |
Definition at line 245 of file if_mskreg.h.
◆ PEX_DEV_CTRL
| #define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */ |
Definition at line 246 of file if_mskreg.h.
◆ PEX_DEV_STAT
| #define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */ |
Definition at line 247 of file if_mskreg.h.
◆ PEX_FATAL_ERRORS
| #define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P) |
Definition at line 425 of file if_mskreg.h.
◆ PEX_FLOW_CTRL_P
| #define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */ |
Definition at line 421 of file if_mskreg.h.
◆ PEX_HEADER_LOG
| #define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */ |
Definition at line 260 of file if_mskreg.h.
◆ PEX_LNK_CAP
| #define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */ |
Definition at line 248 of file if_mskreg.h.
◆ PEX_LNK_CTRL
| #define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */ |
Definition at line 249 of file if_mskreg.h.
◆ PEX_LNK_STAT
| #define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */ |
Definition at line 250 of file if_mskreg.h.
◆ PEX_LS_LINK_SP_MSK
| #define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */ |
Definition at line 413 of file if_mskreg.h.
◆ PEX_LS_LINK_TRAIN
| #define PEX_LS_LINK_TRAIN BIT_11 /* Link Training */ |
Definition at line 410 of file if_mskreg.h.
◆ PEX_LS_LINK_WI_MSK
| #define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */ |
Definition at line 412 of file if_mskreg.h.
◆ PEX_LS_SLOT_CLK_CFG
| #define PEX_LS_SLOT_CLK_CFG BIT_12 /* Slot Clock Config */ |
Definition at line 409 of file if_mskreg.h.
◆ PEX_LS_TRAIN_ERROR
| #define PEX_LS_TRAIN_ERROR BIT_10 /* Training Error */ |
Definition at line 411 of file if_mskreg.h.
◆ PEX_MALFOR_TLP
| #define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */ |
Definition at line 417 of file if_mskreg.h.
◆ PEX_NITEM
| #define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */ |
Definition at line 243 of file if_mskreg.h.
◆ PEX_POIS_TLP
| #define PEX_POIS_TLP BIT_12 /* Poisoned TLP */ |
Definition at line 422 of file if_mskreg.h.
◆ PEX_RD_ACCESS
| #define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */ |
Definition at line 1050 of file if_mskreg.h.
◆ PEX_RX_OV
| #define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */ |
Definition at line 418 of file if_mskreg.h.
◆ PEX_UNC_ERR_MASK
| #define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */ |
Definition at line 255 of file if_mskreg.h.
◆ PEX_UNC_ERR_SEV
| #define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */ |
Definition at line 256 of file if_mskreg.h.
◆ PEX_UNC_ERR_STAT
| #define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */ |
Definition at line 254 of file if_mskreg.h.
◆ PEX_UNEXP_COMP
| #define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */ |
Definition at line 419 of file if_mskreg.h.
◆ PEX_UNSUP_REQ
| #define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */ |
Definition at line 416 of file if_mskreg.h.
◆ PHY_ADDR_MARV
| #define PHY_ADDR_MARV 0 |
Definition at line 2175 of file if_mskreg.h.
◆ PHY_B_1000S_IEC
| #define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ |
Definition at line 1341 of file if_mskreg.h.
◆ PHY_B_1000S_LP_FD
| #define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ |
Definition at line 1339 of file if_mskreg.h.
◆ PHY_B_1000S_LP_HD
| #define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ |
Definition at line 1340 of file if_mskreg.h.
◆ PHY_B_1000S_LRS
| #define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ |
Definition at line 1337 of file if_mskreg.h.
◆ PHY_B_1000S_MSF
| #define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ |
Definition at line 1335 of file if_mskreg.h.
◆ PHY_B_1000S_MSR
| #define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ |
Definition at line 1336 of file if_mskreg.h.
◆ PHY_B_1000S_RRS
| #define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ |
Definition at line 1338 of file if_mskreg.h.
◆ PHY_CT_ANE
| #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ |
Definition at line 1299 of file if_mskreg.h.
◆ PHY_CT_COL_TST
| #define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */ |
Definition at line 1304 of file if_mskreg.h.
◆ PHY_CT_DUP_MD
| #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ |
Definition at line 1303 of file if_mskreg.h.
◆ PHY_CT_ISOL
| #define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */ |
Definition at line 1301 of file if_mskreg.h.
◆ PHY_CT_LOOP
| #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ |
Definition at line 1297 of file if_mskreg.h.
◆ PHY_CT_PDOWN
| #define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */ |
Definition at line 1300 of file if_mskreg.h.
◆ PHY_CT_RE_CFG
| #define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ |
Definition at line 1302 of file if_mskreg.h.
◆ PHY_CT_RESET
| #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ |
Definition at line 1296 of file if_mskreg.h.
◆ PHY_CT_SP10
| #define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */ |
Definition at line 1309 of file if_mskreg.h.
◆ PHY_CT_SP100
| #define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */ |
Definition at line 1308 of file if_mskreg.h.
◆ PHY_CT_SP1000
| #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ |
Definition at line 1307 of file if_mskreg.h.
◆ PHY_CT_SPS_LSB
| #define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */ |
Definition at line 1298 of file if_mskreg.h.
◆ PHY_CT_SPS_MSB
| #define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */ |
Definition at line 1305 of file if_mskreg.h.
◆ PHY_I1_MOD_NUM
| #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ |
Definition at line 1321 of file if_mskreg.h.
◆ PHY_I1_OUI_MSK
| #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ |
Definition at line 1320 of file if_mskreg.h.
◆ PHY_I1_REV_MSK
| #define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */ |
Definition at line 1322 of file if_mskreg.h.
◆ PHY_M_1000C_AFD
| #define PHY_M_1000C_AFD BIT_9 /* Advertise Full Duplex */ |
Definition at line 1374 of file if_mskreg.h.
◆ PHY_M_1000C_AHD
| #define PHY_M_1000C_AHD BIT_8 /* Advertise Half Duplex */ |
Definition at line 1375 of file if_mskreg.h.
◆ PHY_M_1000C_MPD
| #define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */ |
Definition at line 1373 of file if_mskreg.h.
◆ PHY_M_1000C_MSC
| #define PHY_M_1000C_MSC BIT_11 /* M/S Configuration (1=Master) */ |
Definition at line 1372 of file if_mskreg.h.
◆ PHY_M_1000C_MSE
| #define PHY_M_1000C_MSE BIT_12 /* Manual Master/Slave Enable */ |
Definition at line 1371 of file if_mskreg.h.
◆ PHY_M_1000C_TEST
| #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ |
Definition at line 1370 of file if_mskreg.h.
◆ PHY_M_AN_1000X_AFD
| #define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ |
Definition at line 1361 of file if_mskreg.h.
◆ PHY_M_AN_1000X_AHD
| #define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ |
Definition at line 1360 of file if_mskreg.h.
◆ PHY_M_AN_100_FD
| #define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ |
Definition at line 1351 of file if_mskreg.h.
◆ PHY_M_AN_100_HD
| #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ |
Definition at line 1352 of file if_mskreg.h.
◆ PHY_M_AN_100_T4
| #define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */ |
Definition at line 1350 of file if_mskreg.h.
◆ PHY_M_AN_10_FD
| #define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ |
Definition at line 1353 of file if_mskreg.h.
◆ PHY_M_AN_10_HD
| #define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ |
Definition at line 1354 of file if_mskreg.h.
◆ PHY_M_AN_ACK
| #define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ |
Definition at line 1346 of file if_mskreg.h.
◆ PHY_M_AN_ASP
| #define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ |
Definition at line 1348 of file if_mskreg.h.
◆ PHY_M_AN_ASP_X
| #define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ |
Definition at line 1358 of file if_mskreg.h.
◆ PHY_M_AN_NXT_PG
| #define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ |
Definition at line 1345 of file if_mskreg.h.
◆ PHY_M_AN_PC
| #define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ |
Definition at line 1349 of file if_mskreg.h.
◆ PHY_M_AN_PC_X
| #define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ |
Definition at line 1359 of file if_mskreg.h.
◆ PHY_M_AN_RF
| #define PHY_M_AN_RF BIT_13 /* Remote Fault */ |
Definition at line 1347 of file if_mskreg.h.
◆ PHY_M_AN_SEL_MSK
| #define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */ |
Definition at line 1355 of file if_mskreg.h.
◆ PHY_M_CABD_AMPL_MSK
| #define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */ |
Definition at line 1574 of file if_mskreg.h.
◆ PHY_M_CABD_DIS_WAIT
| #define PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */ |
Definition at line 1571 of file if_mskreg.h.
◆ PHY_M_CABD_DIST_MSK
| #define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */ |
Definition at line 1576 of file if_mskreg.h.
◆ PHY_M_CABD_ENA_TEST
| #define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */ |
Definition at line 1570 of file if_mskreg.h.
◆ PHY_M_CABD_STAT_MSK
| #define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */ |
Definition at line 1573 of file if_mskreg.h.
◆ PHY_M_DEF_MSK
| #define PHY_M_DEF_MSK |
Definition at line 1463 of file if_mskreg.h.
◆ PHY_M_DIS_AUT_MED
| #define PHY_M_DIS_AUT_MED BIT_9 /* Disable Aut. Medium Reg. Selection */ |
Definition at line 1563 of file if_mskreg.h.
◆ PHY_M_DTE_POW_STAT
| #define PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */ |
Definition at line 1566 of file if_mskreg.h.
◆ PHY_M_EC2_FI_IMPED
| #define PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */ |
Definition at line 1550 of file if_mskreg.h.
◆ PHY_M_EC2_FO_AM_MSK
| #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ |
Definition at line 1554 of file if_mskreg.h.
◆ PHY_M_EC2_FO_BOOST
| #define PHY_M_EC2_FO_BOOST BIT_3 /* Fiber Output Boost */ |
Definition at line 1553 of file if_mskreg.h.
◆ PHY_M_EC2_FO_IMPED
| #define PHY_M_EC2_FO_IMPED BIT_5 /* Fiber Output Impedance */ |
Definition at line 1551 of file if_mskreg.h.
◆ PHY_M_EC2_FO_M_CLK
| #define PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */ |
Definition at line 1552 of file if_mskreg.h.
◆ PHY_M_EC_DIS_LINK_P
| #define PHY_M_EC_DIS_LINK_P BIT_12 /* Disable Link Pulses (88E1111 only) */ |
Definition at line 1469 of file if_mskreg.h.
◆ PHY_M_EC_DOWN_S_ENA
| #define PHY_M_EC_DOWN_S_ENA BIT_8 /* Downshift Enable (88E1111 only) */ |
Definition at line 1476 of file if_mskreg.h.
◆ PHY_M_EC_DSC_2
| #define PHY_M_EC_DSC_2 | ( | x | ) | (SHIFT9(x) & PHY_M_EC_DSC_MSK_2) |
Definition at line 1492 of file if_mskreg.h.
◆ PHY_M_EC_DSC_MSK_2
| #define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */ |
Definition at line 1474 of file if_mskreg.h.
◆ PHY_M_EC_DTE_D_ENA
| #define PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */ |
Definition at line 1481 of file if_mskreg.h.
◆ PHY_M_EC_ENA_BC_EXT
| #define PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */ |
Definition at line 1467 of file if_mskreg.h.
◆ PHY_M_EC_ENA_LIN_LB
| #define PHY_M_EC_ENA_LIN_LB BIT_14 /* Enable Line Loopback (88E1111 only) */ |
Definition at line 1468 of file if_mskreg.h.
◆ PHY_M_EC_FIB_AN_ENA
| #define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */ |
Definition at line 1480 of file if_mskreg.h.
◆ PHY_M_EC_M_DSC
| #define PHY_M_EC_M_DSC | ( | x | ) | (SHIFT10(x) & PHY_M_EC_M_DSC_MSK) |
Definition at line 1485 of file if_mskreg.h.
◆ PHY_M_EC_M_DSC_MSK
| #define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */ |
Definition at line 1470 of file if_mskreg.h.
◆ PHY_M_EC_MAC_S
| #define PHY_M_EC_MAC_S | ( | x | ) | (SHIFT4(x) & PHY_M_EC_MAC_S_MSK) |
Definition at line 1489 of file if_mskreg.h.
◆ PHY_M_EC_MAC_S_MSK
| #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ |
Definition at line 1479 of file if_mskreg.h.
◆ PHY_M_EC_RX_TIM_CT
| #define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/ |
Definition at line 1478 of file if_mskreg.h.
◆ PHY_M_EC_S_DSC
| #define PHY_M_EC_S_DSC | ( | x | ) | (SHIFT8(x) & PHY_M_EC_S_DSC_MSK) |
Definition at line 1487 of file if_mskreg.h.
◆ PHY_M_EC_S_DSC_MSK
| #define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */ |
Definition at line 1472 of file if_mskreg.h.
◆ PHY_M_EC_TRANS_DIS
| #define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */ |
Definition at line 1483 of file if_mskreg.h.
◆ PHY_M_EC_TX_TIM_CT
| #define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */ |
Definition at line 1482 of file if_mskreg.h.
◆ PHY_M_FC_AN_REG_ACC
| #define PHY_M_FC_AN_REG_ACC BIT_14 /* Fiber/Copper AN Reg. Access */ |
Definition at line 1558 of file if_mskreg.h.
◆ PHY_M_FC_AUTO_SEL
| #define PHY_M_FC_AUTO_SEL BIT_15 /* Fiber/Copper Auto Sel. Dis. */ |
Definition at line 1557 of file if_mskreg.h.
◆ PHY_M_FC_RESOLUTION
| #define PHY_M_FC_RESOLUTION BIT_13 /* Fiber/Copper Resolution */ |
Definition at line 1559 of file if_mskreg.h.
◆ PHY_M_FELP_LED0_CTRL
| #define PHY_M_FELP_LED0_CTRL | ( | x | ) | (SHIFT0(x) & PHY_M_FELP_LED0_MSK) |
Definition at line 1592 of file if_mskreg.h.
◆ PHY_M_FELP_LED0_MSK
| #define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */ |
Definition at line 1588 of file if_mskreg.h.
◆ PHY_M_FELP_LED1_CTRL
| #define PHY_M_FELP_LED1_CTRL | ( | x | ) | (SHIFT4(x) & PHY_M_FELP_LED1_MSK) |
Definition at line 1591 of file if_mskreg.h.
◆ PHY_M_FELP_LED1_MSK
| #define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */ |
Definition at line 1587 of file if_mskreg.h.
◆ PHY_M_FELP_LED2_CTRL
| #define PHY_M_FELP_LED2_CTRL | ( | x | ) | (SHIFT8(x) & PHY_M_FELP_LED2_MSK) |
Definition at line 1590 of file if_mskreg.h.
◆ PHY_M_FELP_LED2_MSK
| #define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */ |
Definition at line 1586 of file if_mskreg.h.
◆ PHY_M_FESC_DIS_WAIT
| #define PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */ |
Definition at line 1612 of file if_mskreg.h.
◆ PHY_M_FESC_ENA_MCLK
| #define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */ |
Definition at line 1613 of file if_mskreg.h.
◆ PHY_M_FESC_SEL_CL_A
| #define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */ |
Definition at line 1614 of file if_mskreg.h.
◆ PHY_M_FIB_FORCE_LNK
| #define PHY_M_FIB_FORCE_LNK BIT_10 /* Force Link Good */ |
Definition at line 1618 of file if_mskreg.h.
◆ PHY_M_FIB_SIGD_POL
| #define PHY_M_FIB_SIGD_POL BIT_9 /* SIGDET Polarity */ |
Definition at line 1619 of file if_mskreg.h.
◆ PHY_M_FIB_TX_DIS
| #define PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */ |
Definition at line 1620 of file if_mskreg.h.
◆ PHY_M_IRQ_POLARITY
| #define PHY_M_IRQ_POLARITY BIT_10 /* IRQ polarity */ |
Definition at line 1562 of file if_mskreg.h.
◆ PHY_M_IS_AN_COMPL
| #define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */ |
Definition at line 1451 of file if_mskreg.h.
◆ PHY_M_IS_AN_ERROR
| #define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */ |
Definition at line 1447 of file if_mskreg.h.
◆ PHY_M_IS_AN_PR
| #define PHY_M_IS_AN_PR BIT_12 /* Page Received */ |
Definition at line 1450 of file if_mskreg.h.
◆ PHY_M_IS_DOWNSH_DET
| #define PHY_M_IS_DOWNSH_DET BIT_5 /* Downshift Detected */ |
Definition at line 1457 of file if_mskreg.h.
◆ PHY_M_IS_DTE_CHANGE
| #define PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */ |
Definition at line 1459 of file if_mskreg.h.
◆ PHY_M_IS_DUP_CHANGE
| #define PHY_M_IS_DUP_CHANGE BIT_13 /* Duplex Mode Changed */ |
Definition at line 1449 of file if_mskreg.h.
◆ PHY_M_IS_END_CHANGE
| #define PHY_M_IS_END_CHANGE BIT_4 /* Energy Detect Changed */ |
Definition at line 1458 of file if_mskreg.h.
◆ PHY_M_IS_FALSE_CARR
| #define PHY_M_IS_FALSE_CARR BIT_8 /* False Carrier */ |
Definition at line 1454 of file if_mskreg.h.
◆ PHY_M_IS_FIFO_ERROR
| #define PHY_M_IS_FIFO_ERROR BIT_7 /* FIFO Overflow/Underrun Error */ |
Definition at line 1455 of file if_mskreg.h.
◆ PHY_M_IS_JABBER
| #define PHY_M_IS_JABBER BIT_0 /* Jabber */ |
Definition at line 1461 of file if_mskreg.h.
◆ PHY_M_IS_LSP_CHANGE
| #define PHY_M_IS_LSP_CHANGE BIT_14 /* Link Speed Changed */ |
Definition at line 1448 of file if_mskreg.h.
◆ PHY_M_IS_LST_CHANGE
| #define PHY_M_IS_LST_CHANGE BIT_10 /* Link Status Changed */ |
Definition at line 1452 of file if_mskreg.h.
◆ PHY_M_IS_MDI_CHANGE
| #define PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */ |
Definition at line 1456 of file if_mskreg.h.
◆ PHY_M_IS_POL_CHANGE
| #define PHY_M_IS_POL_CHANGE BIT_1 /* Polarity Changed */ |
Definition at line 1460 of file if_mskreg.h.
◆ PHY_M_IS_SYMB_ERROR
| #define PHY_M_IS_SYMB_ERROR BIT_9 /* Symbol Error */ |
Definition at line 1453 of file if_mskreg.h.
◆ PHY_M_LED_BLINK_RT
| #define PHY_M_LED_BLINK_RT | ( | x | ) | (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK) |
Definition at line 1527 of file if_mskreg.h.
◆ PHY_M_LED_MO_10
| #define PHY_M_LED_MO_10 | ( | x | ) | SHIFT8(x) /* Bit 9.. 8: Link 10 */ |
Definition at line 1538 of file if_mskreg.h.
◆ PHY_M_LED_MO_100
| #define PHY_M_LED_MO_100 | ( | x | ) | SHIFT6(x) /* Bit 7.. 6: Link 100 */ |
Definition at line 1539 of file if_mskreg.h.
◆ PHY_M_LED_MO_1000
| #define PHY_M_LED_MO_1000 | ( | x | ) | SHIFT4(x) /* Bit 5.. 4: Link 1000 */ |
Definition at line 1540 of file if_mskreg.h.
◆ PHY_M_LED_MO_DUP
| #define PHY_M_LED_MO_DUP | ( | x | ) | SHIFT10(x) /* Bit 11..10: Duplex */ |
Definition at line 1537 of file if_mskreg.h.
◆ PHY_M_LED_MO_RX
| #define PHY_M_LED_MO_RX | ( | x | ) | SHIFT2(x) /* Bit 3.. 2: Rx */ |
Definition at line 1541 of file if_mskreg.h.
◆ PHY_M_LED_MO_SGMII
| #define PHY_M_LED_MO_SGMII | ( | x | ) | SHIFT14(x) /* Bit 15..14: SGMII AN Timer */ |
Definition at line 1536 of file if_mskreg.h.
◆ PHY_M_LED_MO_TX
| #define PHY_M_LED_MO_TX | ( | x | ) | SHIFT0(x) /* Bit 1.. 0: Tx */ |
Definition at line 1542 of file if_mskreg.h.
◆ PHY_M_LED_PULS_DUR
| #define PHY_M_LED_PULS_DUR | ( | x | ) | (SHIFT12(x) & PHY_M_LEDC_PULS_MSK) |
Definition at line 1516 of file if_mskreg.h.
◆ PHY_M_LEDC_BL_R_MSK
| #define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ |
Definition at line 1503 of file if_mskreg.h.
◆ PHY_M_LEDC_DIS_LED
| #define PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */ |
Definition at line 1500 of file if_mskreg.h.
◆ PHY_M_LEDC_DP_C_LSB
| #define PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */ |
Definition at line 1504 of file if_mskreg.h.
◆ PHY_M_LEDC_DP_C_MSB
| #define PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */ |
Definition at line 1511 of file if_mskreg.h.
◆ PHY_M_LEDC_DP_CTRL
| #define PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */ |
Definition at line 1510 of file if_mskreg.h.
◆ PHY_M_LEDC_F_INT
| #define PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */ |
Definition at line 1502 of file if_mskreg.h.
◆ PHY_M_LEDC_INIT_CTRL
| #define PHY_M_LEDC_INIT_CTRL | ( | x | ) | (SHIFT8(x) & PHY_M_LEDC_INIT_MSK) |
Definition at line 1636 of file if_mskreg.h.
◆ PHY_M_LEDC_INIT_MSK
| #define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */ |
Definition at line 1631 of file if_mskreg.h.
◆ PHY_M_LEDC_LINK_MSK
| #define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ |
Definition at line 1508 of file if_mskreg.h.
◆ PHY_M_LEDC_LK_C_MSK
| #define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */ |
Definition at line 1506 of file if_mskreg.h.
◆ PHY_M_LEDC_LOS_CTRL
| #define PHY_M_LEDC_LOS_CTRL | ( | x | ) | (SHIFT12(x) & PHY_M_LEDC_LOS_MSK) |
Definition at line 1635 of file if_mskreg.h.
◆ PHY_M_LEDC_LOS_MSK
| #define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */ |
Definition at line 1630 of file if_mskreg.h.
◆ PHY_M_LEDC_PULS_MSK
| #define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ |
Definition at line 1501 of file if_mskreg.h.
◆ PHY_M_LEDC_RX_CTRL
| #define PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */ |
Definition at line 1512 of file if_mskreg.h.
◆ PHY_M_LEDC_STA0_CTRL
| #define PHY_M_LEDC_STA0_CTRL | ( | x | ) | (SHIFT0(x) & PHY_M_LEDC_STA0_MSK) |
Definition at line 1638 of file if_mskreg.h.
◆ PHY_M_LEDC_STA0_MSK
| #define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ |
Definition at line 1633 of file if_mskreg.h.
◆ PHY_M_LEDC_STA1_CTRL
| #define PHY_M_LEDC_STA1_CTRL | ( | x | ) | (SHIFT4(x) & PHY_M_LEDC_STA1_MSK) |
Definition at line 1637 of file if_mskreg.h.
◆ PHY_M_LEDC_STA1_MSK
| #define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */ |
Definition at line 1632 of file if_mskreg.h.
◆ PHY_M_LEDC_TX_C_LSB
| #define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */ |
Definition at line 1505 of file if_mskreg.h.
◆ PHY_M_LEDC_TX_C_MSB
| #define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */ |
Definition at line 1514 of file if_mskreg.h.
◆ PHY_M_LEDC_TX_CTRL
| #define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */ |
Definition at line 1513 of file if_mskreg.h.
◆ PHY_M_MAC_MD_1000BX
| #define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */ |
Definition at line 1626 of file if_mskreg.h.
◆ PHY_M_MAC_MD_AUTO
| #define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */ |
Definition at line 1624 of file if_mskreg.h.
◆ PHY_M_MAC_MD_COPPER
| #define PHY_M_MAC_MD_COPPER 5 /* Copper only */ |
Definition at line 1625 of file if_mskreg.h.
◆ PHY_M_MAC_MD_MSK
| #define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */ |
Definition at line 1623 of file if_mskreg.h.
◆ PHY_M_MAC_MODE_SEL
| #define PHY_M_MAC_MODE_SEL | ( | x | ) | (SHIFT7(x) & PHY_M_MAC_MD_MSK) |
Definition at line 1627 of file if_mskreg.h.
◆ PHY_M_MODE_MASK
| #define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ |
Definition at line 1567 of file if_mskreg.h.
◆ PHY_M_P_ASYM_MD_X
| #define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */ |
Definition at line 1366 of file if_mskreg.h.
◆ PHY_M_P_BOTH_MD_X
| #define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */ |
Definition at line 1367 of file if_mskreg.h.
◆ PHY_M_P_NO_PAUSE_X
| #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ |
Definition at line 1364 of file if_mskreg.h.
◆ PHY_M_P_SYM_MD_X
| #define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */ |
Definition at line 1365 of file if_mskreg.h.
◆ PHY_M_PC_ASS_CRS_TX
| #define PHY_M_PC_ASS_CRS_TX BIT_11 /* Assert CRS on Transmit */ |
Definition at line 1380 of file if_mskreg.h.
◆ PHY_M_PC_DIS_125CLK
| #define PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */ |
Definition at line 1385 of file if_mskreg.h.
◆ PHY_M_PC_DIS_FEFI
| #define PHY_M_PC_DIS_FEFI BIT_8 /* Disable Far End Fault Indic. (FEFI) */ |
Definition at line 1417 of file if_mskreg.h.
◆ PHY_M_PC_DIS_JABBER
| #define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */ |
Definition at line 1389 of file if_mskreg.h.
◆ PHY_M_PC_DIS_LINK_P
| #define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */ |
Definition at line 1401 of file if_mskreg.h.
◆ PHY_M_PC_DIS_NLP_CK
| #define PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */ |
Definition at line 1413 of file if_mskreg.h.
◆ PHY_M_PC_DIS_NLP_GN
| #define PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */ |
Definition at line 1415 of file if_mskreg.h.
◆ PHY_M_PC_DIS_SCRAMB
| #define PHY_M_PC_DIS_SCRAMB BIT_9 /* Disable Scrambler */ |
Definition at line 1416 of file if_mskreg.h.
◆ PHY_M_PC_DOWN_S_ENA
| #define PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */ |
Definition at line 1403 of file if_mskreg.h.
◆ PHY_M_PC_DSC
| #define PHY_M_PC_DSC | ( | x | ) | (SHIFT12(x) & PHY_M_PC_DSC_MSK) |
Definition at line 1406 of file if_mskreg.h.
◆ PHY_M_PC_DSC_MSK
| #define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */ |
Definition at line 1402 of file if_mskreg.h.
◆ PHY_M_PC_EN_DET
| #define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */ |
Definition at line 1391 of file if_mskreg.h.
◆ PHY_M_PC_EN_DET_MSK
| #define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ |
Definition at line 1382 of file if_mskreg.h.
◆ PHY_M_PC_EN_DET_PLUS
| #define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */ |
Definition at line 1392 of file if_mskreg.h.
◆ PHY_M_PC_ENA_AUTO
| #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ |
Definition at line 1398 of file if_mskreg.h.
◆ PHY_M_PC_ENA_DTE_DT
| #define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */ |
Definition at line 1411 of file if_mskreg.h.
◆ PHY_M_PC_ENA_ENE_DT
| #define PHY_M_PC_ENA_ENE_DT BIT_14 /* Enable Energy Detect (sense & pulse) */ |
Definition at line 1412 of file if_mskreg.h.
◆ PHY_M_PC_ENA_EXT_D
| #define PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */ |
Definition at line 1383 of file if_mskreg.h.
◆ PHY_M_PC_ENA_LIP_NP
| #define PHY_M_PC_ENA_LIP_NP BIT_12 /* Enable Link Partner Next Page Reg. */ |
Definition at line 1414 of file if_mskreg.h.
◆ PHY_M_PC_FL_GOOD
| #define PHY_M_PC_FL_GOOD BIT_10 /* Force Link Good */ |
Definition at line 1381 of file if_mskreg.h.
◆ PHY_M_PC_MAC_POW_UP
| #define PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */ |
Definition at line 1386 of file if_mskreg.h.
◆ PHY_M_PC_MAN_MDI
| #define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ |
Definition at line 1396 of file if_mskreg.h.
◆ PHY_M_PC_MAN_MDIX
| #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ |
Definition at line 1397 of file if_mskreg.h.
◆ PHY_M_PC_MDI_XMODE
| #define PHY_M_PC_MDI_XMODE | ( | x | ) | (SHIFT5(x) & PHY_M_PC_MDIX_MSK) |
Definition at line 1394 of file if_mskreg.h.
◆ PHY_M_PC_MDIX_MSK
| #define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ |
Definition at line 1384 of file if_mskreg.h.
◆ PHY_M_PC_POL_R_DIS
| #define PHY_M_PC_POL_R_DIS BIT_1 /* Polarity Reversal Disabled */ |
Definition at line 1388 of file if_mskreg.h.
◆ PHY_M_PC_RX_FD_MSK
| #define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */ |
Definition at line 1419 of file if_mskreg.h.
◆ PHY_M_PC_RX_FFD_MSK
| #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ |
Definition at line 1379 of file if_mskreg.h.
◆ PHY_M_PC_SH_TP_SEL
| #define PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */ |
Definition at line 1418 of file if_mskreg.h.
◆ PHY_M_PC_SQE_T_ENA
| #define PHY_M_PC_SQE_T_ENA BIT_2 /* SQE Test Enabled */ |
Definition at line 1387 of file if_mskreg.h.
◆ PHY_M_PC_TX_FFD_MSK
| #define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ |
Definition at line 1378 of file if_mskreg.h.
◆ PHY_M_POLC_INIT_CTRL
| #define PHY_M_POLC_INIT_CTRL | ( | x | ) | (SHIFT4(x) & PHY_M_POLC_INIT_MSK) |
Definition at line 1651 of file if_mskreg.h.
◆ PHY_M_POLC_INIT_MSK
| #define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ |
Definition at line 1644 of file if_mskreg.h.
◆ PHY_M_POLC_IS0_P_MIX
| #define PHY_M_POLC_IS0_P_MIX | ( | x | ) | (SHIFT8(x) & PHY_M_POLC_IS0M_MSK) |
Definition at line 1649 of file if_mskreg.h.
◆ PHY_M_POLC_IS0M_MSK
| #define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ |
Definition at line 1642 of file if_mskreg.h.
◆ PHY_M_POLC_LOS_CTRL
| #define PHY_M_POLC_LOS_CTRL | ( | x | ) | (SHIFT6(x) & PHY_M_POLC_LOS_MSK) |
Definition at line 1650 of file if_mskreg.h.
◆ PHY_M_POLC_LOS_MSK
| #define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ |
Definition at line 1643 of file if_mskreg.h.
◆ PHY_M_POLC_LS1_P_MIX
| #define PHY_M_POLC_LS1_P_MIX | ( | x | ) | (SHIFT12(x) & PHY_M_POLC_LS1M_MSK) |
Definition at line 1648 of file if_mskreg.h.
◆ PHY_M_POLC_LS1M_MSK
| #define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */ |
Definition at line 1641 of file if_mskreg.h.
◆ PHY_M_POLC_STA0_CTRL
| #define PHY_M_POLC_STA0_CTRL | ( | x | ) | (SHIFT0(x) & PHY_M_POLC_STA0_MSK) |
Definition at line 1653 of file if_mskreg.h.
◆ PHY_M_POLC_STA0_MSK
| #define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ |
Definition at line 1646 of file if_mskreg.h.
◆ PHY_M_POLC_STA1_CTRL
| #define PHY_M_POLC_STA1_CTRL | ( | x | ) | (SHIFT2(x) & PHY_M_POLC_STA1_MSK) |
Definition at line 1652 of file if_mskreg.h.
◆ PHY_M_POLC_STA1_MSK
| #define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ |
Definition at line 1645 of file if_mskreg.h.
◆ PHY_M_PS_CABLE_MSK
| #define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */ |
Definition at line 1430 of file if_mskreg.h.
◆ PHY_M_PS_DOWNS_STAT
| #define PHY_M_PS_DOWNS_STAT BIT_5 /* Downshift Status (1=downsh.) */ |
Definition at line 1432 of file if_mskreg.h.
◆ PHY_M_PS_DTE_DETECT
| #define PHY_M_PS_DTE_DETECT BIT_15 /* Data Terminal Equipment (DTE) Detected */ |
Definition at line 1442 of file if_mskreg.h.
◆ PHY_M_PS_ENDET_STAT
| #define PHY_M_PS_ENDET_STAT BIT_4 /* Energy Detect Status (1=act) */ |
Definition at line 1433 of file if_mskreg.h.
◆ PHY_M_PS_FULL_DUP
| #define PHY_M_PS_FULL_DUP BIT_13 /* Full Duplex */ |
Definition at line 1426 of file if_mskreg.h.
◆ PHY_M_PS_JABBER
| #define PHY_M_PS_JABBER BIT_0 /* Jabber */ |
Definition at line 1437 of file if_mskreg.h.
◆ PHY_M_PS_LINK_UP
| #define PHY_M_PS_LINK_UP BIT_10 /* Link Up */ |
Definition at line 1429 of file if_mskreg.h.
◆ PHY_M_PS_MDI_X_STAT
| #define PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */ |
Definition at line 1431 of file if_mskreg.h.
◆ PHY_M_PS_PAGE_REC
| #define PHY_M_PS_PAGE_REC BIT_12 /* Page Received */ |
Definition at line 1427 of file if_mskreg.h.
◆ PHY_M_PS_PAUSE_MSK
| #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) |
Definition at line 1439 of file if_mskreg.h.
◆ PHY_M_PS_POL_REV
| #define PHY_M_PS_POL_REV BIT_1 /* Polarity Reversed */ |
Definition at line 1436 of file if_mskreg.h.
◆ PHY_M_PS_RES_SPEED
| #define PHY_M_PS_RES_SPEED BIT_14 /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ |
Definition at line 1443 of file if_mskreg.h.
◆ PHY_M_PS_RX_P_EN
| #define PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */ |
Definition at line 1435 of file if_mskreg.h.
◆ PHY_M_PS_SPDUP_RES
| #define PHY_M_PS_SPDUP_RES BIT_11 /* Speed & Duplex Resolved */ |
Definition at line 1428 of file if_mskreg.h.
◆ PHY_M_PS_SPEED_10
| #define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ |
Definition at line 1425 of file if_mskreg.h.
◆ PHY_M_PS_SPEED_100
| #define PHY_M_PS_SPEED_100 BIT_14 /* 01 = 100 Mbps */ |
Definition at line 1424 of file if_mskreg.h.
◆ PHY_M_PS_SPEED_1000
| #define PHY_M_PS_SPEED_1000 BIT_15 /* 10 = 1000 Mbps */ |
Definition at line 1423 of file if_mskreg.h.
◆ PHY_M_PS_SPEED_MSK
| #define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ |
Definition at line 1422 of file if_mskreg.h.
◆ PHY_M_PS_TX_P_EN
| #define PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */ |
Definition at line 1434 of file if_mskreg.h.
◆ PHY_M_SER_IF_AN_BP
| #define PHY_M_SER_IF_AN_BP BIT_12 /* Ser. IF AN Bypass Enable */ |
Definition at line 1560 of file if_mskreg.h.
◆ PHY_M_SER_IF_BP_ST
| #define PHY_M_SER_IF_BP_ST BIT_11 /* Ser. IF AN Bypass Status */ |
Definition at line 1561 of file if_mskreg.h.
◆ PHY_M_UNDOC1
| #define PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */ |
Definition at line 1565 of file if_mskreg.h.
◆ PHY_MARV_1000T_CTRL
| #define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ |
Definition at line 1269 of file if_mskreg.h.
◆ PHY_MARV_1000T_STAT
| #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ |
Definition at line 1270 of file if_mskreg.h.
◆ PHY_MARV_AUNE_ADV
| #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ |
Definition at line 1263 of file if_mskreg.h.
◆ PHY_MARV_AUNE_EXP
| #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ |
Definition at line 1265 of file if_mskreg.h.
◆ PHY_MARV_AUNE_LP
| #define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ |
Definition at line 1264 of file if_mskreg.h.
◆ PHY_MARV_CABLE_DIAG
| #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ |
Definition at line 1285 of file if_mskreg.h.
◆ PHY_MARV_CTRL
| #define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */ |
Definition at line 1259 of file if_mskreg.h.
◆ PHY_MARV_EXT_ADR
| #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ |
Definition at line 1279 of file if_mskreg.h.
◆ PHY_MARV_EXT_CTRL
| #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ |
Definition at line 1277 of file if_mskreg.h.
◆ PHY_MARV_EXT_CTRL_2
| #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ |
Definition at line 1283 of file if_mskreg.h.
◆ PHY_MARV_EXT_P_STAT
| #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ |
Definition at line 1284 of file if_mskreg.h.
◆ PHY_MARV_EXT_STAT
| #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ |
Definition at line 1272 of file if_mskreg.h.
◆ PHY_MARV_FE_LED_PAR
| #define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */ |
Definition at line 1290 of file if_mskreg.h.
◆ PHY_MARV_FE_LED_SER
| #define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */ |
Definition at line 1291 of file if_mskreg.h.
◆ PHY_MARV_FE_SPEC_2
| #define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */ |
Definition at line 1294 of file if_mskreg.h.
◆ PHY_MARV_FE_VCT_RX
| #define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */ |
Definition at line 1293 of file if_mskreg.h.
◆ PHY_MARV_FE_VCT_TX
| #define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */ |
Definition at line 1292 of file if_mskreg.h.
◆ PHY_MARV_ID0
| #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ |
Definition at line 1261 of file if_mskreg.h.
◆ PHY_MARV_ID0_VAL
| #define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */ |
Definition at line 1325 of file if_mskreg.h.
◆ PHY_MARV_ID1
| #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ |
Definition at line 1262 of file if_mskreg.h.
◆ PHY_MARV_ID1_B0
| #define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1011) */ |
Definition at line 1327 of file if_mskreg.h.
◆ PHY_MARV_ID1_B2
| #define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */ |
Definition at line 1328 of file if_mskreg.h.
◆ PHY_MARV_ID1_C2
| #define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */ |
Definition at line 1329 of file if_mskreg.h.
◆ PHY_MARV_ID1_ECU
| #define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */ |
Definition at line 1332 of file if_mskreg.h.
◆ PHY_MARV_ID1_FE
| #define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */ |
Definition at line 1331 of file if_mskreg.h.
◆ PHY_MARV_ID1_Y2
| #define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */ |
Definition at line 1330 of file if_mskreg.h.
◆ PHY_MARV_INT_MASK
| #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ |
Definition at line 1275 of file if_mskreg.h.
◆ PHY_MARV_INT_STAT
| #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ |
Definition at line 1276 of file if_mskreg.h.
◆ PHY_MARV_LED_CTRL
| #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ |
Definition at line 1281 of file if_mskreg.h.
◆ PHY_MARV_LED_OVER
| #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ |
Definition at line 1282 of file if_mskreg.h.
◆ PHY_MARV_NEPG
| #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ |
Definition at line 1266 of file if_mskreg.h.
◆ PHY_MARV_NEPG_LP
| #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ |
Definition at line 1267 of file if_mskreg.h.
◆ PHY_MARV_PAGE_ADDR
| #define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */ |
Definition at line 1286 of file if_mskreg.h.
◆ PHY_MARV_PAGE_DATA
| #define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */ |
Definition at line 1287 of file if_mskreg.h.
◆ PHY_MARV_PHY_CTRL
| #define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */ |
Definition at line 1273 of file if_mskreg.h.
◆ PHY_MARV_PHY_STAT
| #define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */ |
Definition at line 1274 of file if_mskreg.h.
◆ PHY_MARV_PORT_IRQ
| #define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */ |
Definition at line 1280 of file if_mskreg.h.
◆ PHY_MARV_RXE_CNT
| #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ |
Definition at line 1278 of file if_mskreg.h.
◆ PHY_MARV_STAT
| #define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */ |
Definition at line 1260 of file if_mskreg.h.
◆ PHY_ST_AN_CAP
| #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ |
Definition at line 1315 of file if_mskreg.h.
◆ PHY_ST_AN_OVER
| #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ |
Definition at line 1313 of file if_mskreg.h.
◆ PHY_ST_EXT_REG
| #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ |
Definition at line 1318 of file if_mskreg.h.
◆ PHY_ST_EXT_ST
| #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ |
Definition at line 1311 of file if_mskreg.h.
◆ PHY_ST_JAB_DET
| #define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */ |
Definition at line 1317 of file if_mskreg.h.
◆ PHY_ST_LSYNC
| #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ |
Definition at line 1316 of file if_mskreg.h.
◆ PHY_ST_PRE_SUP
| #define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */ |
Definition at line 1312 of file if_mskreg.h.
◆ PHY_ST_REM_FLT
| #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occurred */ |
Definition at line 1314 of file if_mskreg.h.
◆ POLL_CTRL
| #define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */ |
Definition at line 680 of file if_mskreg.h.
◆ POLL_LAST_IDX
| #define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */ |
Definition at line 681 of file if_mskreg.h.
◆ POLL_LIST_ADDR_HI
| #define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */ |
Definition at line 683 of file if_mskreg.h.
◆ POLL_LIST_ADDR_LO
| #define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */ |
Definition at line 682 of file if_mskreg.h.
◆ PREF_UNIT_ADDR_HI_REG
| #define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/ |
Definition at line 589 of file if_mskreg.h.
◆ PREF_UNIT_ADDR_LOW_REG
| #define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */ |
Definition at line 588 of file if_mskreg.h.
◆ PREF_UNIT_CTRL_REG
| #define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */ |
Definition at line 586 of file if_mskreg.h.
◆ PREF_UNIT_FIFO_LEV_REG
| #define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */ |
Definition at line 595 of file if_mskreg.h.
◆ PREF_UNIT_FIFO_RP_REG
| #define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */ |
Definition at line 593 of file if_mskreg.h.
◆ PREF_UNIT_FIFO_WM_REG
| #define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */ |
Definition at line 594 of file if_mskreg.h.
◆ PREF_UNIT_FIFO_WP_REG
| #define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */ |
Definition at line 592 of file if_mskreg.h.
◆ PREF_UNIT_GET_IDX_REG
| #define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */ |
Definition at line 590 of file if_mskreg.h.
◆ PREF_UNIT_LAST_IDX_REG
| #define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */ |
Definition at line 587 of file if_mskreg.h.
◆ PREF_UNIT_MASK_IDX
| #define PREF_UNIT_MASK_IDX 0x0fff |
Definition at line 597 of file if_mskreg.h.
◆ PREF_UNIT_OP_OFF
| #define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */ |
Definition at line 1144 of file if_mskreg.h.
◆ PREF_UNIT_OP_ON
| #define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */ |
Definition at line 1143 of file if_mskreg.h.
◆ PREF_UNIT_PUT_IDX_REG
| #define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */ |
Definition at line 591 of file if_mskreg.h.
◆ PREF_UNIT_RST_CLR
| #define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */ |
Definition at line 1145 of file if_mskreg.h.
◆ PREF_UNIT_RST_SET
| #define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */ |
Definition at line 1146 of file if_mskreg.h.
◆ PU_PUTIDX_VALID
| #define PU_PUTIDX_VALID 0x10000000 |
Definition at line 2226 of file if_mskreg.h.
◆ PULS_1300MS
| #define PULS_1300MS 7 /* 1.3 s to 2.7 s */ |
Definition at line 1525 of file if_mskreg.h.
◆ PULS_170MS
| #define PULS_170MS 4 /* 170 ms to 340 ms */ |
Definition at line 1522 of file if_mskreg.h.
◆ PULS_21MS
| #define PULS_21MS 1 /* 21 ms to 42 ms */ |
Definition at line 1519 of file if_mskreg.h.
◆ PULS_340MS
| #define PULS_340MS 5 /* 340 ms to 670 ms */ |
Definition at line 1523 of file if_mskreg.h.
◆ PULS_42MS
| #define PULS_42MS 2 /* 42 ms to 84 ms */ |
Definition at line 1520 of file if_mskreg.h.
◆ PULS_670MS
| #define PULS_670MS 6 /* 670 ms to 1.3 s */ |
Definition at line 1524 of file if_mskreg.h.
◆ PULS_84MS
| #define PULS_84MS 3 /* 84 ms to 170 ms */ |
Definition at line 1521 of file if_mskreg.h.
◆ PULS_NO_STR
| #define PULS_NO_STR 0 /* no pulse stretching */ |
Definition at line 1518 of file if_mskreg.h.
◆ Q_AC_H
| #define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */ |
Definition at line 561 of file if_mskreg.h.
◆ Q_AC_L
| #define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */ |
Definition at line 560 of file if_mskreg.h.
◆ Q_ADDR
| #define Q_ADDR | ( | Queue, | |
| Offs | |||
| ) | (B8_Q_REGS + (Queue) + (Offs)) |
Definition at line 581 of file if_mskreg.h.
◆ Q_AL
| #define Q_AL 0x42 /* 8 bit FIFO Alignment */ |
Definition at line 571 of file if_mskreg.h.
◆ Q_ASF_R1
| #define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */ |
Definition at line 1208 of file if_mskreg.h.
◆ Q_ASF_R2
| #define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */ |
Definition at line 1209 of file if_mskreg.h.
◆ Q_ASF_T1
| #define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */ |
Definition at line 1210 of file if_mskreg.h.
◆ Q_ASF_T2
| #define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */ |
Definition at line 1211 of file if_mskreg.h.
◆ Q_BC
| #define Q_BC 0x30 /* 32 bit Current Byte Counter */ |
Definition at line 562 of file if_mskreg.h.
◆ Q_CSR
| #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ |
Definition at line 563 of file if_mskreg.h.
◆ Q_D
| #define Q_D 0x00 /* 8*32 bit Current Descriptor */ |
Definition at line 557 of file if_mskreg.h.
◆ Q_DA_L
| #define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */ |
Definition at line 558 of file if_mskreg.h.
◆ Q_DONE
| #define Q_DONE 0x24 /* 16 bit Done Index */ |
Definition at line 559 of file if_mskreg.h.
◆ Q_F
| #define Q_F 0x38 /* 32 bit Flag Register */ |
Definition at line 564 of file if_mskreg.h.
◆ Q_R1
| #define Q_R1 0x0000 /* Receive Queue 1 */ |
Definition at line 1201 of file if_mskreg.h.
◆ Q_R2
| #define Q_R2 0x0080 /* Receive Queue 2 */ |
Definition at line 1202 of file if_mskreg.h.
◆ Q_RL
| #define Q_RL 0x4a /* 8 bit FIFO Read Level */ |
Definition at line 575 of file if_mskreg.h.
◆ Q_RP
| #define Q_RP 0x48 /* 8 bit FIFO Read Pointer */ |
Definition at line 574 of file if_mskreg.h.
◆ Q_RSL
| #define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */ |
Definition at line 573 of file if_mskreg.h.
◆ Q_RSP
| #define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */ |
Definition at line 572 of file if_mskreg.h.
◆ Q_T1
| #define Q_T1 0x3c /* 32 bit Test Register 1 */ |
Definition at line 565 of file if_mskreg.h.
◆ Q_T1_RD
| #define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */ |
Definition at line 568 of file if_mskreg.h.
◆ Q_T1_SV
| #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ |
Definition at line 569 of file if_mskreg.h.
◆ Q_T1_TR
| #define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */ |
Definition at line 566 of file if_mskreg.h.
◆ Q_T1_WR
| #define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */ |
Definition at line 567 of file if_mskreg.h.
◆ Q_WL
| #define Q_WL 0x4e /* 8 bit FIFO Write Level */ |
Definition at line 578 of file if_mskreg.h.
◆ Q_WM
| #define Q_WM 0x40 /* 16 bit FIFO Watermark */ |
Definition at line 570 of file if_mskreg.h.
◆ Q_WP
| #define Q_WP 0x4c /* 8 bit FIFO Write Pointer */ |
Definition at line 576 of file if_mskreg.h.
◆ Q_WSL
| #define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */ |
Definition at line 579 of file if_mskreg.h.
◆ Q_WSP
| #define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */ |
Definition at line 577 of file if_mskreg.h.
◆ Q_XA1
| #define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */ |
Definition at line 1204 of file if_mskreg.h.
◆ Q_XA2
| #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ |
Definition at line 1206 of file if_mskreg.h.
◆ Q_XS1
| #define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */ |
Definition at line 1203 of file if_mskreg.h.
◆ Q_XS2
| #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ |
Definition at line 1205 of file if_mskreg.h.
◆ RAM_ADR_RAN
| #define RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */ |
Definition at line 1054 of file if_mskreg.h.
◆ RB_ADDR
| #define RB_ADDR | ( | Queue, | |
| Offs | |||
| ) | (B16_RAM_REGS + (Queue) + (Offs)) |
Definition at line 1213 of file if_mskreg.h.
◆ RB_CTRL
| #define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ |
Definition at line 618 of file if_mskreg.h.
◆ RB_DIS_OP_MD
| #define RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */ |
Definition at line 1179 of file if_mskreg.h.
◆ RB_DIS_STFWD
| #define RB_DIS_STFWD BIT_4 /* Disable Store & Forward */ |
Definition at line 1177 of file if_mskreg.h.
◆ RB_ENA_OP_MD
| #define RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */ |
Definition at line 1178 of file if_mskreg.h.
◆ RB_ENA_STFWD
| #define RB_ENA_STFWD BIT_5 /* Enable Store & Forward */ |
Definition at line 1176 of file if_mskreg.h.
◆ RB_END
| #define RB_END 0x04 /* 32 bit RAM Buffer End Address */ |
Definition at line 609 of file if_mskreg.h.
◆ RB_LEV
| #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ |
Definition at line 617 of file if_mskreg.h.
◆ RB_MSK
| #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ |
Definition at line 1159 of file if_mskreg.h.
◆ RB_PC
| #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ |
Definition at line 616 of file if_mskreg.h.
◆ RB_PC_DEC
| #define RB_PC_DEC BIT_3 /* Packet Counter Decrement */ |
Definition at line 1162 of file if_mskreg.h.
◆ RB_PC_INC
| #define RB_PC_INC BIT_0 /* Packet Counter Increment */ |
Definition at line 1165 of file if_mskreg.h.
◆ RB_PC_T_OFF
| #define RB_PC_T_OFF BIT_1 /* Packet Counter Test Off */ |
Definition at line 1164 of file if_mskreg.h.
◆ RB_PC_T_ON
| #define RB_PC_T_ON BIT_2 /* Packet Counter Test On */ |
Definition at line 1163 of file if_mskreg.h.
◆ RB_RP
| #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ |
Definition at line 611 of file if_mskreg.h.
◆ RB_RP_INC
| #define RB_RP_INC BIT_0 /* Read Pointer Increment */ |
Definition at line 1173 of file if_mskreg.h.
◆ RB_RP_T_OFF
| #define RB_RP_T_OFF BIT_1 /* Read Pointer Test Off */ |
Definition at line 1172 of file if_mskreg.h.
◆ RB_RP_T_ON
| #define RB_RP_T_ON BIT_2 /* Read Pointer Test On */ |
Definition at line 1171 of file if_mskreg.h.
◆ RB_RST_CLR
| #define RB_RST_CLR BIT_1 /* Clear RAM Buf STM Reset */ |
Definition at line 1180 of file if_mskreg.h.
◆ RB_RST_SET
| #define RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */ |
Definition at line 1181 of file if_mskreg.h.
◆ RB_RX_LTHP
| #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ |
Definition at line 615 of file if_mskreg.h.
◆ RB_RX_LTPP
| #define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */ |
Definition at line 613 of file if_mskreg.h.
◆ RB_RX_UTHP
| #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ |
Definition at line 614 of file if_mskreg.h.
◆ RB_RX_UTPP
| #define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */ |
Definition at line 612 of file if_mskreg.h.
◆ RB_START
| #define RB_START 0x00 /* 32 bit RAM Buffer Start Address */ |
Definition at line 608 of file if_mskreg.h.
◆ RB_TST1
| #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ |
Definition at line 619 of file if_mskreg.h.
◆ RB_TST2
| #define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */ |
Definition at line 620 of file if_mskreg.h.
◆ RB_WP
| #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ |
Definition at line 610 of file if_mskreg.h.
◆ RB_WP_INC
| #define RB_WP_INC BIT_4 /* Write Pointer Increment */ |
Definition at line 1170 of file if_mskreg.h.
◆ RB_WP_T_OFF
| #define RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */ |
Definition at line 1169 of file if_mskreg.h.
◆ RB_WP_T_ON
| #define RB_WP_T_ON BIT_6 /* Write Pointer Test On */ |
Definition at line 1168 of file if_mskreg.h.
◆ RI_CLR_RD_PERR
| #define RI_CLR_RD_PERR BIT_9 /* Clear IRQ RAM Read Parity Err */ |
Definition at line 1058 of file if_mskreg.h.
◆ RI_CLR_WR_PERR
| #define RI_CLR_WR_PERR BIT_8 /* Clear IRQ RAM Write Parity Err */ |
Definition at line 1059 of file if_mskreg.h.
◆ RI_RST_CLR
| #define RI_RST_CLR BIT_1 /* Clear RAM Interface Reset */ |
Definition at line 1060 of file if_mskreg.h.
◆ RI_RST_SET
| #define RI_RST_SET BIT_0 /* Set RAM Interface Reset */ |
Definition at line 1061 of file if_mskreg.h.
◆ RSS_KEY_ADDR
| #define RSS_KEY_ADDR | ( | Port, | |
| KeyIndex | |||
| ) | ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex)) |
Definition at line 547 of file if_mskreg.h.
◆ RX_FF_FL_DEF_MSK
| #define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR |
Definition at line 1938 of file if_mskreg.h.
◆ RX_GMF_AF_THR
| #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ |
Definition at line 627 of file if_mskreg.h.
◆ RX_GMF_AF_THR_MIN
| #define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */ |
Definition at line 2002 of file if_mskreg.h.
◆ RX_GMF_CTRL_T
| #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ |
Definition at line 628 of file if_mskreg.h.
◆ RX_GMF_EA
| #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ |
Definition at line 626 of file if_mskreg.h.
◆ RX_GMF_FL_MSK
| #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ |
Definition at line 629 of file if_mskreg.h.
◆ RX_GMF_FL_THR
| #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ |
Definition at line 630 of file if_mskreg.h.
◆ RX_GMF_FL_THR_DEF
| #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ |
Definition at line 2003 of file if_mskreg.h.
◆ RX_GMF_LP_THR
| #define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ |
Definition at line 633 of file if_mskreg.h.
◆ RX_GMF_RLEV
| #define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ |
Definition at line 638 of file if_mskreg.h.
◆ RX_GMF_RP
| #define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ |
Definition at line 637 of file if_mskreg.h.
◆ RX_GMF_TR_THR
| #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ |
Definition at line 631 of file if_mskreg.h.
◆ RX_GMF_UP_THR
| #define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ |
Definition at line 632 of file if_mskreg.h.
◆ RX_GMF_VLAN
| #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ |
Definition at line 634 of file if_mskreg.h.
◆ RX_GMF_WLEV
| #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ |
Definition at line 636 of file if_mskreg.h.
◆ RX_GMF_WP
| #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ |
Definition at line 635 of file if_mskreg.h.
◆ RX_TRUNC_OFF
| #define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ |
Definition at line 1959 of file if_mskreg.h.
◆ RX_TRUNC_ON
| #define RX_TRUNC_ON BIT_27 /* enable packet truncation */ |
Definition at line 1958 of file if_mskreg.h.
◆ RX_VLAN_STRIP_OFF
| #define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ |
Definition at line 1961 of file if_mskreg.h.
◆ RX_VLAN_STRIP_ON
| #define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ |
Definition at line 1960 of file if_mskreg.h.
◆ SC_STAT_CLR_IRQ
| #define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */ |
Definition at line 2057 of file if_mskreg.h.
◆ SC_STAT_OP_OFF
| #define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */ |
Definition at line 2059 of file if_mskreg.h.
◆ SC_STAT_OP_ON
| #define SC_STAT_OP_ON BIT_3 /* Operational Mode On */ |
Definition at line 2058 of file if_mskreg.h.
◆ SC_STAT_RST_CLR
| #define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */ |
Definition at line 2060 of file if_mskreg.h.
◆ SC_STAT_RST_SET
| #define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */ |
Definition at line 2061 of file if_mskreg.h.
◆ SELECT_RAM_BUFFER
| #define SELECT_RAM_BUFFER | ( | rb, | |
| addr | |||
| ) | (addr | (rb << 6)) /* Yukon-2 only */ |
Definition at line 500 of file if_mskreg.h.
◆ SHIFT0
| #define SHIFT0 | ( | x | ) | ((x) << 0) |
Definition at line 225 of file if_mskreg.h.
◆ SHIFT1
| #define SHIFT1 | ( | x | ) | ((x) << 1) |
Definition at line 224 of file if_mskreg.h.
◆ SHIFT10
| #define SHIFT10 | ( | x | ) | ((x) << 10) |
Definition at line 215 of file if_mskreg.h.
◆ SHIFT11
| #define SHIFT11 | ( | x | ) | ((x) << 11) |
Definition at line 214 of file if_mskreg.h.
◆ SHIFT12
| #define SHIFT12 | ( | x | ) | ((x) << 12) |
Definition at line 213 of file if_mskreg.h.
◆ SHIFT13
| #define SHIFT13 | ( | x | ) | ((x) << 13) |
Definition at line 212 of file if_mskreg.h.
◆ SHIFT14
| #define SHIFT14 | ( | x | ) | ((x) << 14) |
Definition at line 211 of file if_mskreg.h.
◆ SHIFT15
| #define SHIFT15 | ( | x | ) | ((x) << 15) |
Definition at line 210 of file if_mskreg.h.
◆ SHIFT16
| #define SHIFT16 | ( | x | ) | ((x) << 16) |
Definition at line 209 of file if_mskreg.h.
◆ SHIFT17
| #define SHIFT17 | ( | x | ) | ((x) << 17) |
Definition at line 208 of file if_mskreg.h.
◆ SHIFT18
| #define SHIFT18 | ( | x | ) | ((x) << 18) |
Definition at line 207 of file if_mskreg.h.
◆ SHIFT19
| #define SHIFT19 | ( | x | ) | ((x) << 19) |
Definition at line 206 of file if_mskreg.h.
◆ SHIFT2
| #define SHIFT2 | ( | x | ) | ((x) << 2) |
Definition at line 223 of file if_mskreg.h.
◆ SHIFT20
| #define SHIFT20 | ( | x | ) | ((x) << 20) |
Definition at line 205 of file if_mskreg.h.
◆ SHIFT21
| #define SHIFT21 | ( | x | ) | ((x) << 21) |
Definition at line 204 of file if_mskreg.h.
◆ SHIFT22
| #define SHIFT22 | ( | x | ) | ((x) << 22) |
Definition at line 203 of file if_mskreg.h.
◆ SHIFT23
| #define SHIFT23 | ( | x | ) | ((x) << 23) |
Definition at line 202 of file if_mskreg.h.
◆ SHIFT24
| #define SHIFT24 | ( | x | ) | ((x) << 24) |
Definition at line 201 of file if_mskreg.h.
◆ SHIFT25
| #define SHIFT25 | ( | x | ) | ((x) << 25) |
Definition at line 200 of file if_mskreg.h.
◆ SHIFT26
| #define SHIFT26 | ( | x | ) | ((x) << 26) |
Definition at line 199 of file if_mskreg.h.
◆ SHIFT27
| #define SHIFT27 | ( | x | ) | ((x) << 27) |
Definition at line 198 of file if_mskreg.h.
◆ SHIFT28
| #define SHIFT28 | ( | x | ) | ((x) << 28) |
Definition at line 197 of file if_mskreg.h.
◆ SHIFT29
| #define SHIFT29 | ( | x | ) | ((x) << 29) |
Definition at line 196 of file if_mskreg.h.
◆ SHIFT3
| #define SHIFT3 | ( | x | ) | ((x) << 3) |
Definition at line 222 of file if_mskreg.h.
◆ SHIFT30
| #define SHIFT30 | ( | x | ) | ((x) << 30) |
Definition at line 195 of file if_mskreg.h.
◆ SHIFT31
| #define SHIFT31 | ( | x | ) | ((x) << 31) |
Definition at line 194 of file if_mskreg.h.
◆ SHIFT4
| #define SHIFT4 | ( | x | ) | ((x) << 4) |
Definition at line 221 of file if_mskreg.h.
◆ SHIFT5
| #define SHIFT5 | ( | x | ) | ((x) << 5) |
Definition at line 220 of file if_mskreg.h.
◆ SHIFT6
| #define SHIFT6 | ( | x | ) | ((x) << 6) |
Definition at line 219 of file if_mskreg.h.
◆ SHIFT7
| #define SHIFT7 | ( | x | ) | ((x) << 7) |
Definition at line 218 of file if_mskreg.h.
◆ SHIFT8
| #define SHIFT8 | ( | x | ) | ((x) << 8) |
Definition at line 217 of file if_mskreg.h.
◆ SHIFT9
| #define SHIFT9 | ( | x | ) | ((x) << 9) |
Definition at line 216 of file if_mskreg.h.
◆ ST_LAST_IDX_MASK
| #define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */ |
Definition at line 734 of file if_mskreg.h.
◆ ST_TXRP_IDX_MASK
| #define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */ |
Definition at line 735 of file if_mskreg.h.
◆ ST_TXTH_IDX_MASK
| #define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */ |
Definition at line 736 of file if_mskreg.h.
◆ ST_WM_IDX_MASK
| #define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */ |
Definition at line 737 of file if_mskreg.h.
◆ STAT_CTRL
| #define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */ |
Definition at line 702 of file if_mskreg.h.
◆ STAT_FIFO_ISR_WM
| #define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */ |
Definition at line 719 of file if_mskreg.h.
◆ STAT_FIFO_LEVEL
| #define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */ |
Definition at line 716 of file if_mskreg.h.
◆ STAT_FIFO_RP
| #define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */ |
Definition at line 714 of file if_mskreg.h.
◆ STAT_FIFO_RSP
| #define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */ |
Definition at line 715 of file if_mskreg.h.
◆ STAT_FIFO_SHLVL
| #define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */ |
Definition at line 717 of file if_mskreg.h.
◆ STAT_FIFO_WM
| #define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */ |
Definition at line 718 of file if_mskreg.h.
◆ STAT_FIFO_WP
| #define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */ |
Definition at line 713 of file if_mskreg.h.
◆ STAT_ISR_TIMER_CNT
| #define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */ |
Definition at line 730 of file if_mskreg.h.
◆ STAT_ISR_TIMER_CTRL
| #define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */ |
Definition at line 731 of file if_mskreg.h.
◆ STAT_ISR_TIMER_INI
| #define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */ |
Definition at line 729 of file if_mskreg.h.
◆ STAT_ISR_TIMER_TEST
| #define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */ |
Definition at line 732 of file if_mskreg.h.
◆ STAT_LAST_IDX
| #define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */ |
Definition at line 703 of file if_mskreg.h.
◆ STAT_LEV_TIMER_CNT
| #define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */ |
Definition at line 722 of file if_mskreg.h.
◆ STAT_LEV_TIMER_CTRL
| #define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */ |
Definition at line 723 of file if_mskreg.h.
◆ STAT_LEV_TIMER_INI
| #define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */ |
Definition at line 721 of file if_mskreg.h.
◆ STAT_LEV_TIMER_TEST
| #define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */ |
Definition at line 724 of file if_mskreg.h.
◆ STAT_LIST_ADDR_HI
| #define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */ |
Definition at line 705 of file if_mskreg.h.
◆ STAT_LIST_ADDR_LO
| #define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */ |
Definition at line 704 of file if_mskreg.h.
◆ STAT_PUT_IDX
| #define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */ |
Definition at line 711 of file if_mskreg.h.
◆ STAT_TX_IDX_TH
| #define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */ |
Definition at line 710 of file if_mskreg.h.
◆ STAT_TX_TIMER_CNT
| #define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */ |
Definition at line 726 of file if_mskreg.h.
◆ STAT_TX_TIMER_CTRL
| #define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */ |
Definition at line 727 of file if_mskreg.h.
◆ STAT_TX_TIMER_INI
| #define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */ |
Definition at line 725 of file if_mskreg.h.
◆ STAT_TX_TIMER_TEST
| #define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */ |
Definition at line 728 of file if_mskreg.h.
◆ STAT_TXA1_RIDX
| #define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */ |
Definition at line 706 of file if_mskreg.h.
◆ STAT_TXA2_RIDX
| #define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */ |
Definition at line 708 of file if_mskreg.h.
◆ STAT_TXS1_RIDX
| #define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */ |
Definition at line 707 of file if_mskreg.h.
◆ STAT_TXS2_RIDX
| #define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */ |
Definition at line 709 of file if_mskreg.h.
◆ STLE_CSS_MASK
| #define STLE_CSS_MASK 0x00ff0000 |
Definition at line 2280 of file if_mskreg.h.
◆ STLE_LEN_MASK
| #define STLE_LEN_MASK 0x0000ffff |
Definition at line 2281 of file if_mskreg.h.
◆ STLE_OP_MASK
| #define STLE_OP_MASK 0xff000000 |
Definition at line 2279 of file if_mskreg.h.
◆ STLE_TXA1_MSKL
| #define STLE_TXA1_MSKL 0x00000fff |
Definition at line 2202 of file if_mskreg.h.
◆ STLE_TXA1_SHIFTL
| #define STLE_TXA1_SHIFTL 0 |
Definition at line 2203 of file if_mskreg.h.
◆ STLE_TXA2_MSKH
| #define STLE_TXA2_MSKH 0x000f |
Definition at line 2212 of file if_mskreg.h.
◆ STLE_TXA2_MSKL
| #define STLE_TXA2_MSKL 0xff000000 |
Definition at line 2210 of file if_mskreg.h.
◆ STLE_TXA2_SHIFTH
| #define STLE_TXA2_SHIFTH 8 |
Definition at line 2214 of file if_mskreg.h.
◆ STLE_TXA2_SHIFTL
| #define STLE_TXA2_SHIFTL 24 |
Definition at line 2211 of file if_mskreg.h.
◆ STLE_TXS1_MSKL
| #define STLE_TXS1_MSKL 0x00fff000 |
Definition at line 2206 of file if_mskreg.h.
◆ STLE_TXS1_SHIFTL
| #define STLE_TXS1_SHIFTL 12 |
Definition at line 2207 of file if_mskreg.h.
◆ STLE_TXS2_MSKH
| #define STLE_TXS2_MSKH 0xfff0 |
Definition at line 2219 of file if_mskreg.h.
◆ STLE_TXS2_MSKL
| #define STLE_TXS2_MSKL 0x00000000 |
Definition at line 2217 of file if_mskreg.h.
◆ STLE_TXS2_SHIFTH
| #define STLE_TXS2_SHIFTH 4 |
Definition at line 2220 of file if_mskreg.h.
◆ STLE_TXS2_SHIFTL
| #define STLE_TXS2_SHIFTL 0 |
Definition at line 2218 of file if_mskreg.h.
◆ SW_OWNER
| #define SW_OWNER 0x00000000 |
Definition at line 2224 of file if_mskreg.h.
◆ TIM_CLR_IRQ
| #define TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */ |
Definition at line 970 of file if_mskreg.h.
◆ TIM_START
| #define TIM_START BIT_2 /* Start Timer */ |
Definition at line 968 of file if_mskreg.h.
◆ TIM_STOP
| #define TIM_STOP BIT_1 /* Stop Timer */ |
Definition at line 969 of file if_mskreg.h.
◆ TIM_T_OFF
| #define TIM_T_OFF BIT_1 /* Test mode off */ |
Definition at line 976 of file if_mskreg.h.
◆ TIM_T_ON
| #define TIM_T_ON BIT_2 /* Test mode on */ |
Definition at line 975 of file if_mskreg.h.
◆ TIM_T_STEP
| #define TIM_T_STEP BIT_0 /* Test step */ |
Definition at line 977 of file if_mskreg.h.
◆ TST_CFG_WRITE_OFF
| #define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */ |
Definition at line 995 of file if_mskreg.h.
◆ TST_CFG_WRITE_ON
| #define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */ |
Definition at line 994 of file if_mskreg.h.
◆ TST_FRC_APERR_M
| #define TST_FRC_APERR_M BIT_3 /* force ADDRPERR on MST */ |
Definition at line 992 of file if_mskreg.h.
◆ TST_FRC_APERR_T
| #define TST_FRC_APERR_T BIT_2 /* force ADDRPERR on TRG */ |
Definition at line 993 of file if_mskreg.h.
◆ TST_FRC_DPERR_MR
| #define TST_FRC_DPERR_MR BIT_7 /* force DATAPERR on MST RD */ |
Definition at line 988 of file if_mskreg.h.
◆ TST_FRC_DPERR_MW
| #define TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */ |
Definition at line 989 of file if_mskreg.h.
◆ TST_FRC_DPERR_TR
| #define TST_FRC_DPERR_TR BIT_5 /* force DATAPERR on TRG RD */ |
Definition at line 990 of file if_mskreg.h.
◆ TST_FRC_DPERR_TW
| #define TST_FRC_DPERR_TW BIT_4 /* force DATAPERR on TRG WR */ |
Definition at line 991 of file if_mskreg.h.
◆ TX_BACK_OFF_LIM
| #define TX_BACK_OFF_LIM | ( | x | ) | ((x) & GM_TXPA_BO_LIM_MSK) |
Definition at line 1873 of file if_mskreg.h.
◆ TX_BOF_LIM_DEF
| #define TX_BOF_LIM_DEF 0x04 |
Definition at line 1878 of file if_mskreg.h.
◆ TX_COL_DEF
| #define TX_COL_DEF 0x04 |
Definition at line 1855 of file if_mskreg.h.
◆ TX_COL_THR
| #define TX_COL_THR | ( | x | ) | (SHIFT10(x) & GM_TXCR_COL_THR_MSK) |
Definition at line 1854 of file if_mskreg.h.
◆ TX_GMF_AE_THR
| #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ |
Definition at line 651 of file if_mskreg.h.
◆ TX_GMF_CTRL_T
| #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ |
Definition at line 652 of file if_mskreg.h.
◆ TX_GMF_EA
| #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ |
Definition at line 650 of file if_mskreg.h.
◆ TX_GMF_RLEV
| #define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ |
Definition at line 659 of file if_mskreg.h.
◆ TX_GMF_RP
| #define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ |
Definition at line 657 of file if_mskreg.h.
◆ TX_GMF_RSTP
| #define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ |
Definition at line 658 of file if_mskreg.h.
◆ TX_GMF_VLAN
| #define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */ |
Definition at line 653 of file if_mskreg.h.
◆ TX_GMF_WLEV
| #define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ |
Definition at line 656 of file if_mskreg.h.
◆ TX_GMF_WP
| #define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ |
Definition at line 654 of file if_mskreg.h.
◆ TX_GMF_WSP
| #define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */ |
Definition at line 655 of file if_mskreg.h.
◆ TX_IPG_JAM_DATA
| #define TX_IPG_JAM_DATA | ( | x | ) | (SHIFT4(x) & GM_TXPA_JAMDAT_MSK) |
Definition at line 1872 of file if_mskreg.h.
◆ TX_IPG_JAM_DEF
| #define TX_IPG_JAM_DEF 0x1c |
Definition at line 1877 of file if_mskreg.h.
◆ TX_JAM_IPG_DEF
| #define TX_JAM_IPG_DEF 0x0b |
Definition at line 1876 of file if_mskreg.h.
◆ TX_JAM_IPG_VAL
| #define TX_JAM_IPG_VAL | ( | x | ) | (SHIFT9(x) & GM_TXPA_JAMIPG_MSK) |
Definition at line 1871 of file if_mskreg.h.
◆ TX_JAM_LEN_DEF
| #define TX_JAM_LEN_DEF 0x03 |
Definition at line 1875 of file if_mskreg.h.
◆ TX_JAM_LEN_VAL
| #define TX_JAM_LEN_VAL | ( | x | ) | (SHIFT14(x) & GM_TXPA_JAMLEN_MSK) |
Definition at line 1870 of file if_mskreg.h.
◆ TX_JUMBO_DIS
| #define TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */ |
Definition at line 1989 of file if_mskreg.h.
◆ TX_JUMBO_ENA
| #define TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */ |
Definition at line 1988 of file if_mskreg.h.
◆ TX_LOCK
| #define TX_LOCK 0x01000000 |
Definition at line 2238 of file if_mskreg.h.
◆ TX_STFW_DIS
| #define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */ |
Definition at line 1984 of file if_mskreg.h.
◆ TX_STFW_ENA
| #define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */ |
Definition at line 1985 of file if_mskreg.h.
◆ TX_VLAN_TAG_OFF
| #define TX_VLAN_TAG_OFF BIT_24 /* disable VLAN tagging */ |
Definition at line 1987 of file if_mskreg.h.
◆ TX_VLAN_TAG_ON
| #define TX_VLAN_TAG_ON BIT_25 /* enable VLAN tagging */ |
Definition at line 1986 of file if_mskreg.h.
◆ TXA_CTRL
| #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ |
Definition at line 533 of file if_mskreg.h.
◆ TXA_DIS_ALLOC
| #define TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */ |
Definition at line 1076 of file if_mskreg.h.
◆ TXA_DIS_ARB
| #define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */ |
Definition at line 1080 of file if_mskreg.h.
◆ TXA_DIS_FSYNC
| #define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */ |
Definition at line 1074 of file if_mskreg.h.
◆ TXA_ENA_ALLOC
| #define TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */ |
Definition at line 1075 of file if_mskreg.h.
◆ TXA_ENA_ARB
| #define TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */ |
Definition at line 1079 of file if_mskreg.h.
◆ TXA_ENA_FSYNC
| #define TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */ |
Definition at line 1073 of file if_mskreg.h.
◆ TXA_INT_T_OFF
| #define TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */ |
Definition at line 1084 of file if_mskreg.h.
◆ TXA_INT_T_ON
| #define TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */ |
Definition at line 1083 of file if_mskreg.h.
◆ TXA_INT_T_STEP
| #define TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */ |
Definition at line 1085 of file if_mskreg.h.
◆ TXA_ITI_INI
| #define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/ |
Definition at line 529 of file if_mskreg.h.
◆ TXA_ITI_VAL
| #define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */ |
Definition at line 530 of file if_mskreg.h.
◆ TXA_LIM_INI
| #define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */ |
Definition at line 531 of file if_mskreg.h.
◆ TXA_LIM_T_OFF
| #define TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */ |
Definition at line 1087 of file if_mskreg.h.
◆ TXA_LIM_T_ON
| #define TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */ |
Definition at line 1086 of file if_mskreg.h.
◆ TXA_LIM_T_STEP
| #define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */ |
Definition at line 1088 of file if_mskreg.h.
◆ TXA_LIM_VAL
| #define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */ |
Definition at line 532 of file if_mskreg.h.
◆ TXA_MAX_VAL
| #define TXA_MAX_VAL 0x00ffffff/* Bit 23.. 0: Max TXA Timer/Cnt Val */ |
Definition at line 1070 of file if_mskreg.h.
◆ TXA_PRIO_XS
| #define TXA_PRIO_XS BIT_0 /* sync queue has prio to send */ |
Definition at line 1091 of file if_mskreg.h.
◆ TXA_START_RC
| #define TXA_START_RC BIT_3 /* Start sync Rate Control */ |
Definition at line 1077 of file if_mskreg.h.
◆ TXA_STAT
| #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ |
Definition at line 535 of file if_mskreg.h.
◆ TXA_STOP_RC
| #define TXA_STOP_RC BIT_2 /* Stop sync Rate Control */ |
Definition at line 1078 of file if_mskreg.h.
◆ TXA_TEST
| #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ |
Definition at line 534 of file if_mskreg.h.
◆ UDPTCP
| #define UDPTCP 0x00010000 |
Definition at line 2229 of file if_mskreg.h.
◆ VENDORID_DLINK
| #define VENDORID_DLINK 0x1186 |
Definition at line 113 of file if_mskreg.h.
◆ VENDORID_MARVELL
| #define VENDORID_MARVELL 0x11AB |
Definition at line 108 of file if_mskreg.h.
◆ VENDORID_SK
| #define VENDORID_SK 0x1148 |
Definition at line 103 of file if_mskreg.h.
◆ WOL_CTL_CLEAR_RESULT
| #define WOL_CTL_CLEAR_RESULT BIT_12 |
Definition at line 1226 of file if_mskreg.h.
◆ WOL_CTL_DEFAULT
| #define WOL_CTL_DEFAULT |
Definition at line 1240 of file if_mskreg.h.
◆ WOL_CTL_DIS_LINK_CHG_UNIT
| #define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4 |
Definition at line 1234 of file if_mskreg.h.
◆ WOL_CTL_DIS_MAGIC_PKT_UNIT
| #define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2 |
Definition at line 1236 of file if_mskreg.h.
◆ WOL_CTL_DIS_PATTERN_UNIT
| #define WOL_CTL_DIS_PATTERN_UNIT BIT_0 |
Definition at line 1238 of file if_mskreg.h.
◆ WOL_CTL_DIS_PME_ON_LINK_CHG
| #define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10 |
Definition at line 1228 of file if_mskreg.h.
◆ WOL_CTL_DIS_PME_ON_MAGIC_PKT
| #define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8 |
Definition at line 1230 of file if_mskreg.h.
◆ WOL_CTL_DIS_PME_ON_PATTERN
| #define WOL_CTL_DIS_PME_ON_PATTERN BIT_6 |
Definition at line 1232 of file if_mskreg.h.
◆ WOL_CTL_ENA_LINK_CHG_UNIT
| #define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5 |
Definition at line 1233 of file if_mskreg.h.
◆ WOL_CTL_ENA_MAGIC_PKT_UNIT
| #define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3 |
Definition at line 1235 of file if_mskreg.h.
◆ WOL_CTL_ENA_PATTERN_UNIT
| #define WOL_CTL_ENA_PATTERN_UNIT BIT_1 |
Definition at line 1237 of file if_mskreg.h.
◆ WOL_CTL_ENA_PME_ON_LINK_CHG
| #define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11 |
Definition at line 1227 of file if_mskreg.h.
◆ WOL_CTL_ENA_PME_ON_MAGIC_PKT
| #define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9 |
Definition at line 1229 of file if_mskreg.h.
◆ WOL_CTL_ENA_PME_ON_PATTERN
| #define WOL_CTL_ENA_PME_ON_PATTERN BIT_7 |
Definition at line 1231 of file if_mskreg.h.
◆ WOL_CTL_LINK_CHG_OCC
| #define WOL_CTL_LINK_CHG_OCC BIT_15 |
Definition at line 1223 of file if_mskreg.h.
◆ WOL_CTL_MAGIC_PKT_OCC
| #define WOL_CTL_MAGIC_PKT_OCC BIT_14 |
Definition at line 1224 of file if_mskreg.h.
◆ WOL_CTL_PATT_ENA
| #define WOL_CTL_PATT_ENA | ( | x | ) | (BIT_0 << (x)) |
Definition at line 1249 of file if_mskreg.h.
◆ WOL_CTL_PATTERN_OCC
| #define WOL_CTL_PATTERN_OCC BIT_13 |
Definition at line 1225 of file if_mskreg.h.
◆ WOL_CTRL_STAT
| #define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */ |
Definition at line 753 of file if_mskreg.h.
◆ WOL_MAC_ADDR_HI
| #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ |
Definition at line 757 of file if_mskreg.h.
◆ WOL_MAC_ADDR_LO
| #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ |
Definition at line 756 of file if_mskreg.h.
◆ WOL_MATCH_CTL
| #define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */ |
Definition at line 754 of file if_mskreg.h.
◆ WOL_MATCH_RES
| #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ |
Definition at line 755 of file if_mskreg.h.
◆ WOL_PATT_ASFM
| #define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */ |
Definition at line 759 of file if_mskreg.h.
◆ WOL_PATT_CNT_0
| #define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */ |
Definition at line 769 of file if_mskreg.h.
◆ WOL_PATT_CNT_4
| #define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */ |
Definition at line 770 of file if_mskreg.h.
◆ WOL_PATT_FORCE_PME
| #define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */ |
Definition at line 1252 of file if_mskreg.h.
◆ WOL_PATT_LEN_HI
| #define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */ |
Definition at line 765 of file if_mskreg.h.
◆ WOL_PATT_LEN_LO
| #define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */ |
Definition at line 764 of file if_mskreg.h.
◆ WOL_PATT_MATCH_PME_ALL
| #define WOL_PATT_MATCH_PME_ALL 0x7f |
Definition at line 1253 of file if_mskreg.h.
◆ WOL_PATT_PME
| #define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */ |
Definition at line 758 of file if_mskreg.h.
◆ WOL_PATT_RAM_1
| #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ |
Definition at line 775 of file if_mskreg.h.
◆ WOL_PATT_RAM_2
| #define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */ |
Definition at line 776 of file if_mskreg.h.
◆ WOL_PATT_RPTR
| #define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */ |
Definition at line 760 of file if_mskreg.h.
◆ WOL_REG_OFFS
| #define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */ |
Definition at line 751 of file if_mskreg.h.
◆ WR_SUM
| #define WR_SUM 0x00040000 |
Definition at line 2231 of file if_mskreg.h.
◆ Y2_ASF_CLK_HALT
| #define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */ |
Definition at line 2027 of file if_mskreg.h.
◆ Y2_ASF_CLR_ASFI
| #define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */ |
Definition at line 2053 of file if_mskreg.h.
◆ Y2_ASF_CLR_HSTI
| #define Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */ |
Definition at line 2023 of file if_mskreg.h.
◆ Y2_ASF_DISABLE
| #define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */ |
Definition at line 792 of file if_mskreg.h.
◆ Y2_ASF_ENABLE
| #define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */ |
Definition at line 791 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_AHB_RST
| #define Y2_ASF_HCU_CCSR_AHB_RST BIT_9 /* Reset AHB bridge */ |
Definition at line 2036 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_ASF_HALTED
| #define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1 |
Definition at line 2048 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_ASF_RESET
| #define Y2_ASF_HCU_CCSR_ASF_RESET 0 |
Definition at line 2047 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_ASF_RUNNING
| #define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0 |
Definition at line 2049 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_CLR_IRQ_HOST
| #define Y2_ASF_HCU_CCSR_CLR_IRQ_HOST BIT_17 /* Clear IRQ_HOST */ |
Definition at line 2034 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0
| #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3 |
Definition at line 2040 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1
| #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4 |
Definition at line 2039 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE
| #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3 |
Definition at line 2042 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK
Definition at line 2041 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_CPU_RST_MODE
| #define Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8 /* CPU Reset Mode */ |
Definition at line 2037 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_CPU_SLEEP
| #define Y2_ASF_HCU_CCSR_CPU_SLEEP BIT_26 /* CPU sleep status */ |
Definition at line 2031 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_CS_TO
| #define Y2_ASF_HCU_CCSR_CS_TO BIT_25 /* Clock Stretching Timeout */ |
Definition at line 2032 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_OS_PRSNT
| #define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */ |
Definition at line 2043 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_SET_IRQ_HCU
| #define Y2_ASF_HCU_CCSR_SET_IRQ_HCU BIT_16 /* Set IRQ_HCU */ |
Definition at line 2035 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_SET_SYNC_CPU
| #define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5 |
Definition at line 2038 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_SMBALERT_MONITOR
| #define Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27 /* SMBALERT pin monitor */ |
Definition at line 2030 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_UC_STATE_BASE
| #define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0 |
Definition at line 2046 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_UC_STATE_MSK
| #define Y2_ASF_HCU_CCSR_UC_STATE_MSK 3 |
Definition at line 2045 of file if_mskreg.h.
◆ Y2_ASF_HCU_CCSR_WDOG
| #define Y2_ASF_HCU_CCSR_WDOG BIT_24 /* Watchdog Reset */ |
Definition at line 2033 of file if_mskreg.h.
◆ Y2_ASF_HOST_IRQ
| #define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */ |
Definition at line 2054 of file if_mskreg.h.
◆ Y2_ASF_IRQ
| #define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */ |
Definition at line 2024 of file if_mskreg.h.
◆ Y2_ASF_OS_PRES
| #define Y2_ASF_OS_PRES BIT_4 /* ASF operation system present */ |
Definition at line 2020 of file if_mskreg.h.
◆ Y2_ASF_RESET
| #define Y2_ASF_RESET BIT_3 /* ASF system in reset state */ |
Definition at line 2021 of file if_mskreg.h.
◆ Y2_ASF_RUNNING
| #define Y2_ASF_RUNNING BIT_2 /* ASF system operational */ |
Definition at line 2022 of file if_mskreg.h.
◆ Y2_ASF_UC_STATE
| #define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */ |
Definition at line 2026 of file if_mskreg.h.
◆ Y2_B8_PREF_REGS
| #define Y2_B8_PREF_REGS 0x0450 |
Definition at line 584 of file if_mskreg.h.
◆ Y2_CFG_SPC
| #define Y2_CFG_SPC 0x1c00 |
Definition at line 779 of file if_mskreg.h.
◆ Y2_CLK_DIV_DIS
| #define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */ |
Definition at line 964 of file if_mskreg.h.
◆ Y2_CLK_DIV_ENA
| #define Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */ |
Definition at line 963 of file if_mskreg.h.
◆ Y2_CLK_DIV_VAL
| #define Y2_CLK_DIV_VAL | ( | x | ) | (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK) |
Definition at line 957 of file if_mskreg.h.
◆ Y2_CLK_DIV_VAL2_MSK
| #define Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */ |
Definition at line 959 of file if_mskreg.h.
◆ Y2_CLK_DIV_VAL_2
| #define Y2_CLK_DIV_VAL_2 | ( | x | ) | (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK) |
Definition at line 961 of file if_mskreg.h.
◆ Y2_CLK_DIV_VAL_MSK
| #define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */ |
Definition at line 956 of file if_mskreg.h.
◆ Y2_CLK_GAT_LNK1_DIS
| #define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */ |
Definition at line 939 of file if_mskreg.h.
◆ Y2_CLK_GAT_LNK2_DIS
| #define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */ |
Definition at line 935 of file if_mskreg.h.
◆ Y2_CLK_RUN_DIS
| #define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */ |
Definition at line 794 of file if_mskreg.h.
◆ Y2_CLK_RUN_ENA
| #define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */ |
Definition at line 793 of file if_mskreg.h.
◆ Y2_CLK_SEL_VAL_2
| #define Y2_CLK_SEL_VAL_2 | ( | x | ) | (SHIFT16(x) & Y2_CLK_SELECT2_MSK) |
Definition at line 962 of file if_mskreg.h.
◆ Y2_CLK_SELECT2_MSK
| #define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */ |
Definition at line 960 of file if_mskreg.h.
◆ Y2_COR_CLK_LNK1_DIS
| #define Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */ |
Definition at line 940 of file if_mskreg.h.
◆ Y2_COR_CLK_LNK2_DIS
| #define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */ |
Definition at line 936 of file if_mskreg.h.
◆ Y2_HW_WOL_OFF
| #define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */ |
Definition at line 790 of file if_mskreg.h.
◆ Y2_HW_WOL_ON
| #define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */ |
Definition at line 789 of file if_mskreg.h.
◆ Y2_HWE_ALL_MSK
| #define Y2_HWE_ALL_MSK |
Definition at line 887 of file if_mskreg.h.
◆ Y2_HWE_L1_MASK
| #define Y2_HWE_L1_MASK |
Definition at line 882 of file if_mskreg.h.
◆ Y2_HWE_L2_MASK
| #define Y2_HWE_L2_MASK |
Definition at line 884 of file if_mskreg.h.
◆ Y2_IS_ALL_MSK
| #define Y2_IS_ALL_MSK 0xef001f1f /* All Interrupt bits */ |
Definition at line 853 of file if_mskreg.h.
◆ Y2_IS_ASF
| #define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */ |
Definition at line 830 of file if_mskreg.h.
◆ Y2_IS_CHK_RX1
| #define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */ |
Definition at line 845 of file if_mskreg.h.
◆ Y2_IS_CHK_RX2
| #define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */ |
Definition at line 837 of file if_mskreg.h.
◆ Y2_IS_CHK_TXA1
| #define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */ |
Definition at line 847 of file if_mskreg.h.
◆ Y2_IS_CHK_TXA2
| #define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */ |
Definition at line 839 of file if_mskreg.h.
◆ Y2_IS_CHK_TXS1
| #define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */ |
Definition at line 846 of file if_mskreg.h.
◆ Y2_IS_CHK_TXS2
| #define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */ |
Definition at line 838 of file if_mskreg.h.
◆ Y2_IS_HW_ERR
| #define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */ |
Definition at line 828 of file if_mskreg.h.
◆ Y2_IS_IRQ_MAC1
| #define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */ |
Definition at line 844 of file if_mskreg.h.
◆ Y2_IS_IRQ_MAC2
| #define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */ |
Definition at line 836 of file if_mskreg.h.
◆ Y2_IS_IRQ_PHY1
| #define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */ |
Definition at line 843 of file if_mskreg.h.
◆ Y2_IS_IRQ_PHY2
| #define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */ |
Definition at line 835 of file if_mskreg.h.
◆ Y2_IS_IRQ_STAT
| #define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */ |
Definition at line 866 of file if_mskreg.h.
◆ Y2_IS_IRQ_SW
| #define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */ |
Definition at line 833 of file if_mskreg.h.
◆ Y2_IS_L1_MASK
| #define Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */ |
Definition at line 849 of file if_mskreg.h.
◆ Y2_IS_L2_MASK
| #define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */ |
Definition at line 851 of file if_mskreg.h.
◆ Y2_IS_MST_ERR
| #define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */ |
Definition at line 865 of file if_mskreg.h.
◆ Y2_IS_PAR_MAC1
| #define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */ |
Definition at line 877 of file if_mskreg.h.
◆ Y2_IS_PAR_MAC2
| #define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */ |
Definition at line 871 of file if_mskreg.h.
◆ Y2_IS_PAR_RD1
| #define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */ |
Definition at line 875 of file if_mskreg.h.
◆ Y2_IS_PAR_RD2
| #define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */ |
Definition at line 869 of file if_mskreg.h.
◆ Y2_IS_PAR_RX1
| #define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */ |
Definition at line 878 of file if_mskreg.h.
◆ Y2_IS_PAR_RX2
| #define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */ |
Definition at line 872 of file if_mskreg.h.
◆ Y2_IS_PAR_WR1
| #define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */ |
Definition at line 876 of file if_mskreg.h.
◆ Y2_IS_PAR_WR2
| #define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */ |
Definition at line 870 of file if_mskreg.h.
◆ Y2_IS_PCI_EXP
| #define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */ |
Definition at line 867 of file if_mskreg.h.
◆ Y2_IS_PCI_NEXP
| #define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */ |
Definition at line 868 of file if_mskreg.h.
◆ Y2_IS_PHY_QLNK
| #define Y2_IS_PHY_QLNK BIT_5 /* PHY Quick Link (Yukon Optima) */ |
Definition at line 842 of file if_mskreg.h.
◆ Y2_IS_POLL_CHK
| #define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */ |
Definition at line 831 of file if_mskreg.h.
◆ Y2_IS_PORT_A
| #define Y2_IS_PORT_A (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1) |
Definition at line 855 of file if_mskreg.h.
◆ Y2_IS_PORT_B
| #define Y2_IS_PORT_B (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2) |
Definition at line 857 of file if_mskreg.h.
◆ Y2_IS_PORT_MASK
| #define Y2_IS_PORT_MASK | ( | Port, | |
| Mask | |||
| ) | ((Mask) << (Port*8)) |
Definition at line 827 of file if_mskreg.h.
◆ Y2_IS_PSM_ACK
| #define Y2_IS_PSM_ACK BIT_7 /* PSM Ack (Yukon Optima) */ |
Definition at line 840 of file if_mskreg.h.
◆ Y2_IS_PTP_TIST
| #define Y2_IS_PTP_TIST BIT_6 /* PTP TIme Stamp (Yukon Optima) */ |
Definition at line 841 of file if_mskreg.h.
◆ Y2_IS_SENSOR
| #define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */ |
Definition at line 864 of file if_mskreg.h.
◆ Y2_IS_STAT_BMU
| #define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */ |
Definition at line 829 of file if_mskreg.h.
◆ Y2_IS_TCP_TXA1
| #define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */ |
Definition at line 880 of file if_mskreg.h.
◆ Y2_IS_TCP_TXA2
| #define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */ |
Definition at line 874 of file if_mskreg.h.
◆ Y2_IS_TCP_TXS1
| #define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */ |
Definition at line 879 of file if_mskreg.h.
◆ Y2_IS_TCP_TXS2
| #define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */ |
Definition at line 873 of file if_mskreg.h.
◆ Y2_IS_TIMINT
| #define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */ |
Definition at line 834 of file if_mskreg.h.
◆ Y2_IS_TIST_OV
| #define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */ |
Definition at line 863 of file if_mskreg.h.
◆ Y2_IS_TWSI_RDY
| #define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */ |
Definition at line 832 of file if_mskreg.h.
◆ Y2_LED_STAT_OFF
| #define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */ |
Definition at line 796 of file if_mskreg.h.
◆ Y2_LED_STAT_ON
| #define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */ |
Definition at line 795 of file if_mskreg.h.
◆ Y2_PCI_CLK_LNK1_DIS
| #define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */ |
Definition at line 941 of file if_mskreg.h.
◆ Y2_PCI_CLK_LNK2_DIS
| #define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */ |
Definition at line 937 of file if_mskreg.h.
◆ Y2_PEX_PHY_ADDR
| #define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */ |
Definition at line 490 of file if_mskreg.h.
◆ Y2_PEX_PHY_DATA
| #define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */ |
Definition at line 489 of file if_mskreg.h.
◆ Y2_PREF_Q_ADDR
| #define Y2_PREF_Q_ADDR | ( | Queue, | |
| Offs | |||
| ) | (Y2_B8_PREF_REGS + (Queue) + (Offs)) |
Definition at line 599 of file if_mskreg.h.
◆ Y2_STATUS_LNK1_INAC
| #define Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */ |
Definition at line 938 of file if_mskreg.h.
◆ Y2_STATUS_LNK2_INAC
| #define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */ |
Definition at line 934 of file if_mskreg.h.
◆ Y2_VAUX_AVAIL
| #define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */ |
Definition at line 788 of file if_mskreg.h.
◆ Y2_VMAIN_AVAIL
| #define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */ |
Definition at line 787 of file if_mskreg.h.
