50#define IDT_CMD_WRITE 1
51#define IDT_CMD_SEARCH 2
52#define IDT_CMD_LEARN 3
55#define IDT_LAR_ADR0 0x180006
56#define IDT_LAR_MODE144 0xffff0000
59#define IDT_SCR_ADR0 0x180000
60#define IDT_SSR0_ADR0 0x180002
61#define IDT_SSR1_ADR0 0x180004
64#define IDT_GMR_BASE_ADR0 0x180020
67#define IDT_DATARY_BASE_ADR0 0
68#define IDT_MSKARY_BASE_ADR0 0x80000
71#define IDT4_CMD_SEARCH144 3
72#define IDT4_CMD_WRITE 4
73#define IDT4_CMD_READ 5
76#define IDT4_SCR_ADR0 0x3
79#define IDT4_GMR_BASE0 0x10
80#define IDT4_GMR_BASE1 0x20
81#define IDT4_GMR_BASE2 0x30
84#define IDT4_DATARY_BASE_ADR0 0x1000000
85#define IDT4_MSKARY_BASE_ADR0 0x2000000
87#define MAX_WRITE_ATTEMPTS 5
89#define MAX_ROUTES 2048
126 CH_ERR(
adapter,
"MC5 timeout writing to TCAM address 0x%x\n", addr_lo);
131 u32 data_array_base,
u32 write_cmd,
151 for (i = 0; i < size72; i++)
152 if (
mc5_write(adap, data_array_base + (i << addr_shift),
157 for (i = 0; i < server_base; i++) {
159 if (
mc5_write(adap, mask_array_base + (i << addr_shift),
164 if (
mc5_write(adap, mask_array_base + (i << addr_shift),
172 for (; i < size72; i++)
173 if (
mc5_write(adap, mask_array_base + (i << addr_shift),
221 for (i = 0; i < 32; ++i) {
222 if (i >= 12 && i < 15)
275 for (i = 0; i < 7; ++i)
279 for (i = 0; i < 4; ++i)
330 unsigned int nroutes)
340 if (nroutes >
MAX_ROUTES || nroutes + nservers + nfilters > tcam_size)
350 CH_ERR(adap,
"TCAM reset timed out\n");
356 tcam_size - nroutes - nfilters);
358 tcam_size - nroutes - nfilters - nservers);
393 unsigned int n,
u32 *buf)
422#define MC5_INT_FATAL (F_PARITYERR | F_REQQPARERR | F_DISPQPARERR)
436 CH_ALERT(adap,
"MC5 parity error\n");
441 CH_ALERT(adap,
"MC5 request queue parity error\n");
446 CH_ALERT(adap,
"MC5 dispatch queue parity error\n");
477 static unsigned int tcam_part_size[] = {
478 64
K, 128
K, 256
K, 32
K
487 mc5->
mode = (
unsigned char) mode;
static __inline void t3_write_reg(adapter_t *adapter, uint32_t reg_addr, uint32_t val)
static __inline uint32_t t3_read_reg(adapter_t *adapter, uint32_t reg_addr)
void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val)
static int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity, int attempts, int delay)
void t3_fatal_err(adapter_t *adapter)
static void mc5_dbgi_mode_enable(const struct mc5 *mc5)
#define IDT_MSKARY_BASE_ADR0
#define MAX_WRITE_ATTEMPTS
#define IDT4_CMD_SEARCH144
static void dbgi_rd_rsp3(adapter_t *adapter, u32 *v1, u32 *v2, u32 *v3)
void __devinit t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode)
static int init_mask_data_array(struct mc5 *mc5, u32 mask_array_base, u32 data_array_base, u32 write_cmd, int addr_shift)
int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, u32 *buf)
static int mc5_write(adapter_t *adapter, u32 addr_lo, u32 cmd)
static int mc5_cmd_write(adapter_t *adapter, u32 cmd)
static int init_idt52100(struct mc5 *mc5)
#define IDT_GMR_BASE_ADR0
int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, unsigned int nroutes)
#define IDT_DATARY_BASE_ADR0
#define IDT4_MSKARY_BASE_ADR0
static int init_idt43102(struct mc5 *mc5)
void t3_mc5_intr_handler(struct mc5 *mc5)
static void mc5_dbgi_mode_disable(const struct mc5 *mc5)
#define IDT4_DATARY_BASE_ADR0
static void dbgi_wr_data3(adapter_t *adapter, u32 v1, u32 v2, u32 v3)
#define CH_ERR(adap, fmt,...)
#define CH_ALERT(adap, fmt,...)
#define A_MC5_DB_DBGI_CONFIG
#define A_MC5_DB_SYN_SRCH_CMD
#define A_MC5_DB_SYN_LRN_CMD
#define A_MC5_DB_PART_ID_INDEX
#define A_MC5_DB_AOPEN_SRCH_CMD
#define A_MC5_DB_FILTER_TABLE
#define A_MC5_DB_ELOOKUP_CMD
#define A_MC5_DB_ILOOKUP_CMD
#define A_MC5_DB_DBGI_REQ_ADDR0
#define A_MC5_DB_ROUTING_TABLE_INDEX
#define A_MC5_DB_ACK_LRN_CMD
#define A_MC5_DB_DBGI_REQ_ADDR2
#define A_MC5_DB_DBGI_RSP_DATA2
#define A_MC5_DB_DATA_WRITE_CMD
#define A_MC5_DB_POPEN_DATA_WR_CMD
#define A_MC5_DB_DBGI_RSP_DATA1
#define A_MC5_DB_DBGI_REQ_CMD
#define A_MC5_DB_DBGI_REQ_ADDR1
#define A_MC5_DB_DATA_READ_CMD
#define A_MC5_DB_ACK_SRCH_CMD
#define A_MC5_DB_RSP_LATENCY
#define A_MC5_DB_DBGI_RSP_STATUS
#define A_MC5_DB_INT_CAUSE
#define A_MC5_DB_DBGI_REQ_DATA1
#define A_MC5_DB_AOPEN_LRN_CMD
#define A_MC5_DB_POPEN_MASK_WR_CMD
#define A_MC5_DB_SERVER_INDEX
#define A_MC5_DB_DBGI_REQ_DATA2
#define A_MC5_DB_DBGI_RSP_DATA0
#define A_MC5_DB_DBGI_REQ_DATA0
struct adapter_params params
unsigned long nfa_srch_err
unsigned long del_act_empty
unsigned long dispq_parity_err
unsigned long unknown_cmd
unsigned long reqq_parity_err
unsigned long active_rgn_full
unsigned char parity_enabled