21#ifndef __ATH_HAL_BTCOEX_H__
22#define __ATH_HAL_BTCOEX_H__
73#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
74#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
76#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004
78#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008
80#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b
82#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09
83#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04
84#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09
85#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02
86#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06
88#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30
90#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666
92#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02
94#define HAL_BT_COEX_LOW_ACK_POWER 0x0
95#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f
162#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
163#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
164#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004
165#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008
166#define HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR 0x00000010
167#define HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX 0x00000020
169#define HAL_MCI_FLAG_DISABLE_TIMESTAMP 0x00000001
191#define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3
192#define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0
194#define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3
195#define MCI_GPM_COEX_MINOR_VERSION_WLAN 0
265#define MCI_GPM_INVALID_PROFILE_HANDLE 0xff
310#define MCI_GPM_RECYCLE(_p_gpm) \
312 *(((u_int32_t *)(_p_gpm)) + MCI_GPM_COEX_W_GPM_PAYLOAD) = MCI_GPM_RSVD_PATTERN32; \
314#define MCI_GPM_TYPE(_p_gpm) \
315 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
316#define MCI_GPM_OPCODE(_p_gpm) \
317 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
319#define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) \
321 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff; \
323#define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) \
325 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \
326 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff; \
328#define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
330#define MCI_NUM_BT_CHANNELS 79
332#define MCI_GPM_SET_CHANNEL_BIT(_p_gpm, _bt_chan) \
334 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \
335 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \
336 (_bt_chan / 8)) |= 1 << (_bt_chan & 7); \
340#define MCI_GPM_CLR_CHANNEL_BIT(_p_gpm, _bt_chan) \
342 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \
343 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \
344 (_bt_chan / 8)) &= ~(1 << (_bt_chan & 7)); \
348#define HAL_MCI_INTERRUPT_SW_MSG_DONE 0x00000001
349#define HAL_MCI_INTERRUPT_CPU_INT_MSG 0x00000002
350#define HAL_MCI_INTERRUPT_RX_CHKSUM_FAIL 0x00000004
351#define HAL_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008
352#define HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010
353#define HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020
354#define HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080
355#define HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100
356#define HAL_MCI_INTERRUPT_RX_MSG 0x00000200
357#define HAL_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400
358#define HAL_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000
359#define HAL_MCI_INTERRUPT_MSG_FAIL_MASK ( HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL | \
360 HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL | \
361 HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL | \
362 HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL )
364#define HAL_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001
365#define HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002
366#define HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004
367#define HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008
368#define HAL_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010
369#define HAL_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020
370#define HAL_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040
371#define HAL_MCI_INTERRUPT_RX_MSG_GPM 0x00000100
372#define HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200
373#define HAL_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400
374#define HAL_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800
375#define HAL_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000
376#define HAL_MCI_INTERRUPT_RX_MSG_MONITOR (HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \
377 HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO | \
378 HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK | \
379 HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO | \
380 HAL_MCI_INTERRUPT_RX_MSG_CONT_RST)
421#define HAL_MCI_STATE_DEBUG_REQ_BT_DEBUG 1
423#define HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002
424#define HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004
425#define HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008
426#define HAL_MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010
427#define HAL_MCI_BT_MCI_FLAGS_DEBUG 0x00000020
428#define HAL_MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040
429#define HAL_MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080
430#define HAL_MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100
431#define HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200
432#define HAL_MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400
433#define HAL_MCI_BT_MCI_FLAGS_EGRET_MODE 0x00000800
434#define HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE 0x00001000
435#define HAL_MCI_BT_MCI_FLAGS_OTHER 0x00010000
437#define HAL_MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde
454#define HAL_MCI_TOGGLE_BT_MCI_FLAGS \
455 ( HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR | \
456 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR | \
457 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD | \
458 HAL_MCI_BT_MCI_FLAGS_MCI_MODE )
460#define HAL_MCI_2G_FLAGS_CLEAR_MASK 0x00000000
461#define HAL_MCI_2G_FLAGS_SET_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS
462#define HAL_MCI_2G_FLAGS HAL_MCI_DEFAULT_BT_MCI_FLAGS
464#define HAL_MCI_5G_FLAGS_CLEAR_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS
465#define HAL_MCI_5G_FLAGS_SET_MASK 0x00000000
466#define HAL_MCI_5G_FLAGS (HAL_MCI_DEFAULT_BT_MCI_FLAGS & \
467 ~HAL_MCI_TOGGLE_BT_MCI_FLAGS)
469#define HAL_MCI_GPM_NOMORE 0
470#define HAL_MCI_GPM_MORE 1
471#define HAL_MCI_GPM_INVALID 0xffffffff
473#define ATH_AIC_MAX_BT_CHANNEL 79
479#define ATH_MCI_CONFIG_CONCUR_TX 0x00000003
480#define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004
481#define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008
482#define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010
483#define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020
484#define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040
485#define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080
486#define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700
487#define ATH_MCI_CONFIG_AGGR_THRESH_S 8
488#define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800
489#define ATH_MCI_CONFIG_CLK_DIV 0x00003000
490#define ATH_MCI_CONFIG_CLK_DIV_S 12
491#define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000
492#define ATH_MCI_CONFIG_DISABLE_AIC 0x00008000
493#define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN 0x007f0000
494#define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN_S 16
495#define ATH_MCI_CONFIG_NO_QUIET_ACK 0x00800000
496#define ATH_MCI_CONFIG_NO_QUIET_ACK_S 23
497#define ATH_MCI_CONFIG_ANT_ARCH 0x07000000
498#define ATH_MCI_CONFIG_ANT_ARCH_S 24
499#define ATH_MCI_CONFIG_FORCE_QUIET_ACK 0x08000000
500#define ATH_MCI_CONFIG_FORCE_QUIET_ACK_S 27
501#define ATH_MCI_CONFIG_FORCE_2CHAIN_ACK 0x10000000
502#define ATH_MCI_CONFIG_MCI_STAT_DBG 0x20000000
503#define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000
504#define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000
506#define ATH_MCI_CONFIG_MCI_OBS_MASK ( ATH_MCI_CONFIG_MCI_OBS_MCI | \
507 ATH_MCI_CONFIG_MCI_OBS_TXRX | \
508 ATH_MCI_CONFIG_MCI_OBS_BT )
509#define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F
511#define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_NON_SHARED 0x00
512#define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED 0x01
513#define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_NON_SHARED 0x02
514#define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED 0x03
515#define ATH_MCI_ANT_ARCH_3_ANT 0x04
517#define MCI_ANT_ARCH_PA_LNA_SHARED(c) \
518 ((MS(c, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED) || \
519 (MS(c, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED))
521#define ATH_MCI_CONCUR_TX_SHARED_CHN 0x01
522#define ATH_MCI_CONCUR_TX_UNSHARED_CHN 0x02
523#define ATH_MCI_CONCUR_TX_DEBUG 0x03
enum mci_gpm_coex_bt_status_type MCI_GPM_COEX_BT_STATUS_TYPE_T
enum mci_gpm_coex_query_type MCI_GPM_COEX_QUERY_TYPE_T
enum mci_bt_state MCI_BT_STATE_T
@ HAL_BT_COEX_CFG_2WIRE_CH1
@ HAL_BT_COEX_CFG_2WIRE_2CH
@ HAL_BT_COEX_CFG_2WIRE_CH0
mci_gpm_coex_profile_role
@ MCI_GPM_COEX_PROFILE_SLAVE
@ MCI_GPM_COEX_PROFILE_MASTER
@ MCI_GPM_COEX_QUERY_BT_DEBUG
@ MCI_GPM_COEX_QUERY_BT_ALL_INFO
@ MCI_GPM_COEX_QUERY_WLAN_ALL_INFO
@ MCI_GPM_COEX_QUERY_BT_TOPOLOGY
@ MCI_GPM_COEX_HALT_BT_GPM
@ MCI_GPM_COEX_BT_UPDATE_FLAGS
@ MCI_GPM_COEX_BT_PROFILE_INFO
@ MCI_GPM_COEX_VERSION_QUERY
@ MCI_GPM_COEX_VERSION_RESPONSE
@ MCI_GPM_COEX_WLAN_CHANNELS
@ MCI_GPM_COEX_STATUS_QUERY
@ MCI_GPM_COEX_BT_STATUS_UPDATE
enum mci_gpm_coex_opcode MCI_GPM_COEX_OPCODE_T
mci_gpm_coex_bt_status_state
@ MCI_GPM_COEX_BT_CRITICAL_STATUS
@ MCI_GPM_COEX_BT_NORMAL_STATUS
mci_gpm_coex_bt_status_type
@ MCI_GPM_COEX_BT_LINK_STATUS
@ MCI_GPM_COEX_BT_NONLINK_STATUS
mci_gpm_coex_profile_type
@ MCI_GPM_COEX_PROFILE_HID
@ MCI_GPM_COEX_PROFILE_UNKNOWN
@ MCI_GPM_COEX_PROFILE_BNEP
@ MCI_GPM_COEX_PROFILE_VOICE
@ MCI_GPM_COEX_PROFILE_MAX
@ MCI_GPM_COEX_PROFILE_RFCOMM
@ MCI_GPM_COEX_PROFILE_A2DP
enum mci_gpm_subtype MCI_GPM_SUBTYPE_T
enum mci_gpm_coex_profile_role MCI_GPM_COEX_PROFILE_ROLE_T
enum mci_gpm_coex_bt_status_state MCI_GPM_COEX_BT_STATUS_STATE_T
enum mci_gpm_coex_bt_updata_flags_op MCI_GPM_COEX_BT_FLAGS_OP_T
enum mci_message_header MCI_MESSAGE_HEADER
@ MCI_GPM_COEX_BT_GPM_UNHALT
@ MCI_GPM_COEX_BT_GPM_HALT
mci_gpm_coex_bt_updata_flags_op
@ MCI_GPM_COEX_BT_FLAGS_SET
@ MCI_GPM_COEX_BT_FLAGS_READ
@ MCI_GPM_COEX_BT_FLAGS_CLEAR
@ HAL_BT_COEX_MODE_UNSLOTTED
@ HAL_BT_COEX_MODE_SLOTTED
@ HAL_BT_COEX_MODE_LEGACY
@ HAL_BT_COEX_MODE_DISALBED
enum mci_gpm_coex_profile_type MCI_GPM_COEX_PROFILE_TYPE_T
enum mci_gpm_coex_profile_state MCI_GPM_COEX_PROFILE_STATE_T
HAL_BT_COEX_SET_PARAMETER
@ HAL_BT_COEX_MCI_MAX_TX_PWR
@ HAL_BT_COEX_ANTENNA_DIVERSITY
@ HAL_BT_COEX_MCI_FTP_STOMP_RX
@ HAL_BT_COEX_LOWER_TX_PWR
@ HAL_BT_COEX_SET_ACK_PWR
mci_gpm_coex_profile_state
@ MCI_GPM_COEX_PROFILE_STATE_END
@ MCI_GPM_COEX_PROFILE_STATE_START
enum mci_state_type HAL_MCI_STATE_TYPE
@ MCI_GPM_WLAN_CAL_W_SEQUENCE
@ MCI_GPM_COEX_W_GPM_PAYLOAD
@ MCI_GPM_COEX_B_BT_FLAGS_OP
@ MCI_GPM_COEX_B_PROFILE_RATE
@ MCI_GPM_COEX_B_PROFILE_VOTYPE
@ MCI_GPM_COEX_B_GPM_TYPE
@ MCI_GPM_COEX_B_PROFILE_STATE
@ MCI_GPM_COEX_B_CHANNEL_MAP
@ MCI_GPM_COEX_B_PROFILE_LINKID
@ MCI_GPM_COEX_B_PROFILE_TYPE
@ MCI_GPM_COEX_H_PROFILE_T
@ MCI_GPM_COEX_B_MAJOR_VERSION
@ MCI_GPM_COEX_B_GPM_OPCODE
@ MCI_GPM_COEX_B_STATUS_STATE
@ MCI_GPM_COEX_B_PROFILE_W
@ MCI_GPM_COEX_B_BT_BITMAP
@ MCI_GPM_COEX_B_STATUS_LINKID
@ MCI_GPM_COEX_B_STATUS_TYPE
@ MCI_GPM_COEX_B_WLAN_BITMAP
@ MCI_GPM_COEX_W_BT_FLAGS
@ MCI_GPM_COEX_B_PROFILE_ROLE
@ MCI_GPM_COEX_B_HALT_STATE
@ MCI_GPM_COEX_B_PROFILE_A
@ MCI_GPM_COEX_B_MINOR_VERSION
@ HAL_BT_COEX_STOMP_ALL_FORCE
@ HAL_BT_COEX_STOMP_AUDIO
@ HAL_BT_COEX_STOMP_LOW_FORCE
@ HAL_MCI_STATE_CONT_PRIORITY
@ HAL_MCI_STATE_INIT_GPM_OFFSET
@ HAL_MCI_STATE_RECOVER_RX
@ HAL_MCI_STATE_RESET_REQ_WAKE
@ HAL_MCI_STATE_LAST_SCHD_MSG_OFFSET
@ HAL_MCI_STATE_LAST_GPM_OFFSET
@ HAL_MCI_STATE_NEXT_GPM_OFFSET
@ HAL_MCI_STATE_SEND_WLAN_CHANNELS
@ HAL_MCI_STATE_SET_BT_SLEEP
@ HAL_MCI_STATE_NEED_FTP_STOMP
@ HAL_MCI_STATE_SET_CONCUR_TX_PRI
@ HAL_MCI_STATE_SEND_VERSION_QUERY
@ HAL_MCI_STATE_CONT_TXRX
@ HAL_MCI_STATE_SEND_STATUS_QUERY
@ HAL_MCI_STATE_SEND_WLAN_COEX_VERSION
@ HAL_MCI_STATE_NEED_FLUSH_BT_INFO
@ HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX
@ HAL_MCI_STATE_SET_BT_COEX_VERSION
@ HAL_MCI_STATE_NEED_TUNING
@ HAL_MCI_STATE_CONT_RSSI_POWER
@ HAL_MCI_STATE_SET_BT_CAL_START
@ HAL_MCI_STATE_SET_BT_CAL
@ HAL_MCI_STATE_REMOTE_SLEEP
@ HAL_MCI_STATE_SET_BT_AWAKE
enum mci_gpm_coex_halt_bt_gpm MCI_GPM_COEX_HALT_BT_GPM_T
HAL_BOOL bt_rxclear_polarity
u_int8_t bt_priority_time
HAL_BOOL bt_quiet_collision
u_int8_t bt_first_slot_time
HAL_BOOL bt_txframe_extend
HAL_BOOL bt_txstate_extend
u_int8_t bt_gpio_bt_priority
u_int8_t bt_active_polarity
u_int8_t bt_gpio_bt_active
u_int8_t bt_gpio_wlan_active