21#ifndef _ATH_AH_EEPROM_V3_H_
22#define _ATH_AH_EEPROM_V3_H_
27#define AR_EEPROM_RFSILENT 0x0f
28#define AR_EEPROM_MAC(i) (0x1d+(i))
29#define AR_EEPROM_MAGIC 0x3d
30#define AR_EEPROM_PROTECT 0x3f
31#define AR_EEPROM_PROTECT_PCIE 0x01
32#define AR_EEPROM_REG_DOMAIN 0xbf
33#define AR_EEPROM_ATHEROS_BASE 0xc0
34#define AR_EEPROM_ATHEROS(i) (AR_EEPROM_ATHEROS_BASE+(i))
35#define AR_EEPROM_ATHEROS_MAX (0x400-AR_EEPROM_ATHEROS_BASE)
36#define AR_EEPROM_VERSION AR_EEPROM_ATHEROS(1)
39#define AR_EEPROM_SIZE_LOWER 0x1b
40#define AR_EEPROM_SIZE_UPPER 0x1c
41#define AR_EEPROM_SIZE_UPPER_MASK 0xfff0
42#define AR_EEPROM_SIZE_UPPER_SHIFT 4
43#define AR_EEPROM_SIZE_ENDLOC_SHIFT 12
44#define AR_EEPROM_ATHEROS_MAX_LOC 0x400
45#define AR_EEPROM_ATHEROS_MAX_OFF (AR_EEPROM_ATHEROS_MAX_LOC-AR_EEPROM_ATHEROS_BASE)
48#define AR_EEPROM_REG_CAPABILITIES_OFFSET 0xCA
49#define AR_EEPROM_REG_CAPABILITIES_OFFSET_PRE4_0 0xCF
52#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
53#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
54#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
55#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
56#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
57#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
60#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
61#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
66#define AR_EEPROM_SERIAL_NUM_OFFSET 0xB0
67#define AR_EEPROM_SERIAL_NUM_SIZE 12
68#define AR_EEPROM_CAPABILITIES_OFFSET 0xC9
70#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
71#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
72#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
73#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
74#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
75#define AR_EEPROM_EEPCAP_MAXQCU_S 4
76#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
77#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
78#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
87#define GROUPS_OFFSET3_2 0x100
88#define GROUPS_OFFSET3_3 0x150
90#define GROUP1_OFFSET 0x0
91#define GROUP2_OFFSET 0x5
92#define GROUP3_OFFSET 0x37
93#define GROUP4_OFFSET 0x46
94#define GROUP5_OFFSET 0x55
95#define GROUP6_OFFSET 0x65
96#define GROUP7_OFFSET 0x69
97#define GROUP8_OFFSET 0x6f
100#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
101#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
102#define AR_EEPROM_RFSILENT_POLARITY 0x0002
103#define AR_EEPROM_RFSILENT_POLARITY_S 1
106#define AR_EEPROM_PROTECT_RP_0_31 0x0001
107#define AR_EEPROM_PROTECT_WP_0_31 0x0002
108#define AR_EEPROM_PROTECT_RP_32_63 0x0004
109#define AR_EEPROM_PROTECT_WP_32_63 0x0008
110#define AR_EEPROM_PROTECT_RP_64_127 0x0010
111#define AR_EEPROM_PROTECT_WP_64_127 0x0020
112#define AR_EEPROM_PROTECT_RP_128_191 0x0040
113#define AR_EEPROM_PROTECT_WP_128_191 0x0080
114#define AR_EEPROM_PROTECT_RP_192_207 0x0100
115#define AR_EEPROM_PROTECT_WP_192_207 0x0200
116#define AR_EEPROM_PROTECT_RP_208_223 0x0400
117#define AR_EEPROM_PROTECT_WP_208_223 0x0800
118#define AR_EEPROM_PROTECT_RP_224_239 0x1000
119#define AR_EEPROM_PROTECT_WP_224_239 0x2000
120#define AR_EEPROM_PROTECT_RP_240_255 0x4000
121#define AR_EEPROM_PROTECT_WP_240_255 0x8000
123#define AR_EEPROM_MODAL_SPURS 5
124#define AR_SPUR_5413_1 1640
125#define AR_SPUR_5413_2 1200
139#define NUM_11A_EEPROM_CHANNELS 10
140#define NUM_2_4_EEPROM_CHANNELS 3
141#define NUM_PCDAC_VALUES 11
142#define NUM_TEST_FREQUENCIES 8
144#define NUM_INTERCEPTS 11
145#define FREQ_MASK 0x7f
146#define FREQ_MASK_3_3 0xff
147#define PCDAC_MASK 0x3f
148#define POWER_MASK 0x3f
149#define NON_EDGE_FLAG_MASK 0x40
150#define CHANNEL_POWER_INFO 8
151#define OBDB_UNSET 0xffff
152#define CHANNEL_UNUSED 0xff
153#define SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
159#define PWR_TABLE_SIZE 64
160#define MAX_RATE_POWER 63
164#define NUM_CTLS_3_3 32
165#define NUM_CTLS_MAX NUM_CTLS_3_3
221#define NUM_XPD_PER_CHANNEL 4
222#define NUM_POINTS_XPD0 4
223#define NUM_POINTS_XPD3 3
224#define IDEAL_10dB_INTERCEPT_2G 35
225#define IDEAL_10dB_INTERCEPT_5G 55
227#define TENX_OFDM_CCK_DELTA_INIT 15
228#define TENX_CH14_FILTER_CCK_DELTA_INIT 15
229#define CCK_OFDM_GAIN_DELTA 15
231#define NUM_TARGET_POWER_LOCATIONS_11B 4
232#define NUM_TARGET_POWER_LOCATIONS_11G 6
281#define NUM_2_4_EEPROM_CHANNELS_2413 4
282#define NUM_11A_EEPROM_CHANNELS_2413 10
283#define PWR_TABLE_SIZE_2413 128
286#define MAX_NUM_PDGAINS_PER_CHANNEL 4
287#define NUM_PDGAINS_PER_CHANNEL 2
288#define NUM_POINTS_LAST_PDGAIN 5
289#define NUM_POINTS_OTHER_PDGAINS 4
290#define XPD_GAIN1_GEN5 3
291#define XPD_GAIN2_GEN5 1
292#define MAX_PWR_RANGE_IN_HALF_DB 64
293#define PD_GAIN_BOUNDARY_STRETCH_IN_HALF_DB 4
357 int8_t ee_antennaGainMax[2];
370 uint16_t ee_switchSettling[3];
371 uint16_t ee_txrxAtten[3];
372 uint16_t ee_txEndToXLNAOn[3];
373 uint16_t ee_thresh62[3];
374 uint16_t ee_txEndToXPAOff[3];
375 uint16_t ee_txFrameToXPAOn[3];
376 int8_t ee_adcDesiredSize[3];
377 int8_t ee_pgaDesiredSize[3];
378 int16_t ee_noiseFloorThresh[3];
379 uint16_t ee_xlnaGain[3];
380 uint16_t ee_xgain[3];
382 uint16_t ee_antennaControl[11][3];
383 uint16_t ee_falseDetectBackoff[3];
384 uint16_t ee_gainI[3];
385 uint16_t ee_rxtxMargin[3];
393 uint16_t ee_switchSettlingTurbo[2];
394 uint16_t ee_txrxAttenTurbo[2];
395 int8_t ee_adcDesiredSizeTurbo[2];
396 int8_t ee_pgaDesiredSizeTurbo[2];
397 uint16_t ee_rxtxMarginTurbo[2];
414 uint16_t ee_ob2GHz[2];
415 uint16_t ee_db2GHz[2];
418 uint16_t ee_iqCalI[2];
419 uint16_t ee_iqCalQ[2];
455#define ee_numTargetPwr_11a ee_tpow.numTargetPwr_11a
456#define ee_trgtPwr_11a ee_tpow.trgtPwr_11a
457#define ee_numTargetPwr_11g ee_tpow.numTargetPwr_11g
458#define ee_trgtPwr_11g ee_tpow.trgtPwr_11g
459#define ee_numTargetPwr_11b ee_tpow.numTargetPwr_11b
460#define ee_trgtPwr_11b ee_tpow.trgtPwr_11b
461#define ee_modePowerArray5112 ee_u.eu_modePowerArray5112
462#define ee_rawDataset2413 ee_u.eu_rawDataset2413
#define MAX_NUM_PDGAINS_PER_CHANNEL
#define NUM_XPD_PER_CHANNEL
#define NUM_POINTS_LAST_PDGAIN
struct cornerCalInfo CORNER_CAL_INFO
struct trgtPowerAllModes TRGT_POWER_ALL_MODES
#define AR_EEPROM_MODAL_SPURS
#define NUM_2_4_EEPROM_CHANNELS
#define NUM_11A_EEPROM_CHANNELS_2413
struct dataPerChannel DATA_PER_CHANNEL
struct trgtPowerInfo TRGT_POWER_INFO
#define NUM_11A_EEPROM_CHANNELS
struct pcdacsEeprom PCDACS_EEPROM
struct fullPcdacStruct FULL_PCDAC_STRUCT
#define NUM_TEST_FREQUENCIES
EXPN_DATA_PER_CHANNEL_5112 * pDataPerChannel
uint8_t ee_cckOfdmPwrDelta
uint16_t ee_turbo5Disable
uint16_t ee_eepMap2PowerCalStart
CORNER_CAL_INFO ee_cornerCal
uint16_t ee_xrTargetPower5
TRGT_POWER_ALL_MODES ee_tpow
uint16_t ee_turbo2Disable
uint16_t ee_scaledCh14FilterCckDelta
uint16_t ee_turbo2WMaxPower5
uint16_t ee_turbo2WMaxPower2
uint16_t ee_numChannels11a
uint8_t ee_exist32kHzCrystal
uint16_t ee_cckOfdmGainDelta
uint16_t ee_numChannels2_4
uint16_t ee_targetPowersStart
uint16_t ee_xrTargetPower2
uint16_t ee_xtnd5GSupport
int16_t PwrValues[NUM_PCDAC_VALUES]
uint16_t PcdacValues[NUM_PCDAC_VALUES]
const uint16_t * pChannelList
const DATA_PER_CHANNEL * pDataPerChannel
uint16_t numTargetPwr_11b
TRGT_POWER_INFO trgtPwr_11b[2]
uint16_t numTargetPwr_11a
TRGT_POWER_INFO trgtPwr_11a[NUM_TEST_FREQUENCIES]
uint16_t numTargetPwr_11g
TRGT_POWER_INFO trgtPwr_11g[3]