|
| #define | UMCS7840_MAX_PORTS 4 |
| |
| #define | UMCS7840_READ_LENGTH 1 /* bytes */ |
| |
| #define | UMCS7840_CTRL_TIMEOUT 500 /* ms */ |
| |
| #define | MCS7840_RDREQ 0x0d |
| |
| #define | MCS7840_WRREQ 0x0e |
| |
| #define | MCS7840_EEPROM_RW_WVALUE 0x0900 |
| |
| #define | MCS7840_DEV_REG_SP1 0x00 /* Options for for UART 1, R/W */ |
| |
| #define | MCS7840_DEV_REG_CONTROL1 |
| |
| #define | MCS7840_DEV_REG_PINPONGHIGH |
| |
| #define | MCS7840_DEV_REG_PINPONGLOW |
| |
| #define | MCS7840_DEV_REG_GPIO |
| |
| #define | MCS7840_DEV_REG_SP2 0x08 /* Options for for UART 2, R/W */ |
| |
| #define | MCS7840_DEV_REG_CONTROL2 |
| |
| #define | MCS7840_DEV_REG_SP3 0x0a /* Options for for UART 3, R/W */ |
| |
| #define | MCS7840_DEV_REG_CONTROL3 |
| |
| #define | MCS7840_DEV_REG_SP4 0x0c /* Options for for UART 4, R/W */ |
| |
| #define | MCS7840_DEV_REG_CONTROL4 |
| |
| #define | MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWN1 0x0f /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */ |
| |
| #define | MCS7840_DEV_REG_CLOCK_MUX |
| |
| #define | MCS7840_DEV_REG_UNKNOWN2 0x11 /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_CLOCK_SELECT12 |
| |
| #define | MCS7840_DEV_REG_CLOCK_SELECT34 |
| |
| #define | MCS7840_DEV_REG_UNKNOWN3 0x15 /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWN4 0x1f /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWN5 0x20 /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWN6 0x21 /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWN7 0x22 /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWN8 0x23 /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWN9 0x24 /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWNA 0x25 /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWNB 0x26 /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWNC 0x27 /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWND 0x28 /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWNE 0x29 /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_UNKNOWNF 0x2a /* NOT MENTIONED AND NOT USED */ |
| |
| #define | MCS7840_DEV_REG_MODE |
| |
| #define | MCS7840_DEV_REG_SP1_ICG |
| |
| #define | MCS7840_DEV_REG_SP2_ICG |
| |
| #define | MCS7840_DEV_REG_SP3_ICG |
| |
| #define | MCS7840_DEV_REG_SP4_ICG |
| |
| #define | MCS7840_DEV_REG_RX_SAMPLING12 |
| |
| #define | MCS7840_DEV_REG_RX_SAMPLING34 |
| |
| #define | MCS7840_DEV_REG_BI_FIFO_STAT1 |
| |
| #define | MCS7840_DEV_REG_BO_FIFO_STAT1 |
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| #define | MCS7840_DEV_REG_BI_FIFO_STAT2 |
| |
| #define | MCS7840_DEV_REG_BO_FIFO_STAT2 |
| |
| #define | MCS7840_DEV_REG_BI_FIFO_STAT3 |
| |
| #define | MCS7840_DEV_REG_BO_FIFO_STAT3 |
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| #define | MCS7840_DEV_REG_BI_FIFO_STAT4 |
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| #define | MCS7840_DEV_REG_BO_FIFO_STAT4 |
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| #define | MCS7840_DEV_REG_ZERO_PERIOD1 |
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| #define | MCS7840_DEV_REG_ZERO_PERIOD2 |
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| #define | MCS7840_DEV_REG_ZERO_PERIOD3 |
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| #define | MCS7840_DEV_REG_ZERO_PERIOD4 |
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| #define | MCS7840_DEV_REG_ZERO_ENABLE |
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| #define | MCS7840_DEV_REG_THR_VAL_LOW1 |
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| #define | MCS7840_DEV_REG_THR_VAL_HIGH1 |
| |
| #define | MCS7840_DEV_REG_THR_VAL_LOW2 |
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| #define | MCS7840_DEV_REG_THR_VAL_HIGH2 |
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| #define | MCS7840_DEV_REG_THR_VAL_LOW3 |
| |
| #define | MCS7840_DEV_REG_THR_VAL_HIGH3 |
| |
| #define | MCS7840_DEV_REG_THR_VAL_LOW4 |
| |
| #define | MCS7840_DEV_REG_THR_VAL_HIGH4 |
| |
| #define | MCS7840_DEV_SPx_LOOP_PIPES |
| |
| #define | MCS7840_DEV_SPx_SKIP_ERR_DATA |
| |
| #define | MCS7840_DEV_SPx_RESET_OUT_FIFO 0x04 /* Reset Bulk-Out FIFO */ |
| |
| #define | MCS7840_DEV_SPx_RESET_IN_FIFO 0x08 /* Reset Bulk-In FIFO */ |
| |
| #define | MCS7840_DEV_SPx_CLOCK_MASK |
| |
| #define | MCS7840_DEV_SPx_CLOCK_X1 |
| |
| #define | MCS7840_DEV_SPx_CLOCK_X2 |
| |
| #define | MCS7840_DEV_SPx_CLOCK_X35 |
| |
| #define | MCS7840_DEV_SPx_CLOCK_X4 |
| |
| #define | MCS7840_DEV_SPx_CLOCK_X7 |
| |
| #define | MCS7840_DEV_SPx_CLOCK_X8 |
| |
| #define | MCS7840_DEV_SPx_CLOCK_24MHZ |
| |
| #define | MCS7840_DEV_SPx_CLOCK_48MHZ |
| |
| #define | MCS7840_DEV_SPx_CLOCK_SHIFT |
| |
| #define | MCS7840_DEV_SPx_UART_RESET 0x80 /* Reset UART */ |
| |
| #define | MCS7840_DEV_CONTROLx_HWFC |
| |
| #define | MCS7840_DEV_CONTROLx_UNUNSED1 0x02 /* Reserved */ |
| |
| #define | MCS7840_DEV_CONTROLx_CTS_ENABLE |
| |
| #define | MCS7840_DEV_CONTROLx_UNUSED2 |
| |
| #define | MCS7840_DEV_CONTROL1_DRIVER_DONE |
| |
| #define | MCS7840_DEV_CONTROLx_RX_NEGATE |
| |
| #define | MCS7840_DEV_CONTROLx_RX_DISABLE |
| |
| #define | MCS7840_DEV_CONTROLx_FSM_CONTROL |
| |
| #define | MCS7840_DEV_CONTROLx_UNUSED3 0x80 /* Reserved */ |
| |
| #define | MCS7840_DEV_PINPONGHIGH_MULT |
| |
| #define | MCS7840_DEV_PINPONGLOW_BITS |
| |
| #define | MCS7840_DEV_GPIO_4PORTS |
| |
| #define | MCS7840_DEV_GPIO_GPIO_0 0x01 /* The same as above */ |
| |
| #define | MCS7840_DEV_GPIO_GPIO_1 0x02 /* GPIO_1 data */ |
| |
| #define | MCS7840_DEV_PLL_DIV_M_BITS |
| |
| #define | MCS7840_DEV_PLL_DIV_M_MASK 0x3f /* Mask for M divider */ |
| |
| #define | MCS7840_DEV_PLL_DIV_M_MIN |
| |
| #define | MCS7840_DEV_PLL_DIV_M_DEF 1 /* Default value for M */ |
| |
| #define | MCS7840_DEV_PLL_DIV_M_MAX 63 /* Maximum value for M */ |
| |
| #define | MCS7840_DEV_PLL_DIV_N_BITS |
| |
| #define | MCS7840_DEV_PLL_DIV_N_MASK 0x3f /* Mask for N divider */ |
| |
| #define | MCS7840_DEV_PLL_DIV_N_MIN |
| |
| #define | MCS7840_DEV_PLL_DIV_N_DEF 8 /* Default value for N */ |
| |
| #define | MCS7840_DEV_PLL_DIV_N_MAX 63 /* Maximum value for N */ |
| |
| #define | MCS7840_DEV_CLOCK_MUX_INPUTMASK |
| |
| #define | MCS7840_DEV_CLOCK_MUX_IN12MHZ 0x00 /* 12Mhz PLL input, default */ |
| |
| #define | MCS7840_DEV_CLOCK_MUX_INEXTRN |
| |
| #define | MCS7840_DEV_CLOCK_MUX_INRSV1 0x02 /* Reserved */ |
| |
| #define | MCS7840_DEV_CLOCK_MUX_INRSV2 0x03 /* Reserved */ |
| |
| #define | MCS7840_DEV_CLOCK_MUX_PLLHIGH |
| |
| #define | MCS7840_DEV_CLOCK_MUX_INTRFIFOS |
| |
| #define | MCS7840_DEV_CLOCK_MUX_RESERVED1 0x10 /* Unused */ |
| |
| #define | MCS7840_DEV_CLOCK_MUX_RESERVED2 0x20 /* Unused */ |
| |
| #define | MCS7840_DEV_CLOCK_MUX_RESERVED3 0x40 /* Unused */ |
| |
| #define | MCS7840_DEV_CLOCK_MUX_RESERVED4 0x80 /* Unused */ |
| |
| #define | MCS7840_DEV_CLOCK_SELECT1_MASK |
| |
| #define | MCS7840_DEV_CLOCK_SELECT1_SHIFT |
| |
| #define | MCS7840_DEV_CLOCK_SELECT2_MASK |
| |
| #define | MCS7840_DEV_CLOCK_SELECT2_SHIFT |
| |
| #define | MCS7840_DEV_CLOCK_SELECT3_MASK |
| |
| #define | MCS7840_DEV_CLOCK_SELECT3_SHIFT |
| |
| #define | MCS7840_DEV_CLOCK_SELECT4_MASK |
| |
| #define | MCS7840_DEV_CLOCK_SELECT4_SHIFT |
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| #define | MCS7840_DEV_CLOCK_SELECT_STD |
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| #define | MCS7840_DEV_CLOCK_SELECT_30MHZ 0x01 /* 30Mhz */ |
| |
| #define | MCS7840_DEV_CLOCK_SELECT_96MHZ 0x02 /* 96Mhz direct */ |
| |
| #define | MCS7840_DEV_CLOCK_SELECT_120MHZ 0x03 /* 120Mhz */ |
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| #define | MCS7840_DEV_CLOCK_SELECT_PLL |
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| #define | MCS7840_DEV_CLOCK_SELECT_EXT |
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| #define | MCS7840_DEV_CLOCK_SELECT_RES1 0x06 /* Unused */ |
| |
| #define | MCS7840_DEV_CLOCK_SELECT_RES2 0x07 /* Unused */ |
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| #define | MCS7840_DEV_MODE_RESERVED1 0x01 /* Unused */ |
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| #define | MCS7840_DEV_MODE_RESET |
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| #define | MCS7840_DEV_MODE_SER_PRSNT |
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| #define | MCS7840_DEV_MODE_PLLBYPASS |
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| #define | MCS7840_DEV_MODE_PORBYPASS |
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| #define | MCS7840_DEV_MODE_SELECT24S |
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| #define | MCS7840_DEV_MODE_EEPROMWR |
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| #define | MCS7840_DEV_MODE_IRDA |
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| #define | MCS7840_DEV_SPx_ICG_DEF |
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| #define | MCS7840_DEV_RX_SAMPLING1_MASK |
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| #define | MCS7840_DEV_RX_SAMPLING1_SHIFT |
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| #define | MCS7840_DEV_RX_SAMPLING2_MASK |
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| #define | MCS7840_DEV_RX_SAMPLING2_SHIFT |
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| #define | MCS7840_DEV_RX_SAMPLING3_MASK |
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| #define | MCS7840_DEV_RX_SAMPLING3_SHIFT |
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| #define | MCS7840_DEV_RX_SAMPLING4_MASK |
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| #define | MCS7840_DEV_RX_SAMPLING4_SHIFT |
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| #define | MCS7840_DEV_RX_SAMPLINGx_MIN 0 /* Max for any RX Sampling */ |
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| #define | MCS7840_DEV_RX_SAMPLINGx_DEF |
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| #define | MCS7840_DEV_RX_SAMPLINGx_MAX 15 /* Min for any RX Sampling */ |
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| #define | MCS7840_DEV_ZERO_PERIODx_DEF |
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| #define | MCS7840_DEV_ZERO_ENABLE_PORT1 |
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| #define | MCS7840_DEV_ZERO_ENABLE_PORT2 |
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| #define | MCS7840_DEV_ZERO_ENABLE_PORT3 |
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| #define | MCS7840_DEV_ZERO_ENABLE_PORT4 |
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| #define | MCS7840_DEV_THR_VAL_HIGH_MASK 0x01 /* Only one bit is used */ |
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| #define | MCS7840_DEV_THR_VAL_HIGH_MUL 256 /* This one bit is means "256" */ |
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| #define | MCS7840_DEV_THR_VAL_HIGH_SHIFT 8 /* This one bit is means "256" */ |
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| #define | MCS7840_DEV_THR_VAL_HIGH_ENABLE 0x80 /* Enable threshold */ |
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| #define | MCS7840_DEV_REG_DCR0_1 |
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| #define | MCS7840_DEV_REG_DCR1_1 |
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| #define | MCS7840_DEV_REG_DCR2_1 |
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| #define | MCS7840_DEV_REG_DCR0_2 |
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| #define | MCS7840_DEV_REG_DCR1_2 |
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| #define | MCS7840_DEV_REG_DCR2_2 |
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| #define | MCS7840_DEV_REG_DCR0_3 |
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| #define | MCS7840_DEV_REG_DCR1_3 |
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| #define | MCS7840_DEV_REG_DCR2_3 |
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| #define | MCS7840_DEV_REG_DCR0_4 |
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| #define | MCS7840_DEV_REG_DCR1_4 |
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| #define | MCS7840_DEV_REG_DCR2_4 |
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| #define | MCS7840_DEV_DCR0_PWRSAVE |
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| #define | MCS7840_DEV_DCR0_RESERVED1 0x02 /* Unused */ |
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| #define | MCS7840_DEV_DCR0_GPIO_MODE_MASK |
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| #define | MCS7840_DEV_DCR0_GPIO_MODE_IN |
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| #define | MCS7840_DEV_DCR0_GPIO_MODE_OUT |
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| #define | MCS7840_DEV_DCR0_RTS_ACTIVE_HIGH |
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| #define | MCS7840_DEV_DCR0_RTS_AUTO |
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| #define | MCS7840_DEV_DCR0_IRDA 0x40 /* IrDA mode */ |
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| #define | MCS7840_DEV_DCR0_RESERVED2 0x80 /* Unused */ |
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| #define | MCS7840_DEV_DCR1_GPIO_CURRENT_MASK |
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| #define | MCS7840_DEV_DCR1_GPIO_CURRENT_6MA |
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| #define | MCS7840_DEV_DCR1_GPIO_CURRENT_8MA |
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| #define | MCS7840_DEV_DCR1_GPIO_CURRENT_10MA |
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| #define | MCS7840_DEV_DCR1_GPIO_CURRENT_12MA |
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| #define | MCS7840_DEV_DCR1_UART_CURRENT_MASK |
| |
| #define | MCS7840_DEV_DCR1_UART_CURRENT_6MA |
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| #define | MCS7840_DEV_DCR1_UART_CURRENT_8MA |
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| #define | MCS7840_DEV_DCR1_UART_CURRENT_10MA |
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| #define | MCS7840_DEV_DCR1_UART_CURRENT_12MA |
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| #define | MCS7840_DEV_DCR1_WAKEUP_DISABLE |
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| #define | MCS7840_DEV_DCR1_PLLPWRDOWN_DISABLE |
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| #define | MCS7840_DEV_DCR1_LONG_INTERRUPT |
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| #define | MCS7840_DEV_DCR1_RESERVED1 0x80 /* Unused */ |
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| #define | MCS7840_DEV_DCR2_WAKEUP_CTS |
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| #define | MCS7840_DEV_DCR2_WAKEUP_DCD |
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| #define | MCS7840_DEV_DCR2_WAKEUP_RI |
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| #define | MCS7840_DEV_DCR2_WAKEUP_DSR |
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| #define | MCS7840_DEV_DCR2_WAKEUP_RXD |
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| #define | MCS7840_DEV_DCR2_WAKEUP_RESUME |
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| #define | MCS7840_DEV_DCR2_RESERVED1 0x40 /* Unused */ |
| |
| #define | MCS7840_DEV_DCR2_SHDN_POLARITY |
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| #define | MCS7840_IEP_FIFO_STATUS_INDEX 5 |
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| #define | MCS7840_IEP_BO_PORT1_HASDATA 0x01 |
| |
| #define | MCS7840_IEP_BI_PORT1_HASDATA 0x02 |
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| #define | MCS7840_IEP_BO_PORT2_HASDATA 0x04 |
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| #define | MCS7840_IEP_BI_PORT2_HASDATA 0x08 |
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| #define | MCS7840_IEP_BO_PORT3_HASDATA 0x10 |
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| #define | MCS7840_IEP_BI_PORT3_HASDATA 0x20 |
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| #define | MCS7840_IEP_BO_PORT4_HASDATA 0x40 |
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| #define | MCS7840_IEP_BI_PORT4_HASDATA 0x80 |
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| #define | MCS7840_UART_REG_THR |
| |
| #define | MCS7840_UART_REG_RHR |
| |
| #define | MCS7840_UART_REG_IER |
| |
| #define | MCS7840_UART_REG_FCR |
| |
| #define | MCS7840_UART_REG_ISR |
| |
| #define | MCS7840_UART_REG_LCR 0x03 /* Line control register R/W */ |
| |
| #define | MCS7840_UART_REG_MCR 0x04 /* Modem control register R/W */ |
| |
| #define | MCS7840_UART_REG_LSR 0x05 /* Line status register R/Only */ |
| |
| #define | MCS7840_UART_REG_MSR |
| |
| #define | MCS7840_UART_REG_SCRATCHPAD 0x07 /* Scratch pad register */ |
| |
| #define | MCS7840_UART_REG_DLL 0x00 /* Low bits of BAUD divider */ |
| |
| #define | MCS7840_UART_REG_DLM 0x01 /* High bits of BAUD divider */ |
| |
| #define | MCS7840_UART_IER_RXREADY 0x01 /* RX Ready interrumpt mask */ |
| |
| #define | MCS7840_UART_IER_TXREADY 0x02 /* TX Ready interrumpt mask */ |
| |
| #define | MCS7840_UART_IER_RXSTAT 0x04 /* RX Status interrumpt mask */ |
| |
| #define | MCS7840_UART_IER_MODEM |
| |
| #define | MCS7840_UART_IER_SLEEP 0x10 /* SLEEP enable */ |
| |
| #define | MCS7840_UART_FCR_ENABLE 0x01 /* Enable FIFO */ |
| |
| #define | MCS7840_UART_FCR_FLUSHRHR 0x02 /* Flush RHR and FIFO */ |
| |
| #define | MCS7840_UART_FCR_FLUSHTHR 0x04 /* Flush THR and FIFO */ |
| |
| #define | MCS7840_UART_FCR_RTLMASK |
| |
| #define | MCS7840_UART_FCR_RTL_1_1 0x00 /* L1 = 1, L2 = 1 */ |
| |
| #define | MCS7840_UART_FCR_RTL_1_4 0x40 /* L1 = 1, L2 = 4 */ |
| |
| #define | MCS7840_UART_FCR_RTL_1_8 0x80 /* L1 = 1, L2 = 8 */ |
| |
| #define | MCS7840_UART_FCR_RTL_1_14 0xa0 /* L1 = 1, L2 = 14 */ |
| |
| #define | MCS7840_UART_ISR_NOPENDING 0x01 /* No interrupt pending */ |
| |
| #define | MCS7840_UART_ISR_INTMASK |
| |
| #define | MCS7840_UART_ISR_RXERR 0x06 /* Recevir error */ |
| |
| #define | MCS7840_UART_ISR_RXHASDATA 0x04 /* Recevier has data */ |
| |
| #define | MCS7840_UART_ISR_RXTIMEOUT 0x0c /* Recevier timeout */ |
| |
| #define | MCS7840_UART_ISR_TXEMPTY 0x02 /* Transmitter empty */ |
| |
| #define | MCS7840_UART_ISR_MSCHANGE 0x00 /* Modem status change */ |
| |
| #define | MCS7840_UART_LCR_DATALENMASK 0x03 /* Mask for data length */ |
| |
| #define | MCS7840_UART_LCR_DATALEN5 0x00 /* 5 data bits */ |
| |
| #define | MCS7840_UART_LCR_DATALEN6 0x01 /* 6 data bits */ |
| |
| #define | MCS7840_UART_LCR_DATALEN7 0x02 /* 7 data bits */ |
| |
| #define | MCS7840_UART_LCR_DATALEN8 0x03 /* 8 data bits */ |
| |
| #define | MCS7840_UART_LCR_STOPBMASK 0x04 /* Mask for stop bits */ |
| |
| #define | MCS7840_UART_LCR_STOPB1 0x00 /* 1 stop bit in any case */ |
| |
| #define | MCS7840_UART_LCR_STOPB2 |
| |
| #define | MCS7840_UART_LCR_PARITYMASK 0x38 /* Mask for all parity data */ |
| |
| #define | MCS7840_UART_LCR_PARITYON 0x08 /* Parity ON/OFF - ON */ |
| |
| #define | MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */ |
| |
| #define | MCS7840_UART_LCR_PARITYEVEN 0x10 /* Parity Even */ |
| |
| #define | MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */ |
| |
| #define | MCS7840_UART_LCR_PARITYFORCE 0x20 /* Force parity odd/even */ |
| |
| #define | MCS7840_UART_LCR_BREAK 0x40 /* Send BREAK */ |
| |
| #define | MCS7840_UART_LCR_DIVISORS |
| |
| #define | MCS7840_UART_LSR_RHRAVAIL 0x01 /* Data available for read */ |
| |
| #define | MCS7840_UART_LSR_RHROVERRUN 0x02 /* Data FIFO/register overflow */ |
| |
| #define | MCS7840_UART_LSR_PARITYERR 0x04 /* Parity error */ |
| |
| #define | MCS7840_UART_LSR_FRAMEERR 0x10 /* Framing error */ |
| |
| #define | MCS7840_UART_LSR_BREAKERR 0x20 /* BREAK signal received */ |
| |
| #define | MCS7840_UART_LSR_THREMPTY |
| |
| #define | MCS7840_UART_LSR_HASERR 0x80 /* Has error in receiver FIFO */ |
| |
| #define | MCS7840_UART_MCR_DTR |
| |
| #define | MCS7840_UART_MCR_RTS |
| |
| #define | MCS7840_UART_MCR_IE |
| |
| #define | MCS7840_UART_MCR_LOOPBACK |
| |
| #define | MCS7840_UART_MCR_CTSRTS |
| |
| #define | MCS7840_UART_MCR_DTRDSR |
| |
| #define | MCS7840_UART_MCR_DCD |
| |
| #define | MCS7840_UART_MSR_DELTACTS |
| |
| #define | MCS7840_UART_MSR_DELTADSR |
| |
| #define | MCS7840_UART_MSR_DELTARI |
| |
| #define | MCS7840_UART_MSR_DELTADCD |
| |
| #define | MCS7840_UART_MSR_NEGCTS 0x10 /* Negated CTS signal */ |
| |
| #define | MCS7840_UART_MSR_NEGDSR 0x20 /* Negated DSR signal */ |
| |
| #define | MCS7840_UART_MSR_NEGRI 0x40 /* Negated RI signal */ |
| |
| #define | MCS7840_UART_MSR_NEGDCD 0x80 /* Negated DCD signal */ |
| |
| #define | MCS7840_UART_SCRATCHPAD_RS232 0x00 /* RS-485 disabled */ |
| |
| #define | MCS7840_UART_SCRATCHPAD_RS485_DTRRX |
| |
| #define | MCS7840_UART_SCRATCHPAD_RS485_DTRTX |
| |
| #define | MCS7840_CONFIG_INDEX 0 |
| |
| #define | MCS7840_IFACE_INDEX 0 |
| |
