FreeBSD kernel usb device Code
uhci.c
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1/* $FreeBSD$ */
2/*-
3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 *
5 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
6 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved.
7 * Copyright (c) 1998 Lennart Augustsson. All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31/*
32 * USB Universal Host Controller driver.
33 * Handles e.g. PIIX3 and PIIX4.
34 *
35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm
36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip
37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf
38 * ftp://download.intel.com/design/intarch/datashts/29056201.pdf
39 */
40
41#ifdef USB_GLOBAL_INCLUDE_FILE
42#include USB_GLOBAL_INCLUDE_FILE
43#else
44#include <sys/stdint.h>
45#include <sys/stddef.h>
46#include <sys/param.h>
47#include <sys/queue.h>
48#include <sys/types.h>
49#include <sys/systm.h>
50#include <sys/kernel.h>
51#include <sys/bus.h>
52#include <sys/module.h>
53#include <sys/lock.h>
54#include <sys/mutex.h>
55#include <sys/condvar.h>
56#include <sys/sysctl.h>
57#include <sys/sx.h>
58#include <sys/unistd.h>
59#include <sys/callout.h>
60#include <sys/malloc.h>
61#include <sys/priv.h>
62
63#include <dev/usb/usb.h>
64#include <dev/usb/usbdi.h>
65
66#define USB_DEBUG_VAR uhcidebug
67
68#include <dev/usb/usb_core.h>
69#include <dev/usb/usb_debug.h>
70#include <dev/usb/usb_busdma.h>
71#include <dev/usb/usb_process.h>
72#include <dev/usb/usb_transfer.h>
73#include <dev/usb/usb_device.h>
74#include <dev/usb/usb_hub.h>
75#include <dev/usb/usb_util.h>
76
77#include <dev/usb/usb_controller.h>
78#include <dev/usb/usb_bus.h>
79#endif /* USB_GLOBAL_INCLUDE_FILE */
80
81#include <dev/usb/controller/uhci.h>
82#include <dev/usb/controller/uhcireg.h>
83
84#define alt_next next
85#define UHCI_BUS2SC(bus) \
86 __containerof(bus, uhci_softc_t, sc_bus)
87
88#ifdef USB_DEBUG
89static int uhcidebug = 0;
90static int uhcinoloop = 0;
91
92static SYSCTL_NODE(_hw_usb, OID_AUTO, uhci, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
93 "USB uhci");
94SYSCTL_INT(_hw_usb_uhci, OID_AUTO, debug, CTLFLAG_RWTUN,
95 &uhcidebug, 0, "uhci debug level");
96SYSCTL_INT(_hw_usb_uhci, OID_AUTO, loop, CTLFLAG_RWTUN,
97 &uhcinoloop, 0, "uhci noloop");
98
99static void uhci_dumpregs(uhci_softc_t *sc);
100static void uhci_dump_tds(uhci_td_t *td);
101
102#endif
103
104#define UBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \
105 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
106#define UWRITE1(sc, r, x) \
107 do { UBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
108 } while (/*CONSTCOND*/0)
109#define UWRITE2(sc, r, x) \
110 do { UBARR(sc); bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
111 } while (/*CONSTCOND*/0)
112#define UWRITE4(sc, r, x) \
113 do { UBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); \
114 } while (/*CONSTCOND*/0)
115#define UREAD1(sc, r) (UBARR(sc), bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
116#define UREAD2(sc, r) (UBARR(sc), bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
117#define UREAD4(sc, r) (UBARR(sc), bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r)))
118
119#define UHCICMD(sc, cmd) UWRITE2(sc, UHCI_CMD, cmd)
120#define UHCISTS(sc) UREAD2(sc, UHCI_STS)
121
122#define UHCI_RESET_TIMEOUT 100 /* ms, reset timeout */
123
124#define UHCI_INTR_ENDPT 1
125
126struct uhci_mem_layout {
127 struct usb_page_search buf_res;
128 struct usb_page_search fix_res;
129
130 struct usb_page_cache *buf_pc;
131 struct usb_page_cache *fix_pc;
132
133 uint32_t buf_offset;
134
135 uint16_t max_frame_size;
136};
137
138struct uhci_std_temp {
139 struct uhci_mem_layout ml;
140 uhci_td_t *td;
141 uhci_td_t *td_next;
142 uint32_t average;
143 uint32_t td_status;
144 uint32_t td_token;
145 uint32_t len;
146 uint16_t max_frame_size;
147 uint8_t shortpkt;
148 uint8_t setup_alt_next;
149 uint8_t last_frame;
150};
151
152static const struct usb_bus_methods uhci_bus_methods;
153static const struct usb_pipe_methods uhci_device_bulk_methods;
154static const struct usb_pipe_methods uhci_device_ctrl_methods;
155static const struct usb_pipe_methods uhci_device_intr_methods;
156static const struct usb_pipe_methods uhci_device_isoc_methods;
157
158static uint8_t uhci_restart(uhci_softc_t *sc);
159static void uhci_do_poll(struct usb_bus *);
160static void uhci_device_done(struct usb_xfer *, usb_error_t);
161static void uhci_transfer_intr_enqueue(struct usb_xfer *);
162static void uhci_timeout(void *);
163static uint8_t uhci_check_transfer(struct usb_xfer *);
164static void uhci_root_intr(uhci_softc_t *sc);
165
166void
167uhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
168{
169 struct uhci_softc *sc = UHCI_BUS2SC(bus);
170 uint32_t i;
171
172 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
173 sizeof(uint32_t) * UHCI_FRAMELIST_COUNT, UHCI_FRAMELIST_ALIGN);
174
175 cb(bus, &sc->sc_hw.ls_ctl_start_pc, &sc->sc_hw.ls_ctl_start_pg,
176 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
177
178 cb(bus, &sc->sc_hw.fs_ctl_start_pc, &sc->sc_hw.fs_ctl_start_pg,
179 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
180
181 cb(bus, &sc->sc_hw.bulk_start_pc, &sc->sc_hw.bulk_start_pg,
182 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
183
184 cb(bus, &sc->sc_hw.last_qh_pc, &sc->sc_hw.last_qh_pg,
185 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
186
187 cb(bus, &sc->sc_hw.last_td_pc, &sc->sc_hw.last_td_pg,
188 sizeof(uhci_td_t), UHCI_TD_ALIGN);
189
190 for (i = 0; i != UHCI_VFRAMELIST_COUNT; i++) {
191 cb(bus, sc->sc_hw.isoc_start_pc + i,
192 sc->sc_hw.isoc_start_pg + i,
193 sizeof(uhci_td_t), UHCI_TD_ALIGN);
194 }
195
196 for (i = 0; i != UHCI_IFRAMELIST_COUNT; i++) {
197 cb(bus, sc->sc_hw.intr_start_pc + i,
198 sc->sc_hw.intr_start_pg + i,
199 sizeof(uhci_qh_t), UHCI_QH_ALIGN);
200 }
201}
202
203static void
204uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer)
205{
206 ml->buf_pc = xfer->frbuffers + 0;
207 ml->fix_pc = xfer->buf_fixup;
208
209 ml->buf_offset = 0;
210
211 ml->max_frame_size = xfer->max_frame_size;
212}
213
214static void
215uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td)
216{
217 usbd_get_page(ml->buf_pc, ml->buf_offset, &ml->buf_res);
218
219 if (ml->buf_res.length < td->len) {
220 /* need to do a fixup */
221
222 usbd_get_page(ml->fix_pc, 0, &ml->fix_res);
223
224 td->td_buffer = htole32(ml->fix_res.physaddr);
225
226 /*
227 * The UHCI driver cannot handle
228 * page crossings, so a fixup is
229 * needed:
230 *
231 * +----+----+ - - -
232 * | YYY|Y |
233 * +----+----+ - - -
234 * \ \
235 * \ \
236 * +----+
237 * |YYYY| (fixup)
238 * +----+
239 */
240
241 if ((td->td_token & htole32(UHCI_TD_PID)) ==
242 htole32(UHCI_TD_PID_IN)) {
243 td->fix_pc = ml->fix_pc;
244 usb_pc_cpu_invalidate(ml->fix_pc);
245
246 } else {
247 td->fix_pc = NULL;
248
249 /* copy data to fixup location */
250
251 usbd_copy_out(ml->buf_pc, ml->buf_offset,
252 ml->fix_res.buffer, td->len);
253
254 usb_pc_cpu_flush(ml->fix_pc);
255 }
256
257 /* prepare next fixup */
258
259 ml->fix_pc++;
260
261 } else {
262 td->td_buffer = htole32(ml->buf_res.physaddr);
263 td->fix_pc = NULL;
264 }
265
266 /* prepare next data location */
267
268 ml->buf_offset += td->len;
269}
270
271/*
272 * Return values:
273 * 0: Success
274 * Else: Failure
275 */
276static uint8_t
277uhci_restart(uhci_softc_t *sc)
278{
279 struct usb_page_search buf_res;
280
281 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
282
283 if (UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS) {
284 DPRINTFN(2, "Already started\n");
285 return (0);
286 }
287
288 DPRINTFN(2, "Restarting\n");
289
290 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
291
292 /* Reload fresh base address */
293 UWRITE4(sc, UHCI_FLBASEADDR, buf_res.physaddr);
294
295 /*
296 * Assume 64 byte packets at frame end and start HC controller:
297 */
298 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS));
299
300 /* wait 10 milliseconds */
301
302 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
303
304 /* check that controller has started */
305
306 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) {
307 DPRINTFN(2, "Failed\n");
308 return (1);
309 }
310 return (0);
311}
312
313void
314uhci_reset(uhci_softc_t *sc)
315{
316 uint16_t n;
317
318 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
319
320 DPRINTF("resetting the HC\n");
321
322 /* disable interrupts */
323
324 UWRITE2(sc, UHCI_INTR, 0);
325
326 /* global reset */
327
328 UHCICMD(sc, UHCI_CMD_GRESET);
329
330 /* wait */
331
332 usb_pause_mtx(&sc->sc_bus.bus_mtx,
333 USB_MS_TO_TICKS(USB_BUS_RESET_DELAY));
334
335 /* terminate all transfers */
336
337 UHCICMD(sc, UHCI_CMD_HCRESET);
338
339 /* the reset bit goes low when the controller is done */
340
341 n = UHCI_RESET_TIMEOUT;
342 while (n--) {
343 /* wait one millisecond */
344
345 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
346
347 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) {
348 goto done_1;
349 }
350 }
351
352 device_printf(sc->sc_bus.bdev,
353 "controller did not reset\n");
354
355done_1:
356
357 n = 10;
358 while (n--) {
359 /* wait one millisecond */
360
361 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
362
363 /* check if HC is stopped */
364 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) {
365 goto done_2;
366 }
367 }
368
369 device_printf(sc->sc_bus.bdev,
370 "controller did not stop\n");
371
372done_2:
373
374 /* reset frame number */
375 UWRITE2(sc, UHCI_FRNUM, 0);
376 /* set default SOF value */
377 UWRITE1(sc, UHCI_SOF, 0x40);
378
379 USB_BUS_UNLOCK(&sc->sc_bus);
380
381 /* stop root interrupt */
382 usb_callout_drain(&sc->sc_root_intr);
383
384 USB_BUS_LOCK(&sc->sc_bus);
385}
386
387static void
388uhci_start(uhci_softc_t *sc)
389{
390 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
391
392 DPRINTFN(2, "enabling\n");
393
394 /* enable interrupts */
395
396 UWRITE2(sc, UHCI_INTR,
397 (UHCI_INTR_TOCRCIE |
398 UHCI_INTR_RIE |
399 UHCI_INTR_IOCE |
400 UHCI_INTR_SPIE));
401
402 if (uhci_restart(sc)) {
403 device_printf(sc->sc_bus.bdev,
404 "cannot start HC controller\n");
405 }
406
407 /* start root interrupt */
408 uhci_root_intr(sc);
409}
410
411static struct uhci_qh *
412uhci_init_qh(struct usb_page_cache *pc)
413{
414 struct usb_page_search buf_res;
415 struct uhci_qh *qh;
416
417 usbd_get_page(pc, 0, &buf_res);
418
419 qh = buf_res.buffer;
420
421 qh->qh_self =
422 htole32(buf_res.physaddr) |
423 htole32(UHCI_PTR_QH);
424
425 qh->page_cache = pc;
426
427 return (qh);
428}
429
430static struct uhci_td *
431uhci_init_td(struct usb_page_cache *pc)
432{
433 struct usb_page_search buf_res;
434 struct uhci_td *td;
435
436 usbd_get_page(pc, 0, &buf_res);
437
438 td = buf_res.buffer;
439
440 td->td_self =
441 htole32(buf_res.physaddr) |
442 htole32(UHCI_PTR_TD);
443
444 td->page_cache = pc;
445
446 return (td);
447}
448
449usb_error_t
450uhci_init(uhci_softc_t *sc)
451{
452 uint16_t bit;
453 uint16_t x;
454 uint16_t y;
455
456 DPRINTF("start\n");
457
458 usb_callout_init_mtx(&sc->sc_root_intr, &sc->sc_bus.bus_mtx, 0);
459
460#ifdef USB_DEBUG
461 if (uhcidebug > 2) {
462 uhci_dumpregs(sc);
463 }
464#endif
465 /*
466 * Setup QH's
467 */
468 sc->sc_ls_ctl_p_last =
469 uhci_init_qh(&sc->sc_hw.ls_ctl_start_pc);
470
471 sc->sc_fs_ctl_p_last =
472 uhci_init_qh(&sc->sc_hw.fs_ctl_start_pc);
473
474 sc->sc_bulk_p_last =
475 uhci_init_qh(&sc->sc_hw.bulk_start_pc);
476#if 0
477 sc->sc_reclaim_qh_p =
478 sc->sc_fs_ctl_p_last;
479#else
480 /* setup reclaim looping point */
481 sc->sc_reclaim_qh_p =
482 sc->sc_bulk_p_last;
483#endif
484
485 sc->sc_last_qh_p =
486 uhci_init_qh(&sc->sc_hw.last_qh_pc);
487
488 sc->sc_last_td_p =
489 uhci_init_td(&sc->sc_hw.last_td_pc);
490
491 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) {
492 sc->sc_isoc_p_last[x] =
493 uhci_init_td(sc->sc_hw.isoc_start_pc + x);
494 }
495
496 for (x = 0; x != UHCI_IFRAMELIST_COUNT; x++) {
497 sc->sc_intr_p_last[x] =
498 uhci_init_qh(sc->sc_hw.intr_start_pc + x);
499 }
500
501 /*
502 * the QHs are arranged to give poll intervals that are
503 * powers of 2 times 1ms
504 */
505 bit = UHCI_IFRAMELIST_COUNT / 2;
506 while (bit) {
507 x = bit;
508 while (x & bit) {
509 uhci_qh_t *qh_x;
510 uhci_qh_t *qh_y;
511
512 y = (x ^ bit) | (bit / 2);
513
514 /*
515 * the next QH has half the poll interval
516 */
517 qh_x = sc->sc_intr_p_last[x];
518 qh_y = sc->sc_intr_p_last[y];
519
520 qh_x->h_next = NULL;
521 qh_x->qh_h_next = qh_y->qh_self;
522 qh_x->e_next = NULL;
523 qh_x->qh_e_next = htole32(UHCI_PTR_T);
524 x++;
525 }
526 bit >>= 1;
527 }
528
529 if (1) {
530 uhci_qh_t *qh_ls;
531 uhci_qh_t *qh_intr;
532
533 qh_ls = sc->sc_ls_ctl_p_last;
534 qh_intr = sc->sc_intr_p_last[0];
535
536 /* start QH for interrupt traffic */
537 qh_intr->h_next = qh_ls;
538 qh_intr->qh_h_next = qh_ls->qh_self;
539 qh_intr->e_next = 0;
540 qh_intr->qh_e_next = htole32(UHCI_PTR_T);
541 }
542 for (x = 0; x != UHCI_VFRAMELIST_COUNT; x++) {
543 uhci_td_t *td_x;
544 uhci_qh_t *qh_intr;
545
546 td_x = sc->sc_isoc_p_last[x];
547 qh_intr = sc->sc_intr_p_last[x | (UHCI_IFRAMELIST_COUNT / 2)];
548
549 /* start TD for isochronous traffic */
550 td_x->next = NULL;
551 td_x->td_next = qh_intr->qh_self;
552 td_x->td_status = htole32(UHCI_TD_IOS);
553 td_x->td_token = htole32(0);
554 td_x->td_buffer = htole32(0);
555 }
556
557 if (1) {
558 uhci_qh_t *qh_ls;
559 uhci_qh_t *qh_fs;
560
561 qh_ls = sc->sc_ls_ctl_p_last;
562 qh_fs = sc->sc_fs_ctl_p_last;
563
564 /* start QH where low speed control traffic will be queued */
565 qh_ls->h_next = qh_fs;
566 qh_ls->qh_h_next = qh_fs->qh_self;
567 qh_ls->e_next = 0;
568 qh_ls->qh_e_next = htole32(UHCI_PTR_T);
569 }
570 if (1) {
571 uhci_qh_t *qh_ctl;
572 uhci_qh_t *qh_blk;
573 uhci_qh_t *qh_lst;
574 uhci_td_t *td_lst;
575
576 qh_ctl = sc->sc_fs_ctl_p_last;
577 qh_blk = sc->sc_bulk_p_last;
578
579 /* start QH where full speed control traffic will be queued */
580 qh_ctl->h_next = qh_blk;
581 qh_ctl->qh_h_next = qh_blk->qh_self;
582 qh_ctl->e_next = 0;
583 qh_ctl->qh_e_next = htole32(UHCI_PTR_T);
584
585 qh_lst = sc->sc_last_qh_p;
586
587 /* start QH where bulk traffic will be queued */
588 qh_blk->h_next = qh_lst;
589 qh_blk->qh_h_next = qh_lst->qh_self;
590 qh_blk->e_next = 0;
591 qh_blk->qh_e_next = htole32(UHCI_PTR_T);
592
593 td_lst = sc->sc_last_td_p;
594
595 /* end QH which is used for looping the QHs */
596 qh_lst->h_next = 0;
597 qh_lst->qh_h_next = htole32(UHCI_PTR_T); /* end of QH chain */
598 qh_lst->e_next = td_lst;
599 qh_lst->qh_e_next = td_lst->td_self;
600
601 /*
602 * end TD which hangs from the last QH, to avoid a bug in the PIIX
603 * that makes it run berserk otherwise
604 */
605 td_lst->next = 0;
606 td_lst->td_next = htole32(UHCI_PTR_T);
607 td_lst->td_status = htole32(0); /* inactive */
608 td_lst->td_token = htole32(0);
609 td_lst->td_buffer = htole32(0);
610 }
611 if (1) {
612 struct usb_page_search buf_res;
613 uint32_t *pframes;
614
615 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
616
617 pframes = buf_res.buffer;
618
619 /*
620 * Setup UHCI framelist
621 *
622 * Execution order:
623 *
624 * pframes -> full speed isochronous -> interrupt QH's -> low
625 * speed control -> full speed control -> bulk transfers
626 *
627 */
628
629 for (x = 0; x != UHCI_FRAMELIST_COUNT; x++) {
630 pframes[x] =
631 sc->sc_isoc_p_last[x % UHCI_VFRAMELIST_COUNT]->td_self;
632 }
633 }
634 /* flush all cache into memory */
635
636 usb_bus_mem_flush_all(&sc->sc_bus, &uhci_iterate_hw_softc);
637
638 /* set up the bus struct */
639 sc->sc_bus.methods = &uhci_bus_methods;
640
641 USB_BUS_LOCK(&sc->sc_bus);
642 /* reset the controller */
643 uhci_reset(sc);
644
645 /* start the controller */
646 uhci_start(sc);
647 USB_BUS_UNLOCK(&sc->sc_bus);
648
649 /* catch lost interrupts */
650 uhci_do_poll(&sc->sc_bus);
651
652 return (0);
653}
654
655static void
656uhci_suspend(uhci_softc_t *sc)
657{
658#ifdef USB_DEBUG
659 if (uhcidebug > 2) {
660 uhci_dumpregs(sc);
661 }
662#endif
663
664 USB_BUS_LOCK(&sc->sc_bus);
665
666 /* stop the controller */
667
668 uhci_reset(sc);
669
670 /* enter global suspend */
671
672 UHCICMD(sc, UHCI_CMD_EGSM);
673
674 USB_BUS_UNLOCK(&sc->sc_bus);
675}
676
677static void
678uhci_resume(uhci_softc_t *sc)
679{
680 USB_BUS_LOCK(&sc->sc_bus);
681
682 /* reset the controller */
683
684 uhci_reset(sc);
685
686 /* force global resume */
687
688 UHCICMD(sc, UHCI_CMD_FGR);
689
690 /* and start traffic again */
691
692 uhci_start(sc);
693
694 USB_BUS_UNLOCK(&sc->sc_bus);
695
696#ifdef USB_DEBUG
697 if (uhcidebug > 2)
698 uhci_dumpregs(sc);
699#endif
700
701 /* catch lost interrupts */
702 uhci_do_poll(&sc->sc_bus);
703}
704
705#ifdef USB_DEBUG
706static void
707uhci_dumpregs(uhci_softc_t *sc)
708{
709 DPRINTFN(0, "%s regs: cmd=%04x, sts=%04x, intr=%04x, frnum=%04x, "
710 "flbase=%08x, sof=%04x, portsc1=%04x, portsc2=%04x\n",
711 device_get_nameunit(sc->sc_bus.bdev),
712 UREAD2(sc, UHCI_CMD),
713 UREAD2(sc, UHCI_STS),
714 UREAD2(sc, UHCI_INTR),
715 UREAD2(sc, UHCI_FRNUM),
716 UREAD4(sc, UHCI_FLBASEADDR),
717 UREAD1(sc, UHCI_SOF),
718 UREAD2(sc, UHCI_PORTSC1),
719 UREAD2(sc, UHCI_PORTSC2));
720}
721
722static uint8_t
723uhci_dump_td(uhci_td_t *p)
724{
725 uint32_t td_next;
726 uint32_t td_status;
727 uint32_t td_token;
728 uint8_t temp;
729
730 usb_pc_cpu_invalidate(p->page_cache);
731
732 td_next = le32toh(p->td_next);
733 td_status = le32toh(p->td_status);
734 td_token = le32toh(p->td_token);
735
736 /*
737 * Check whether the link pointer in this TD marks the link pointer
738 * as end of queue:
739 */
740 temp = ((td_next & UHCI_PTR_T) || (td_next == 0));
741
742 printf("TD(%p) at 0x%08x = link=0x%08x status=0x%08x "
743 "token=0x%08x buffer=0x%08x\n",
744 p,
745 le32toh(p->td_self),
746 td_next,
747 td_status,
748 td_token,
749 le32toh(p->td_buffer));
750
751 printf("TD(%p) td_next=%s%s%s td_status=%s%s%s%s%s%s%s%s%s%s%s, errcnt=%d, actlen=%d pid=%02x,"
752 "addr=%d,endpt=%d,D=%d,maxlen=%d\n",
753 p,
754 (td_next & 1) ? "-T" : "",
755 (td_next & 2) ? "-Q" : "",
756 (td_next & 4) ? "-VF" : "",
757 (td_status & UHCI_TD_BITSTUFF) ? "-BITSTUFF" : "",
758 (td_status & UHCI_TD_CRCTO) ? "-CRCTO" : "",
759 (td_status & UHCI_TD_NAK) ? "-NAK" : "",
760 (td_status & UHCI_TD_BABBLE) ? "-BABBLE" : "",
761 (td_status & UHCI_TD_DBUFFER) ? "-DBUFFER" : "",
762 (td_status & UHCI_TD_STALLED) ? "-STALLED" : "",
763 (td_status & UHCI_TD_ACTIVE) ? "-ACTIVE" : "",
764 (td_status & UHCI_TD_IOC) ? "-IOC" : "",
765 (td_status & UHCI_TD_IOS) ? "-IOS" : "",
766 (td_status & UHCI_TD_LS) ? "-LS" : "",
767 (td_status & UHCI_TD_SPD) ? "-SPD" : "",
768 UHCI_TD_GET_ERRCNT(td_status),
769 UHCI_TD_GET_ACTLEN(td_status),
770 UHCI_TD_GET_PID(td_token),
771 UHCI_TD_GET_DEVADDR(td_token),
772 UHCI_TD_GET_ENDPT(td_token),
773 UHCI_TD_GET_DT(td_token),
774 UHCI_TD_GET_MAXLEN(td_token));
775
776 return (temp);
777}
778
779static uint8_t
780uhci_dump_qh(uhci_qh_t *sqh)
781{
782 uint8_t temp;
783 uint32_t qh_h_next;
784 uint32_t qh_e_next;
785
786 usb_pc_cpu_invalidate(sqh->page_cache);
787
788 qh_h_next = le32toh(sqh->qh_h_next);
789 qh_e_next = le32toh(sqh->qh_e_next);
790
791 DPRINTFN(0, "QH(%p) at 0x%08x: h_next=0x%08x e_next=0x%08x\n", sqh,
792 le32toh(sqh->qh_self), qh_h_next, qh_e_next);
793
794 temp = ((((sqh->h_next != NULL) && !(qh_h_next & UHCI_PTR_T)) ? 1 : 0) |
795 (((sqh->e_next != NULL) && !(qh_e_next & UHCI_PTR_T)) ? 2 : 0));
796
797 return (temp);
798}
799
800static void
801uhci_dump_all(uhci_softc_t *sc)
802{
803 uhci_dumpregs(sc);
804 uhci_dump_qh(sc->sc_ls_ctl_p_last);
805 uhci_dump_qh(sc->sc_fs_ctl_p_last);
806 uhci_dump_qh(sc->sc_bulk_p_last);
807 uhci_dump_qh(sc->sc_last_qh_p);
808}
809
810static void
811uhci_dump_tds(uhci_td_t *td)
812{
813 for (;
814 td != NULL;
815 td = td->obj_next) {
816 if (uhci_dump_td(td)) {
817 break;
818 }
819 }
820}
821
822#endif
823
824/*
825 * Let the last QH loop back to the full speed control transfer QH.
826 * This is what intel calls "bandwidth reclamation" and improves
827 * USB performance a lot for some devices.
828 * If we are already looping, just count it.
829 */
830static void
831uhci_add_loop(uhci_softc_t *sc)
832{
833 struct uhci_qh *qh_lst;
834 struct uhci_qh *qh_rec;
835
836#ifdef USB_DEBUG
837 if (uhcinoloop) {
838 return;
839 }
840#endif
841 if (++(sc->sc_loops) == 1) {
842 DPRINTFN(6, "add\n");
843
844 qh_lst = sc->sc_last_qh_p;
845 qh_rec = sc->sc_reclaim_qh_p;
846
847 /* NOTE: we don't loop back the soft pointer */
848
849 qh_lst->qh_h_next = qh_rec->qh_self;
850 usb_pc_cpu_flush(qh_lst->page_cache);
851 }
852}
853
854static void
855uhci_rem_loop(uhci_softc_t *sc)
856{
857 struct uhci_qh *qh_lst;
858
859#ifdef USB_DEBUG
860 if (uhcinoloop) {
861 return;
862 }
863#endif
864 if (--(sc->sc_loops) == 0) {
865 DPRINTFN(6, "remove\n");
866
867 qh_lst = sc->sc_last_qh_p;
868 qh_lst->qh_h_next = htole32(UHCI_PTR_T);
869 usb_pc_cpu_flush(qh_lst->page_cache);
870 }
871}
872
873static void
874uhci_transfer_intr_enqueue(struct usb_xfer *xfer)
875{
876 /* check for early completion */
877 if (uhci_check_transfer(xfer)) {
878 return;
879 }
880 /* put transfer on interrupt queue */
881 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
882
883 /* start timeout, if any */
884 if (xfer->timeout != 0) {
885 usbd_transfer_timeout_ms(xfer, &uhci_timeout, xfer->timeout);
886 }
887}
888
889#define UHCI_APPEND_TD(std,last) (last) = _uhci_append_td(std,last)
890static uhci_td_t *
891_uhci_append_td(uhci_td_t *std, uhci_td_t *last)
892{
893 DPRINTFN(11, "%p to %p\n", std, last);
894
895 /* (sc->sc_bus.mtx) must be locked */
896
897 std->next = last->next;
898 std->td_next = last->td_next;
899
900 std->prev = last;
901
902 usb_pc_cpu_flush(std->page_cache);
903
904 /*
905 * the last->next->prev is never followed: std->next->prev = std;
906 */
907 last->next = std;
908 last->td_next = std->td_self;
909
910 usb_pc_cpu_flush(last->page_cache);
911
912 return (std);
913}
914
915#define UHCI_APPEND_QH(sqh,last) (last) = _uhci_append_qh(sqh,last)
916static uhci_qh_t *
917_uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last)
918{
919 DPRINTFN(11, "%p to %p\n", sqh, last);
920
921 if (sqh->h_prev != NULL) {
922 /* should not happen */
923 DPRINTFN(0, "QH already linked!\n");
924 return (last);
925 }
926 /* (sc->sc_bus.mtx) must be locked */
927
928 sqh->h_next = last->h_next;
929 sqh->qh_h_next = last->qh_h_next;
930
931 sqh->h_prev = last;
932
933 usb_pc_cpu_flush(sqh->page_cache);
934
935 /*
936 * The "last->h_next->h_prev" is never followed:
937 *
938 * "sqh->h_next->h_prev" = sqh;
939 */
940
941 last->h_next = sqh;
942 last->qh_h_next = sqh->qh_self;
943
944 usb_pc_cpu_flush(last->page_cache);
945
946 return (sqh);
947}
948
949
950
951#define UHCI_REMOVE_TD(std,last) (last) = _uhci_remove_td(std,last)
952static uhci_td_t *
953_uhci_remove_td(uhci_td_t *std, uhci_td_t *last)
954{
955 DPRINTFN(11, "%p from %p\n", std, last);
956
957 /* (sc->sc_bus.mtx) must be locked */
958
959 std->prev->next = std->next;
960 std->prev->td_next = std->td_next;
961
962 usb_pc_cpu_flush(std->prev->page_cache);
963
964 if (std->next) {
965 std->next->prev = std->prev;
966 usb_pc_cpu_flush(std->next->page_cache);
967 }
968 return ((last == std) ? std->prev : last);
969}
970
971#define UHCI_REMOVE_QH(sqh,last) (last) = _uhci_remove_qh(sqh,last)
972static uhci_qh_t *
973_uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last)
974{
975 DPRINTFN(11, "%p from %p\n", sqh, last);
976
977 /* (sc->sc_bus.mtx) must be locked */
978
979 /* only remove if not removed from a queue */
980 if (sqh->h_prev) {
981 sqh->h_prev->h_next = sqh->h_next;
982 sqh->h_prev->qh_h_next = sqh->qh_h_next;
983
984 usb_pc_cpu_flush(sqh->h_prev->page_cache);
985
986 if (sqh->h_next) {
987 sqh->h_next->h_prev = sqh->h_prev;
988 usb_pc_cpu_flush(sqh->h_next->page_cache);
989 }
990 last = ((last == sqh) ? sqh->h_prev : last);
991
992 sqh->h_prev = 0;
993
994 usb_pc_cpu_flush(sqh->page_cache);
995 }
996 return (last);
997}
998
999static void
1000uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer)
1001{
1002 struct usb_page_search res;
1003 uint32_t nframes = xfer->nframes;
1004 uint32_t status;
1005 uint32_t offset = 0;
1006 uint32_t *plen = xfer->frlengths;
1007 uint16_t len = 0;
1008 uhci_td_t *td = xfer->td_transfer_first;
1009 uhci_td_t **pp_last = &sc->sc_isoc_p_last[xfer->qh_pos];
1010
1011 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1012 xfer, xfer->endpoint);
1013
1014 /* sync any DMA memory before doing fixups */
1015
1016 usb_bdma_post_sync(xfer);
1017
1018 while (nframes--) {
1019 if (td == NULL) {
1020 panic("%s:%d: out of TD's\n",
1021 __FUNCTION__, __LINE__);
1022 }
1023 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) {
1024 pp_last = &sc->sc_isoc_p_last[0];
1025 }
1026#ifdef USB_DEBUG
1027 if (uhcidebug > 5) {
1028 DPRINTF("isoc TD\n");
1029 uhci_dump_td(td);
1030 }
1031#endif
1032 usb_pc_cpu_invalidate(td->page_cache);
1033 status = le32toh(td->td_status);
1034
1035 len = UHCI_TD_GET_ACTLEN(status);
1036
1037 if (len > *plen) {
1038 len = *plen;
1039 }
1040 if (td->fix_pc) {
1041 usbd_get_page(td->fix_pc, 0, &res);
1042
1043 /* copy data from fixup location to real location */
1044
1045 usb_pc_cpu_invalidate(td->fix_pc);
1046
1047 usbd_copy_in(xfer->frbuffers, offset,
1048 res.buffer, len);
1049 }
1050 offset += *plen;
1051
1052 *plen = len;
1053
1054 /* remove TD from schedule */
1055 UHCI_REMOVE_TD(td, *pp_last);
1056
1057 pp_last++;
1058 plen++;
1059 td = td->obj_next;
1060 }
1061
1062 xfer->aframes = xfer->nframes;
1063}
1064
1065static usb_error_t
1066uhci_non_isoc_done_sub(struct usb_xfer *xfer)
1067{
1068 struct usb_page_search res;
1069 uhci_td_t *td;
1070 uhci_td_t *td_alt_next;
1071 uint32_t status;
1072 uint32_t token;
1073 uint16_t len;
1074
1075 td = xfer->td_transfer_cache;
1076 td_alt_next = td->alt_next;
1077
1078 if (xfer->aframes != xfer->nframes) {
1079 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1080 }
1081 while (1) {
1082 usb_pc_cpu_invalidate(td->page_cache);
1083 status = le32toh(td->td_status);
1084 token = le32toh(td->td_token);
1085
1086 /*
1087 * Verify the status and add
1088 * up the actual length:
1089 */
1090
1091 len = UHCI_TD_GET_ACTLEN(status);
1092 if (len > td->len) {
1093 /* should not happen */
1094 DPRINTF("Invalid status length, "
1095 "0x%04x/0x%04x bytes\n", len, td->len);
1096 status |= UHCI_TD_STALLED;
1097
1098 } else if ((xfer->aframes != xfer->nframes) && (len > 0)) {
1099 if (td->fix_pc) {
1100 usbd_get_page(td->fix_pc, 0, &res);
1101
1102 /*
1103 * copy data from fixup location to real
1104 * location
1105 */
1106
1107 usb_pc_cpu_invalidate(td->fix_pc);
1108
1109 usbd_copy_in(xfer->frbuffers + xfer->aframes,
1110 xfer->frlengths[xfer->aframes], res.buffer, len);
1111 }
1112 /* update actual length */
1113
1114 xfer->frlengths[xfer->aframes] += len;
1115 }
1116 /* Check for last transfer */
1117 if (((void *)td) == xfer->td_transfer_last) {
1118 td = NULL;
1119 break;
1120 }
1121 if (status & UHCI_TD_STALLED) {
1122 /* the transfer is finished */
1123 td = NULL;
1124 break;
1125 }
1126 /* Check for short transfer */
1127 if (len != td->len) {
1128 if (xfer->flags_int.short_frames_ok) {
1129 /* follow alt next */
1130 td = td->alt_next;
1131 } else {
1132 /* the transfer is finished */
1133 td = NULL;
1134 }
1135 break;
1136 }
1137 td = td->obj_next;
1138
1139 if (td->alt_next != td_alt_next) {
1140 /* this USB frame is complete */
1141 break;
1142 }
1143 }
1144
1145 /* update transfer cache */
1146
1147 xfer->td_transfer_cache = td;
1148
1149 /* update data toggle */
1150
1151 xfer->endpoint->toggle_next = (token & UHCI_TD_SET_DT(1)) ? 0 : 1;
1152
1153#ifdef USB_DEBUG
1154 if (status & UHCI_TD_ERROR) {
1155 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x "
1156 "status=%s%s%s%s%s%s%s%s%s%s%s\n",
1157 xfer->address, xfer->endpointno, xfer->aframes,
1158 (status & UHCI_TD_BITSTUFF) ? "[BITSTUFF]" : "",
1159 (status & UHCI_TD_CRCTO) ? "[CRCTO]" : "",
1160 (status & UHCI_TD_NAK) ? "[NAK]" : "",
1161 (status & UHCI_TD_BABBLE) ? "[BABBLE]" : "",
1162 (status & UHCI_TD_DBUFFER) ? "[DBUFFER]" : "",
1163 (status & UHCI_TD_STALLED) ? "[STALLED]" : "",
1164 (status & UHCI_TD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1165 (status & UHCI_TD_IOC) ? "[IOC]" : "",
1166 (status & UHCI_TD_IOS) ? "[IOS]" : "",
1167 (status & UHCI_TD_LS) ? "[LS]" : "",
1168 (status & UHCI_TD_SPD) ? "[SPD]" : "");
1169 }
1170#endif
1171 if (status & UHCI_TD_STALLED) {
1172 /* try to separate I/O errors from STALL */
1173 if (UHCI_TD_GET_ERRCNT(status) == 0)
1174 return (USB_ERR_IOERROR);
1175 return (USB_ERR_STALLED);
1176 }
1177 return (USB_ERR_NORMAL_COMPLETION);
1178}
1179
1180static void
1181uhci_non_isoc_done(struct usb_xfer *xfer)
1182{
1183 usb_error_t err = 0;
1184
1185 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1186 xfer, xfer->endpoint);
1187
1188#ifdef USB_DEBUG
1189 if (uhcidebug > 10) {
1190 uhci_dump_tds(xfer->td_transfer_first);
1191 }
1192#endif
1193
1194 /* sync any DMA memory before doing fixups */
1195
1196 usb_bdma_post_sync(xfer);
1197
1198 /* reset scanner */
1199
1200 xfer->td_transfer_cache = xfer->td_transfer_first;
1201
1202 if (xfer->flags_int.control_xfr) {
1203 if (xfer->flags_int.control_hdr) {
1204 err = uhci_non_isoc_done_sub(xfer);
1205 }
1206 xfer->aframes = 1;
1207
1208 if (xfer->td_transfer_cache == NULL) {
1209 goto done;
1210 }
1211 }
1212 while (xfer->aframes != xfer->nframes) {
1213 err = uhci_non_isoc_done_sub(xfer);
1214 xfer->aframes++;
1215
1216 if (xfer->td_transfer_cache == NULL) {
1217 goto done;
1218 }
1219 }
1220
1221 if (xfer->flags_int.control_xfr &&
1222 !xfer->flags_int.control_act) {
1223 err = uhci_non_isoc_done_sub(xfer);
1224 }
1225done:
1226 uhci_device_done(xfer, err);
1227}
1228
1229/*------------------------------------------------------------------------*
1230 * uhci_check_transfer_sub
1231 *
1232 * The main purpose of this function is to update the data-toggle
1233 * in case it is wrong.
1234 *------------------------------------------------------------------------*/
1235static void
1236uhci_check_transfer_sub(struct usb_xfer *xfer)
1237{
1238 uhci_qh_t *qh;
1239 uhci_td_t *td;
1240 uhci_td_t *td_alt_next;
1241
1242 uint32_t td_token;
1243 uint32_t td_self;
1244
1245 td = xfer->td_transfer_cache;
1246 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1247
1248 td_token = td->obj_next->td_token;
1249 td = td->alt_next;
1250 xfer->td_transfer_cache = td;
1251 td_self = td->td_self;
1252 td_alt_next = td->alt_next;
1253
1254 if (xfer->flags_int.control_xfr)
1255 goto skip; /* don't touch the DT value! */
1256
1257 if (!((td->td_token ^ td_token) & htole32(UHCI_TD_SET_DT(1))))
1258 goto skip; /* data toggle has correct value */
1259
1260 /*
1261 * The data toggle is wrong and we need to toggle it !
1262 */
1263 while (1) {
1264 td->td_token ^= htole32(UHCI_TD_SET_DT(1));
1265 usb_pc_cpu_flush(td->page_cache);
1266
1267 if (td == xfer->td_transfer_last) {
1268 /* last transfer */
1269 break;
1270 }
1271 td = td->obj_next;
1272
1273 if (td->alt_next != td_alt_next) {
1274 /* next frame */
1275 break;
1276 }
1277 }
1278skip:
1279
1280 /* update the QH */
1281 qh->qh_e_next = td_self;
1282 usb_pc_cpu_flush(qh->page_cache);
1283
1284 DPRINTFN(13, "xfer=%p following alt next\n", xfer);
1285}
1286
1287/*------------------------------------------------------------------------*
1288 * uhci_check_transfer
1289 *
1290 * Return values:
1291 * 0: USB transfer is not finished
1292 * Else: USB transfer is finished
1293 *------------------------------------------------------------------------*/
1294static uint8_t
1295uhci_check_transfer(struct usb_xfer *xfer)
1296{
1297 uint32_t status;
1298 uint32_t token;
1299 uhci_td_t *td;
1300
1301 DPRINTFN(16, "xfer=%p checking transfer\n", xfer);
1302
1303 if (xfer->endpoint->methods == &uhci_device_isoc_methods) {
1304 /* isochronous transfer */
1305
1306 td = xfer->td_transfer_last;
1307
1308 usb_pc_cpu_invalidate(td->page_cache);
1309 status = le32toh(td->td_status);
1310
1311 /* check also if the first is complete */
1312
1313 td = xfer->td_transfer_first;
1314
1315 usb_pc_cpu_invalidate(td->page_cache);
1316 status |= le32toh(td->td_status);
1317
1318 if (!(status & UHCI_TD_ACTIVE)) {
1319 uhci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1320 goto transferred;
1321 }
1322 } else {
1323 /* non-isochronous transfer */
1324
1325 /*
1326 * check whether there is an error somewhere
1327 * in the middle, or whether there was a short
1328 * packet (SPD and not ACTIVE)
1329 */
1330 td = xfer->td_transfer_cache;
1331
1332 while (1) {
1333 usb_pc_cpu_invalidate(td->page_cache);
1334 status = le32toh(td->td_status);
1335 token = le32toh(td->td_token);
1336
1337 /*
1338 * if there is an active TD the transfer isn't done
1339 */
1340 if (status & UHCI_TD_ACTIVE) {
1341 /* update cache */
1342 xfer->td_transfer_cache = td;
1343 goto done;
1344 }
1345 /*
1346 * last transfer descriptor makes the transfer done
1347 */
1348 if (((void *)td) == xfer->td_transfer_last) {
1349 break;
1350 }
1351 /*
1352 * any kind of error makes the transfer done
1353 */
1354 if (status & UHCI_TD_STALLED) {
1355 break;
1356 }
1357 /*
1358 * check if we reached the last packet
1359 * or if there is a short packet:
1360 */
1361 if ((td->td_next == htole32(UHCI_PTR_T)) ||
1362 (UHCI_TD_GET_ACTLEN(status) < td->len)) {
1363 if (xfer->flags_int.short_frames_ok) {
1364 /* follow alt next */
1365 if (td->alt_next) {
1366 /* update cache */
1367 xfer->td_transfer_cache = td;
1368 uhci_check_transfer_sub(xfer);
1369 goto done;
1370 }
1371 }
1372 /* transfer is done */
1373 break;
1374 }
1375 td = td->obj_next;
1376 }
1377 uhci_non_isoc_done(xfer);
1378 goto transferred;
1379 }
1380
1381done:
1382 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1383 return (0);
1384
1385transferred:
1386 return (1);
1387}
1388
1389static void
1390uhci_interrupt_poll(uhci_softc_t *sc)
1391{
1392 struct usb_xfer *xfer;
1393
1394repeat:
1395 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1396 /*
1397 * check if transfer is transferred
1398 */
1399 if (uhci_check_transfer(xfer)) {
1400 /* queue has been modified */
1401 goto repeat;
1402 }
1403 }
1404}
1405
1406/*------------------------------------------------------------------------*
1407 * uhci_interrupt - UHCI interrupt handler
1408 *
1409 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1410 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1411 * is present !
1412 *------------------------------------------------------------------------*/
1413void
1414uhci_interrupt(uhci_softc_t *sc)
1415{
1416 uint32_t status;
1417
1418 USB_BUS_LOCK(&sc->sc_bus);
1419
1420 DPRINTFN(16, "real interrupt\n");
1421
1422#ifdef USB_DEBUG
1423 if (uhcidebug > 15) {
1424 uhci_dumpregs(sc);
1425 }
1426#endif
1427 status = UREAD2(sc, UHCI_STS) & UHCI_STS_ALLINTRS;
1428 if (status == 0) {
1429 /* the interrupt was not for us */
1430 goto done;
1431 }
1432 if (status & (UHCI_STS_RD | UHCI_STS_HSE |
1433 UHCI_STS_HCPE | UHCI_STS_HCH)) {
1434 if (status & UHCI_STS_RD) {
1435#ifdef USB_DEBUG
1436 printf("%s: resume detect\n",
1437 __FUNCTION__);
1438#endif
1439 }
1440 if (status & UHCI_STS_HSE) {
1441 printf("%s: host system error\n",
1442 __FUNCTION__);
1443 }
1444 if (status & UHCI_STS_HCPE) {
1445 printf("%s: host controller process error\n",
1446 __FUNCTION__);
1447 }
1448 if (status & UHCI_STS_HCH) {
1449 /* no acknowledge needed */
1450 DPRINTF("%s: host controller halted\n",
1451 __FUNCTION__);
1452#ifdef USB_DEBUG
1453 if (uhcidebug > 0) {
1454 uhci_dump_all(sc);
1455 }
1456#endif
1457 }
1458 }
1459 /* get acknowledge bits */
1460 status &= (UHCI_STS_USBINT |
1461 UHCI_STS_USBEI |
1462 UHCI_STS_RD |
1463 UHCI_STS_HSE |
1464 UHCI_STS_HCPE |
1465 UHCI_STS_HCH);
1466
1467 if (status == 0) {
1468 /* nothing to acknowledge */
1469 goto done;
1470 }
1471 /* acknowledge interrupts */
1472 UWRITE2(sc, UHCI_STS, status);
1473
1474 /* poll all the USB transfers */
1475 uhci_interrupt_poll(sc);
1476
1477done:
1478 USB_BUS_UNLOCK(&sc->sc_bus);
1479}
1480
1481/*
1482 * called when a request does not complete
1483 */
1484static void
1485uhci_timeout(void *arg)
1486{
1487 struct usb_xfer *xfer = arg;
1488
1489 DPRINTF("xfer=%p\n", xfer);
1490
1491 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1492
1493 /* transfer is transferred */
1494 uhci_device_done(xfer, USB_ERR_TIMEOUT);
1495}
1496
1497static void
1498uhci_do_poll(struct usb_bus *bus)
1499{
1500 struct uhci_softc *sc = UHCI_BUS2SC(bus);
1501
1502 USB_BUS_LOCK(&sc->sc_bus);
1503 uhci_interrupt_poll(sc);
1504 USB_BUS_UNLOCK(&sc->sc_bus);
1505}
1506
1507static void
1508uhci_setup_standard_chain_sub(struct uhci_std_temp *temp)
1509{
1510 uhci_td_t *td;
1511 uhci_td_t *td_next;
1512 uhci_td_t *td_alt_next;
1513 uint32_t average;
1514 uint32_t len_old;
1515 uint8_t shortpkt_old;
1516 uint8_t precompute;
1517
1518 td_alt_next = NULL;
1519 shortpkt_old = temp->shortpkt;
1520 len_old = temp->len;
1521 precompute = 1;
1522
1523 /* software is used to detect short incoming transfers */
1524
1525 if ((temp->td_token & htole32(UHCI_TD_PID)) == htole32(UHCI_TD_PID_IN)) {
1526 temp->td_status |= htole32(UHCI_TD_SPD);
1527 } else {
1528 temp->td_status &= ~htole32(UHCI_TD_SPD);
1529 }
1530
1531 temp->ml.buf_offset = 0;
1532
1533restart:
1534
1535 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0));
1536 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->average));
1537
1538 td = temp->td;
1539 td_next = temp->td_next;
1540
1541 while (1) {
1542 if (temp->len == 0) {
1543 if (temp->shortpkt) {
1544 break;
1545 }
1546 /* send a Zero Length Packet, ZLP, last */
1547
1548 temp->shortpkt = 1;
1549 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(0));
1550 average = 0;
1551
1552 } else {
1553 average = temp->average;
1554
1555 if (temp->len < average) {
1556 temp->shortpkt = 1;
1557 temp->td_token &= ~htole32(UHCI_TD_SET_MAXLEN(0));
1558 temp->td_token |= htole32(UHCI_TD_SET_MAXLEN(temp->len));
1559 average = temp->len;
1560 }
1561 }
1562
1563 if (td_next == NULL) {
1564 panic("%s: out of UHCI transfer descriptors!", __FUNCTION__);
1565 }
1566 /* get next TD */
1567
1568 td = td_next;
1569 td_next = td->obj_next;
1570
1571 /* check if we are pre-computing */
1572
1573 if (precompute) {
1574 /* update remaining length */
1575
1576 temp->len -= average;
1577
1578 continue;
1579 }
1580 /* fill out current TD */
1581
1582 td->td_status = temp->td_status;
1583 td->td_token = temp->td_token;
1584
1585 /* update data toggle */
1586
1587 temp->td_token ^= htole32(UHCI_TD_SET_DT(1));
1588
1589 if (average == 0) {
1590 td->len = 0;
1591 td->td_buffer = 0;
1592 td->fix_pc = NULL;
1593
1594 } else {
1595 /* update remaining length */
1596
1597 temp->len -= average;
1598
1599 td->len = average;
1600
1601 /* fill out buffer pointer and do fixup, if any */
1602
1603 uhci_mem_layout_fixup(&temp->ml, td);
1604 }
1605
1606 td->alt_next = td_alt_next;
1607
1608 if ((td_next == td_alt_next) && temp->setup_alt_next) {
1609 /* we need to receive these frames one by one ! */
1610 td->td_status |= htole32(UHCI_TD_IOC);
1611 td->td_next = htole32(UHCI_PTR_T);
1612 } else {
1613 if (td_next) {
1614 /* link the current TD with the next one */
1615 td->td_next = td_next->td_self;
1616 }
1617 }
1618
1619 usb_pc_cpu_flush(td->page_cache);
1620 }
1621
1622 if (precompute) {
1623 precompute = 0;
1624
1625 /* setup alt next pointer, if any */
1626 if (temp->last_frame) {
1627 td_alt_next = NULL;
1628 } else {
1629 /* we use this field internally */
1630 td_alt_next = td_next;
1631 }
1632
1633 /* restore */
1634 temp->shortpkt = shortpkt_old;
1635 temp->len = len_old;
1636 goto restart;
1637 }
1638 temp->td = td;
1639 temp->td_next = td_next;
1640}
1641
1642static uhci_td_t *
1643uhci_setup_standard_chain(struct usb_xfer *xfer)
1644{
1645 struct uhci_std_temp temp;
1646 uhci_td_t *td;
1647 uint32_t x;
1648
1649 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1650 xfer->address, UE_GET_ADDR(xfer->endpointno),
1651 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1652
1653 temp.average = xfer->max_frame_size;
1654 temp.max_frame_size = xfer->max_frame_size;
1655
1656 /* toggle the DMA set we are using */
1657 xfer->flags_int.curr_dma_set ^= 1;
1658
1659 /* get next DMA set */
1660 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1661 xfer->td_transfer_first = td;
1662 xfer->td_transfer_cache = td;
1663
1664 temp.td = NULL;
1665 temp.td_next = td;
1666 temp.last_frame = 0;
1667 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1668
1669 uhci_mem_layout_init(&temp.ml, xfer);
1670
1671 temp.td_status =
1672 htole32(UHCI_TD_ZERO_ACTLEN(UHCI_TD_SET_ERRCNT(3) |
1673 UHCI_TD_ACTIVE));
1674
1675 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1676 temp.td_status |= htole32(UHCI_TD_LS);
1677 }
1678 temp.td_token =
1679 htole32(UHCI_TD_SET_ENDPT(xfer->endpointno) |
1680 UHCI_TD_SET_DEVADDR(xfer->address));
1681
1682 if (xfer->endpoint->toggle_next) {
1683 /* DATA1 is next */
1684 temp.td_token |= htole32(UHCI_TD_SET_DT(1));
1685 }
1686 /* check if we should prepend a setup message */
1687
1688 if (xfer->flags_int.control_xfr) {
1689 if (xfer->flags_int.control_hdr) {
1690 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1691 UHCI_TD_SET_ENDPT(0xF));
1692 temp.td_token |= htole32(UHCI_TD_PID_SETUP |
1693 UHCI_TD_SET_DT(0));
1694
1695 temp.len = xfer->frlengths[0];
1696 temp.ml.buf_pc = xfer->frbuffers + 0;
1697 temp.shortpkt = temp.len ? 1 : 0;
1698 /* check for last frame */
1699 if (xfer->nframes == 1) {
1700 /* no STATUS stage yet, SETUP is last */
1701 if (xfer->flags_int.control_act) {
1702 temp.last_frame = 1;
1703 temp.setup_alt_next = 0;
1704 }
1705 }
1706 uhci_setup_standard_chain_sub(&temp);
1707 }
1708 x = 1;
1709 } else {
1710 x = 0;
1711 }
1712
1713 while (x != xfer->nframes) {
1714 /* DATA0 / DATA1 message */
1715
1716 temp.len = xfer->frlengths[x];
1717 temp.ml.buf_pc = xfer->frbuffers + x;
1718
1719 x++;
1720
1721 if (x == xfer->nframes) {
1722 if (xfer->flags_int.control_xfr) {
1723 /* no STATUS stage yet, DATA is last */
1724 if (xfer->flags_int.control_act) {
1725 temp.last_frame = 1;
1726 temp.setup_alt_next = 0;
1727 }
1728 } else {
1729 temp.last_frame = 1;
1730 temp.setup_alt_next = 0;
1731 }
1732 }
1733 /*
1734 * Keep previous data toggle,
1735 * device address and endpoint number:
1736 */
1737
1738 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1739 UHCI_TD_SET_ENDPT(0xF) |
1740 UHCI_TD_SET_DT(1));
1741
1742 if (temp.len == 0) {
1743 /* make sure that we send an USB packet */
1744
1745 temp.shortpkt = 0;
1746
1747 } else {
1748 /* regular data transfer */
1749
1750 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1751 }
1752
1753 /* set endpoint direction */
1754
1755 temp.td_token |=
1756 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1757 htole32(UHCI_TD_PID_IN) :
1758 htole32(UHCI_TD_PID_OUT);
1759
1760 uhci_setup_standard_chain_sub(&temp);
1761 }
1762
1763 /* check if we should append a status stage */
1764
1765 if (xfer->flags_int.control_xfr &&
1766 !xfer->flags_int.control_act) {
1767 /*
1768 * send a DATA1 message and reverse the current endpoint
1769 * direction
1770 */
1771
1772 temp.td_token &= htole32(UHCI_TD_SET_DEVADDR(0x7F) |
1773 UHCI_TD_SET_ENDPT(0xF) |
1774 UHCI_TD_SET_DT(1));
1775 temp.td_token |=
1776 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1777 htole32(UHCI_TD_PID_IN | UHCI_TD_SET_DT(1)) :
1778 htole32(UHCI_TD_PID_OUT | UHCI_TD_SET_DT(1));
1779
1780 temp.len = 0;
1781 temp.ml.buf_pc = NULL;
1782 temp.shortpkt = 0;
1783 temp.last_frame = 1;
1784 temp.setup_alt_next = 0;
1785
1786 uhci_setup_standard_chain_sub(&temp);
1787 }
1788 td = temp.td;
1789
1790 /* Ensure that last TD is terminating: */
1791 td->td_next = htole32(UHCI_PTR_T);
1792
1793 /* set interrupt bit */
1794
1795 td->td_status |= htole32(UHCI_TD_IOC);
1796
1797 usb_pc_cpu_flush(td->page_cache);
1798
1799 /* must have at least one frame! */
1800
1801 xfer->td_transfer_last = td;
1802
1803#ifdef USB_DEBUG
1804 if (uhcidebug > 8) {
1805 DPRINTF("nexttog=%d; data before transfer:\n",
1806 xfer->endpoint->toggle_next);
1807 uhci_dump_tds(xfer->td_transfer_first);
1808 }
1809#endif
1810 return (xfer->td_transfer_first);
1811}
1812
1813/* NOTE: "done" can be run two times in a row,
1814 * from close and from interrupt
1815 */
1816
1817static void
1818uhci_device_done(struct usb_xfer *xfer, usb_error_t error)
1819{
1820 const struct usb_pipe_methods *methods = xfer->endpoint->methods;
1821 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1822 uhci_qh_t *qh;
1823
1824 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1825
1826 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
1827 xfer, xfer->endpoint, error);
1828
1829 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1830 if (qh) {
1831 usb_pc_cpu_invalidate(qh->page_cache);
1832 }
1833 if (xfer->flags_int.bandwidth_reclaimed) {
1834 xfer->flags_int.bandwidth_reclaimed = 0;
1835 uhci_rem_loop(sc);
1836 }
1837 if (methods == &uhci_device_bulk_methods) {
1838 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last);
1839 }
1840 if (methods == &uhci_device_ctrl_methods) {
1841 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1842 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last);
1843 } else {
1844 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last);
1845 }
1846 }
1847 if (methods == &uhci_device_intr_methods) {
1848 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
1849 }
1850 /*
1851 * Only finish isochronous transfers once
1852 * which will update "xfer->frlengths".
1853 */
1854 if (xfer->td_transfer_first &&
1855 xfer->td_transfer_last) {
1856 if (methods == &uhci_device_isoc_methods) {
1857 uhci_isoc_done(sc, xfer);
1858 }
1859 xfer->td_transfer_first = NULL;
1860 xfer->td_transfer_last = NULL;
1861 }
1862 /* dequeue transfer and start next transfer */
1863 usbd_transfer_done(xfer, error);
1864}
1865
1866/*------------------------------------------------------------------------*
1867 * uhci bulk support
1868 *------------------------------------------------------------------------*/
1869static void
1870uhci_device_bulk_open(struct usb_xfer *xfer)
1871{
1872 return;
1873}
1874
1875static void
1876uhci_device_bulk_close(struct usb_xfer *xfer)
1877{
1878 uhci_device_done(xfer, USB_ERR_CANCELLED);
1879}
1880
1881static void
1882uhci_device_bulk_enter(struct usb_xfer *xfer)
1883{
1884 return;
1885}
1886
1887static void
1888uhci_device_bulk_start(struct usb_xfer *xfer)
1889{
1890 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1891 uhci_td_t *td;
1892 uhci_qh_t *qh;
1893
1894 /* setup TD's */
1895 td = uhci_setup_standard_chain(xfer);
1896
1897 /* setup QH */
1898 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1899
1900 qh->e_next = td;
1901 qh->qh_e_next = td->td_self;
1902
1903 if (xfer->xroot->udev->flags.self_suspended == 0) {
1904 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last);
1905 uhci_add_loop(sc);
1906 xfer->flags_int.bandwidth_reclaimed = 1;
1907 } else {
1908 usb_pc_cpu_flush(qh->page_cache);
1909 }
1910
1911 /* put transfer on interrupt queue */
1912 uhci_transfer_intr_enqueue(xfer);
1913}
1914
1915static const struct usb_pipe_methods uhci_device_bulk_methods =
1916{
1917 .open = uhci_device_bulk_open,
1918 .close = uhci_device_bulk_close,
1919 .enter = uhci_device_bulk_enter,
1920 .start = uhci_device_bulk_start,
1921};
1922
1923/*------------------------------------------------------------------------*
1924 * uhci control support
1925 *------------------------------------------------------------------------*/
1926static void
1927uhci_device_ctrl_open(struct usb_xfer *xfer)
1928{
1929 return;
1930}
1931
1932static void
1933uhci_device_ctrl_close(struct usb_xfer *xfer)
1934{
1935 uhci_device_done(xfer, USB_ERR_CANCELLED);
1936}
1937
1938static void
1939uhci_device_ctrl_enter(struct usb_xfer *xfer)
1940{
1941 return;
1942}
1943
1944static void
1945uhci_device_ctrl_start(struct usb_xfer *xfer)
1946{
1947 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1948 uhci_qh_t *qh;
1949 uhci_td_t *td;
1950
1951 /* setup TD's */
1952 td = uhci_setup_standard_chain(xfer);
1953
1954 /* setup QH */
1955 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1956
1957 qh->e_next = td;
1958 qh->qh_e_next = td->td_self;
1959
1960 /*
1961 * NOTE: some devices choke on bandwidth- reclamation for control
1962 * transfers
1963 */
1964 if (xfer->xroot->udev->flags.self_suspended == 0) {
1965 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
1966 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last);
1967 } else {
1968 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last);
1969 }
1970 } else {
1971 usb_pc_cpu_flush(qh->page_cache);
1972 }
1973 /* put transfer on interrupt queue */
1974 uhci_transfer_intr_enqueue(xfer);
1975}
1976
1977static const struct usb_pipe_methods uhci_device_ctrl_methods =
1978{
1979 .open = uhci_device_ctrl_open,
1980 .close = uhci_device_ctrl_close,
1981 .enter = uhci_device_ctrl_enter,
1982 .start = uhci_device_ctrl_start,
1983};
1984
1985/*------------------------------------------------------------------------*
1986 * uhci interrupt support
1987 *------------------------------------------------------------------------*/
1988static void
1989uhci_device_intr_open(struct usb_xfer *xfer)
1990{
1991 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
1992 uint16_t best;
1993 uint16_t bit;
1994 uint16_t x;
1995
1996 best = 0;
1997 bit = UHCI_IFRAMELIST_COUNT / 2;
1998 while (bit) {
1999 if (xfer->interval >= bit) {
2000 x = bit;
2001 best = bit;
2002 while (x & bit) {
2003 if (sc->sc_intr_stat[x] <
2004 sc->sc_intr_stat[best]) {
2005 best = x;
2006 }
2007 x++;
2008 }
2009 break;
2010 }
2011 bit >>= 1;
2012 }
2013
2014 sc->sc_intr_stat[best]++;
2015 xfer->qh_pos = best;
2016
2017 DPRINTFN(3, "best=%d interval=%d\n",
2018 best, xfer->interval);
2019}
2020
2021static void
2022uhci_device_intr_close(struct usb_xfer *xfer)
2023{
2024 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2025
2026 sc->sc_intr_stat[xfer->qh_pos]--;
2027
2028 uhci_device_done(xfer, USB_ERR_CANCELLED);
2029}
2030
2031static void
2032uhci_device_intr_enter(struct usb_xfer *xfer)
2033{
2034 return;
2035}
2036
2037static void
2038uhci_device_intr_start(struct usb_xfer *xfer)
2039{
2040 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2041 uhci_qh_t *qh;
2042 uhci_td_t *td;
2043
2044 /* setup TD's */
2045 td = uhci_setup_standard_chain(xfer);
2046
2047 /* setup QH */
2048 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
2049
2050 qh->e_next = td;
2051 qh->qh_e_next = td->td_self;
2052
2053 if (xfer->xroot->udev->flags.self_suspended == 0) {
2054 /* enter QHs into the controller data structures */
2055 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
2056 } else {
2057 usb_pc_cpu_flush(qh->page_cache);
2058 }
2059
2060 /* put transfer on interrupt queue */
2061 uhci_transfer_intr_enqueue(xfer);
2062}
2063
2064static const struct usb_pipe_methods uhci_device_intr_methods =
2065{
2066 .open = uhci_device_intr_open,
2067 .close = uhci_device_intr_close,
2068 .enter = uhci_device_intr_enter,
2069 .start = uhci_device_intr_start,
2070};
2071
2072/*------------------------------------------------------------------------*
2073 * uhci isochronous support
2074 *------------------------------------------------------------------------*/
2075static void
2076uhci_device_isoc_open(struct usb_xfer *xfer)
2077{
2078 uhci_td_t *td;
2079 uint32_t td_token;
2080 uint8_t ds;
2081
2082 td_token =
2083 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
2084 UHCI_TD_IN(0, xfer->endpointno, xfer->address, 0) :
2085 UHCI_TD_OUT(0, xfer->endpointno, xfer->address, 0);
2086
2087 td_token = htole32(td_token);
2088
2089 /* initialize all TD's */
2090
2091 for (ds = 0; ds != 2; ds++) {
2092 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2093 /* mark TD as inactive */
2094 td->td_status = htole32(UHCI_TD_IOS);
2095 td->td_token = td_token;
2096
2097 usb_pc_cpu_flush(td->page_cache);
2098 }
2099 }
2100}
2101
2102static void
2103uhci_device_isoc_close(struct usb_xfer *xfer)
2104{
2105 uhci_device_done(xfer, USB_ERR_CANCELLED);
2106}
2107
2108static void
2109uhci_device_isoc_enter(struct usb_xfer *xfer)
2110{
2111 struct uhci_mem_layout ml;
2112 uhci_softc_t *sc = UHCI_BUS2SC(xfer->xroot->bus);
2113 uint32_t nframes;
2114 uint32_t startframe;
2115 uint32_t *plen;
2116
2117#ifdef USB_DEBUG
2118 uint8_t once = 1;
2119
2120#endif
2121 uhci_td_t *td;
2122 uhci_td_t *td_last = NULL;
2123 uhci_td_t **pp_last;
2124
2125 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2126 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2127
2128 nframes = UREAD2(sc, UHCI_FRNUM);
2129
2130 if (usbd_xfer_get_isochronous_start_frame(
2131 xfer, nframes, 0, 1, UHCI_VFRAMELIST_COUNT - 1, &startframe))
2132 DPRINTFN(3, "start next=%d\n", startframe);
2133
2134 /* get the real number of frames */
2135
2136 nframes = xfer->nframes;
2137
2138 uhci_mem_layout_init(&ml, xfer);
2139
2140 plen = xfer->frlengths;
2141
2142 /* toggle the DMA set we are using */
2143 xfer->flags_int.curr_dma_set ^= 1;
2144
2145 /* get next DMA set */
2146 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2147 xfer->td_transfer_first = td;
2148
2149 pp_last = &sc->sc_isoc_p_last[startframe];
2150
2151 /* store starting position */
2152
2153 xfer->qh_pos = startframe;
2154
2155 while (nframes--) {
2156 if (td == NULL) {
2157 panic("%s:%d: out of TD's\n",
2158 __FUNCTION__, __LINE__);
2159 }
2160 if (pp_last >= &sc->sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]) {
2161 pp_last = &sc->sc_isoc_p_last[0];
2162 }
2163 if (*plen > xfer->max_frame_size) {
2164#ifdef USB_DEBUG
2165 if (once) {
2166 once = 0;
2167 printf("%s: frame length(%d) exceeds %d "
2168 "bytes (frame truncated)\n",
2169 __FUNCTION__, *plen,
2170 xfer->max_frame_size);
2171 }
2172#endif
2173 *plen = xfer->max_frame_size;
2174 }
2175 /* reuse td_token from last transfer */
2176
2177 td->td_token &= htole32(~UHCI_TD_MAXLEN_MASK);
2178 td->td_token |= htole32(UHCI_TD_SET_MAXLEN(*plen));
2179
2180 td->len = *plen;
2181
2182 if (td->len == 0) {
2183 /*
2184 * Do not call "uhci_mem_layout_fixup()" when the
2185 * length is zero!
2186 */
2187 td->td_buffer = 0;
2188 td->fix_pc = NULL;
2189
2190 } else {
2191 /* fill out buffer pointer and do fixup, if any */
2192
2193 uhci_mem_layout_fixup(&ml, td);
2194 }
2195
2196 /* update status */
2197 if (nframes == 0) {
2198 td->td_status = htole32
2199 (UHCI_TD_ZERO_ACTLEN
2200 (UHCI_TD_SET_ERRCNT(0) |
2201 UHCI_TD_ACTIVE |
2202 UHCI_TD_IOS |
2203 UHCI_TD_IOC));
2204 } else {
2205 td->td_status = htole32
2206 (UHCI_TD_ZERO_ACTLEN
2207 (UHCI_TD_SET_ERRCNT(0) |
2208 UHCI_TD_ACTIVE |
2209 UHCI_TD_IOS));
2210 }
2211
2212 usb_pc_cpu_flush(td->page_cache);
2213
2214#ifdef USB_DEBUG
2215 if (uhcidebug > 5) {
2216 DPRINTF("TD %d\n", nframes);
2217 uhci_dump_td(td);
2218 }
2219#endif
2220 /* insert TD into schedule */
2221 UHCI_APPEND_TD(td, *pp_last);
2222 pp_last++;
2223
2224 plen++;
2225 td_last = td;
2226 td = td->obj_next;
2227 }
2228
2229 xfer->td_transfer_last = td_last;
2230}
2231
2232static void
2233uhci_device_isoc_start(struct usb_xfer *xfer)
2234{
2235 /* put transfer on interrupt queue */
2236 uhci_transfer_intr_enqueue(xfer);
2237}
2238
2239static const struct usb_pipe_methods uhci_device_isoc_methods =
2240{
2241 .open = uhci_device_isoc_open,
2242 .close = uhci_device_isoc_close,
2243 .enter = uhci_device_isoc_enter,
2244 .start = uhci_device_isoc_start,
2245};
2246
2247/*------------------------------------------------------------------------*
2248 * uhci root control support
2249 *------------------------------------------------------------------------*
2250 * Simulate a hardware hub by handling all the necessary requests.
2251 *------------------------------------------------------------------------*/
2252
2253static const
2254struct usb_device_descriptor uhci_devd =
2255{
2256 sizeof(struct usb_device_descriptor),
2257 UDESC_DEVICE, /* type */
2258 {0x00, 0x01}, /* USB version */
2259 UDCLASS_HUB, /* class */
2260 UDSUBCLASS_HUB, /* subclass */
2261 UDPROTO_FSHUB, /* protocol */
2262 64, /* max packet */
2263 {0}, {0}, {0x00, 0x01}, /* device id */
2264 1, 2, 0, /* string indexes */
2265 1 /* # of configurations */
2266};
2267
2268static const struct uhci_config_desc uhci_confd = {
2269 .confd = {
2270 .bLength = sizeof(struct usb_config_descriptor),
2271 .bDescriptorType = UDESC_CONFIG,
2272 .wTotalLength[0] = sizeof(uhci_confd),
2273 .bNumInterface = 1,
2274 .bConfigurationValue = 1,
2275 .iConfiguration = 0,
2276 .bmAttributes = UC_SELF_POWERED,
2277 .bMaxPower = 0 /* max power */
2278 },
2279 .ifcd = {
2280 .bLength = sizeof(struct usb_interface_descriptor),
2281 .bDescriptorType = UDESC_INTERFACE,
2282 .bNumEndpoints = 1,
2283 .bInterfaceClass = UICLASS_HUB,
2284 .bInterfaceSubClass = UISUBCLASS_HUB,
2285 .bInterfaceProtocol = UIPROTO_FSHUB,
2286 },
2287 .endpd = {
2288 .bLength = sizeof(struct usb_endpoint_descriptor),
2289 .bDescriptorType = UDESC_ENDPOINT,
2290 .bEndpointAddress = UE_DIR_IN | UHCI_INTR_ENDPT,
2291 .bmAttributes = UE_INTERRUPT,
2292 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
2293 .bInterval = 255,
2294 },
2295};
2296
2297static const
2298struct usb_hub_descriptor_min uhci_hubd_piix =
2299{
2300 .bDescLength = sizeof(uhci_hubd_piix),
2301 .bDescriptorType = UDESC_HUB,
2302 .bNbrPorts = 2,
2303 .wHubCharacteristics = {UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0},
2304 .bPwrOn2PwrGood = 50,
2305};
2306
2307/*
2308 * The USB hub protocol requires that SET_FEATURE(PORT_RESET) also
2309 * enables the port, and also states that SET_FEATURE(PORT_ENABLE)
2310 * should not be used by the USB subsystem. As we cannot issue a
2311 * SET_FEATURE(PORT_ENABLE) externally, we must ensure that the port
2312 * will be enabled as part of the reset.
2313 *
2314 * On the VT83C572, the port cannot be successfully enabled until the
2315 * outstanding "port enable change" and "connection status change"
2316 * events have been reset.
2317 */
2318static usb_error_t
2319uhci_portreset(uhci_softc_t *sc, uint16_t index)
2320{
2321 uint16_t port;
2322 uint16_t x;
2323 uint8_t lim;
2324
2325 if (index == 1)
2326 port = UHCI_PORTSC1;
2327 else if (index == 2)
2328 port = UHCI_PORTSC2;
2329 else
2330 return (USB_ERR_IOERROR);
2331
2332 /*
2333 * Before we do anything, turn on SOF messages on the USB
2334 * BUS. Some USB devices do not cope without them!
2335 */
2336 uhci_restart(sc);
2337
2338 x = URWMASK(UREAD2(sc, port));
2339 UWRITE2(sc, port, x | UHCI_PORTSC_PR);
2340
2341 usb_pause_mtx(&sc->sc_bus.bus_mtx,
2342 USB_MS_TO_TICKS(usb_port_root_reset_delay));
2343
2344 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n",
2345 index, UREAD2(sc, port));
2346
2347 x = URWMASK(UREAD2(sc, port));
2348 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
2349
2350 mtx_unlock(&sc->sc_bus.bus_mtx);
2351
2352 /*
2353 * This delay needs to be exactly 100us, else some USB devices
2354 * fail to attach!
2355 */
2356 DELAY(100);
2357
2358 mtx_lock(&sc->sc_bus.bus_mtx);
2359
2360 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n",
2361 index, UREAD2(sc, port));
2362
2363 x = URWMASK(UREAD2(sc, port));
2364 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
2365
2366 for (lim = 0; lim < 12; lim++) {
2367 usb_pause_mtx(&sc->sc_bus.bus_mtx,
2368 USB_MS_TO_TICKS(usb_port_reset_delay));
2369
2370 x = UREAD2(sc, port);
2371
2372 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n",
2373 index, lim, x);
2374
2375 if (!(x & UHCI_PORTSC_CCS)) {
2376 /*
2377 * No device is connected (or was disconnected
2378 * during reset). Consider the port reset.
2379 * The delay must be long enough to ensure on
2380 * the initial iteration that the device
2381 * connection will have been registered. 50ms
2382 * appears to be sufficient, but 20ms is not.
2383 */
2384 DPRINTFN(4, "uhci port %d loop %u, device detached\n",
2385 index, lim);
2386 goto done;
2387 }
2388 if (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)) {
2389 /*
2390 * Port enabled changed and/or connection
2391 * status changed were set. Reset either or
2392 * both raised flags (by writing a 1 to that
2393 * bit), and wait again for state to settle.
2394 */
2395 UWRITE2(sc, port, URWMASK(x) |
2396 (x & (UHCI_PORTSC_POEDC | UHCI_PORTSC_CSC)));
2397 continue;
2398 }
2399 if (x & UHCI_PORTSC_PE) {
2400 /* port is enabled */
2401 goto done;
2402 }
2403 UWRITE2(sc, port, URWMASK(x) | UHCI_PORTSC_PE);
2404 }
2405
2406 DPRINTFN(2, "uhci port %d reset timed out\n", index);
2407 return (USB_ERR_TIMEOUT);
2408
2409done:
2410 DPRINTFN(4, "uhci port %d reset, status2 = 0x%04x\n",
2411 index, UREAD2(sc, port));
2412
2413 sc->sc_isreset = 1;
2414 return (USB_ERR_NORMAL_COMPLETION);
2415}
2416
2417static usb_error_t
2418uhci_roothub_exec(struct usb_device *udev,
2419 struct usb_device_request *req, const void **pptr, uint16_t *plength)
2420{
2421 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus);
2422 const void *ptr;
2423 const char *str_ptr;
2424 uint16_t x;
2425 uint16_t port;
2426 uint16_t value;
2427 uint16_t index;
2428 uint16_t status;
2429 uint16_t change;
2430 uint16_t len;
2431 usb_error_t err;
2432
2433 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2434
2435 /* buffer reset */
2436 ptr = (const void *)&sc->sc_hub_desc.temp;
2437 len = 0;
2438 err = 0;
2439
2440 value = UGETW(req->wValue);
2441 index = UGETW(req->wIndex);
2442
2443 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
2444 "wValue=0x%04x wIndex=0x%04x\n",
2445 req->bmRequestType, req->bRequest,
2446 UGETW(req->wLength), value, index);
2447
2448#define C(x,y) ((x) | ((y) << 8))
2449 switch (C(req->bRequest, req->bmRequestType)) {
2450 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
2451 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
2452 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
2453 /*
2454 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
2455 * for the integrated root hub.
2456 */
2457 break;
2458 case C(UR_GET_CONFIG, UT_READ_DEVICE):
2459 len = 1;
2460 sc->sc_hub_desc.temp[0] = sc->sc_conf;
2461 break;
2462 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2463 switch (value >> 8) {
2464 case UDESC_DEVICE:
2465 if ((value & 0xff) != 0) {
2466 err = USB_ERR_IOERROR;
2467 goto done;
2468 }
2469 len = sizeof(uhci_devd);
2470 ptr = (const void *)&uhci_devd;
2471 break;
2472
2473 case UDESC_CONFIG:
2474 if ((value & 0xff) != 0) {
2475 err = USB_ERR_IOERROR;
2476 goto done;
2477 }
2478 len = sizeof(uhci_confd);
2479 ptr = (const void *)&uhci_confd;
2480 break;
2481
2482 case UDESC_STRING:
2483 switch (value & 0xff) {
2484 case 0: /* Language table */
2485 str_ptr = "\001";
2486 break;
2487
2488 case 1: /* Vendor */
2489 str_ptr = sc->sc_vendor;
2490 break;
2491
2492 case 2: /* Product */
2493 str_ptr = "UHCI root HUB";
2494 break;
2495
2496 default:
2497 str_ptr = "";
2498 break;
2499 }
2500
2501 len = usb_make_str_desc
2502 (sc->sc_hub_desc.temp,
2503 sizeof(sc->sc_hub_desc.temp),
2504 str_ptr);
2505 break;
2506
2507 default:
2508 err = USB_ERR_IOERROR;
2509 goto done;
2510 }
2511 break;
2512 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
2513 len = 1;
2514 sc->sc_hub_desc.temp[0] = 0;
2515 break;
2516 case C(UR_GET_STATUS, UT_READ_DEVICE):
2517 len = 2;
2518 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
2519 break;
2520 case C(UR_GET_STATUS, UT_READ_INTERFACE):
2521 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
2522 len = 2;
2523 USETW(sc->sc_hub_desc.stat.wStatus, 0);
2524 break;
2525 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
2526 if (value >= UHCI_MAX_DEVICES) {
2527 err = USB_ERR_IOERROR;
2528 goto done;
2529 }
2530 sc->sc_addr = value;
2531 break;
2532 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
2533 if ((value != 0) && (value != 1)) {
2534 err = USB_ERR_IOERROR;
2535 goto done;
2536 }
2537 sc->sc_conf = value;
2538 break;
2539 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
2540 break;
2541 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
2542 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
2543 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
2544 err = USB_ERR_IOERROR;
2545 goto done;
2546 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
2547 break;
2548 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
2549 break;
2550 /* Hub requests */
2551 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2552 break;
2553 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2554 DPRINTFN(4, "UR_CLEAR_PORT_FEATURE "
2555 "port=%d feature=%d\n",
2556 index, value);
2557 if (index == 1)
2558 port = UHCI_PORTSC1;
2559 else if (index == 2)
2560 port = UHCI_PORTSC2;
2561 else {
2562 err = USB_ERR_IOERROR;
2563 goto done;
2564 }
2565 switch (value) {
2566 case UHF_PORT_ENABLE:
2567 x = URWMASK(UREAD2(sc, port));
2568 UWRITE2(sc, port, x & ~UHCI_PORTSC_PE);
2569 break;
2570 case UHF_PORT_SUSPEND:
2571 x = URWMASK(UREAD2(sc, port));
2572 UWRITE2(sc, port, x & ~(UHCI_PORTSC_SUSP));
2573 break;
2574 case UHF_PORT_RESET:
2575 x = URWMASK(UREAD2(sc, port));
2576 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
2577 break;
2578 case UHF_C_PORT_CONNECTION:
2579 x = URWMASK(UREAD2(sc, port));
2580 UWRITE2(sc, port, x | UHCI_PORTSC_CSC);
2581 break;
2582 case UHF_C_PORT_ENABLE:
2583 x = URWMASK(UREAD2(sc, port));
2584 UWRITE2(sc, port, x | UHCI_PORTSC_POEDC);
2585 break;
2586 case UHF_C_PORT_OVER_CURRENT:
2587 x = URWMASK(UREAD2(sc, port));
2588 UWRITE2(sc, port, x | UHCI_PORTSC_OCIC);
2589 break;
2590 case UHF_C_PORT_RESET:
2591 sc->sc_isreset = 0;
2592 err = USB_ERR_NORMAL_COMPLETION;
2593 goto done;
2594 case UHF_C_PORT_SUSPEND:
2595 sc->sc_isresumed &= ~(1 << index);
2596 break;
2597 case UHF_PORT_CONNECTION:
2598 case UHF_PORT_OVER_CURRENT:
2599 case UHF_PORT_POWER:
2600 case UHF_PORT_LOW_SPEED:
2601 default:
2602 err = USB_ERR_IOERROR;
2603 goto done;
2604 }
2605 break;
2606 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER):
2607 if (index == 1)
2608 port = UHCI_PORTSC1;
2609 else if (index == 2)
2610 port = UHCI_PORTSC2;
2611 else {
2612 err = USB_ERR_IOERROR;
2613 goto done;
2614 }
2615 len = 1;
2616 sc->sc_hub_desc.temp[0] =
2617 ((UREAD2(sc, port) & UHCI_PORTSC_LS) >>
2618 UHCI_PORTSC_LS_SHIFT);
2619 break;
2620 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2621 if ((value & 0xff) != 0) {
2622 err = USB_ERR_IOERROR;
2623 goto done;
2624 }
2625 len = sizeof(uhci_hubd_piix);
2626 ptr = (const void *)&uhci_hubd_piix;
2627 break;
2628 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2629 len = 16;
2630 memset(sc->sc_hub_desc.temp, 0, 16);
2631 break;
2632 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2633 if (index == 1)
2634 port = UHCI_PORTSC1;
2635 else if (index == 2)
2636 port = UHCI_PORTSC2;
2637 else {
2638 err = USB_ERR_IOERROR;
2639 goto done;
2640 }
2641 x = UREAD2(sc, port);
2642 status = change = 0;
2643 if (x & UHCI_PORTSC_CCS)
2644 status |= UPS_CURRENT_CONNECT_STATUS;
2645 if (x & UHCI_PORTSC_CSC)
2646 change |= UPS_C_CONNECT_STATUS;
2647 if (x & UHCI_PORTSC_PE)
2648 status |= UPS_PORT_ENABLED;
2649 if (x & UHCI_PORTSC_POEDC)
2650 change |= UPS_C_PORT_ENABLED;
2651 if (x & UHCI_PORTSC_OCI)
2652 status |= UPS_OVERCURRENT_INDICATOR;
2653 if (x & UHCI_PORTSC_OCIC)
2654 change |= UPS_C_OVERCURRENT_INDICATOR;
2655 if (x & UHCI_PORTSC_LSDA)
2656 status |= UPS_LOW_SPEED;
2657 if ((x & UHCI_PORTSC_PE) && (x & UHCI_PORTSC_RD)) {
2658 /* need to do a write back */
2659 UWRITE2(sc, port, URWMASK(x));
2660
2661 /* wait 20ms for resume sequence to complete */
2662 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
2663
2664 /* clear suspend and resume detect */
2665 UWRITE2(sc, port, URWMASK(x) & ~(UHCI_PORTSC_RD |
2666 UHCI_PORTSC_SUSP));
2667
2668 /* wait a little bit */
2669 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 500);
2670
2671 sc->sc_isresumed |= (1 << index);
2672
2673 } else if (x & UHCI_PORTSC_SUSP) {
2674 status |= UPS_SUSPEND;
2675 }
2676 status |= UPS_PORT_POWER;
2677 if (sc->sc_isresumed & (1 << index))
2678 change |= UPS_C_SUSPEND;
2679 if (sc->sc_isreset)
2680 change |= UPS_C_PORT_RESET;
2681 USETW(sc->sc_hub_desc.ps.wPortStatus, status);
2682 USETW(sc->sc_hub_desc.ps.wPortChange, change);
2683 len = sizeof(sc->sc_hub_desc.ps);
2684 break;
2685 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2686 err = USB_ERR_IOERROR;
2687 goto done;
2688 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2689 break;
2690 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2691 if (index == 1)
2692 port = UHCI_PORTSC1;
2693 else if (index == 2)
2694 port = UHCI_PORTSC2;
2695 else {
2696 err = USB_ERR_IOERROR;
2697 goto done;
2698 }
2699 switch (value) {
2700 case UHF_PORT_ENABLE:
2701 x = URWMASK(UREAD2(sc, port));
2702 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
2703 break;
2704 case UHF_PORT_SUSPEND:
2705 x = URWMASK(UREAD2(sc, port));
2706 UWRITE2(sc, port, x | UHCI_PORTSC_SUSP);
2707 break;
2708 case UHF_PORT_RESET:
2709 err = uhci_portreset(sc, index);
2710 goto done;
2711 case UHF_PORT_POWER:
2712 /* pretend we turned on power */
2713 err = USB_ERR_NORMAL_COMPLETION;
2714 goto done;
2715 case UHF_C_PORT_CONNECTION:
2716 case UHF_C_PORT_ENABLE:
2717 case UHF_C_PORT_OVER_CURRENT:
2718 case UHF_PORT_CONNECTION:
2719 case UHF_PORT_OVER_CURRENT:
2720 case UHF_PORT_LOW_SPEED:
2721 case UHF_C_PORT_SUSPEND:
2722 case UHF_C_PORT_RESET:
2723 default:
2724 err = USB_ERR_IOERROR;
2725 goto done;
2726 }
2727 break;
2728 default:
2729 err = USB_ERR_IOERROR;
2730 goto done;
2731 }
2732done:
2733 *plength = len;
2734 *pptr = ptr;
2735 return (err);
2736}
2737
2738/*
2739 * This routine is executed periodically and simulates interrupts from
2740 * the root controller interrupt pipe for port status change:
2741 */
2742static void
2743uhci_root_intr(uhci_softc_t *sc)
2744{
2745 DPRINTFN(21, "\n");
2746
2747 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2748
2749 sc->sc_hub_idata[0] = 0;
2750
2751 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC |
2752 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) {
2753 sc->sc_hub_idata[0] |= 1 << 1;
2754 }
2755 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC |
2756 UHCI_PORTSC_OCIC | UHCI_PORTSC_RD)) {
2757 sc->sc_hub_idata[0] |= 1 << 2;
2758 }
2759
2760 /* restart timer */
2761 usb_callout_reset(&sc->sc_root_intr, hz,
2762 (void *)&uhci_root_intr, sc);
2763
2764 if (sc->sc_hub_idata[0] != 0) {
2765 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2766 sizeof(sc->sc_hub_idata));
2767 }
2768}
2769
2770static void
2771uhci_xfer_setup(struct usb_setup_params *parm)
2772{
2773 struct usb_page_search page_info;
2774 struct usb_page_cache *pc;
2775 uhci_softc_t *sc;
2776 struct usb_xfer *xfer;
2777 void *last_obj;
2778 uint32_t ntd;
2779 uint32_t nqh;
2780 uint32_t nfixup;
2781 uint32_t n;
2782 uint16_t align;
2783
2784 sc = UHCI_BUS2SC(parm->udev->bus);
2785 xfer = parm->curr_xfer;
2786
2787 parm->hc_max_packet_size = 0x500;
2788 parm->hc_max_packet_count = 1;
2789 parm->hc_max_frame_size = 0x500;
2790
2791 /*
2792 * compute ntd and nqh
2793 */
2794 if (parm->methods == &uhci_device_ctrl_methods) {
2795 xfer->flags_int.bdma_enable = 1;
2796 xfer->flags_int.bdma_no_post_sync = 1;
2797
2798 usbd_transfer_setup_sub(parm);
2799
2800 /* see EHCI HC driver for proof of "ntd" formula */
2801
2802 nqh = 1;
2803 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
2804 + (xfer->max_data_length / xfer->max_frame_size));
2805
2806 } else if (parm->methods == &uhci_device_bulk_methods) {
2807 xfer->flags_int.bdma_enable = 1;
2808 xfer->flags_int.bdma_no_post_sync = 1;
2809
2810 usbd_transfer_setup_sub(parm);
2811
2812 nqh = 1;
2813 ntd = ((2 * xfer->nframes)
2814 + (xfer->max_data_length / xfer->max_frame_size));
2815
2816 } else if (parm->methods == &uhci_device_intr_methods) {
2817 xfer->flags_int.bdma_enable = 1;
2818 xfer->flags_int.bdma_no_post_sync = 1;
2819
2820 usbd_transfer_setup_sub(parm);
2821
2822 nqh = 1;
2823 ntd = ((2 * xfer->nframes)
2824 + (xfer->max_data_length / xfer->max_frame_size));
2825
2826 } else if (parm->methods == &uhci_device_isoc_methods) {
2827 xfer->flags_int.bdma_enable = 1;
2828 xfer->flags_int.bdma_no_post_sync = 1;
2829
2830 usbd_transfer_setup_sub(parm);
2831
2832 nqh = 0;
2833 ntd = xfer->nframes;
2834
2835 } else {
2836 usbd_transfer_setup_sub(parm);
2837
2838 nqh = 0;
2839 ntd = 0;
2840 }
2841
2842 if (parm->err) {
2843 return;
2844 }
2845 /*
2846 * NOTE: the UHCI controller requires that
2847 * every packet must be contiguous on
2848 * the same USB memory page !
2849 */
2850 nfixup = (parm->bufsize / USB_PAGE_SIZE) + 1;
2851
2852 /*
2853 * Compute a suitable power of two alignment
2854 * for our "max_frame_size" fixup buffer(s):
2855 */
2856 align = xfer->max_frame_size;
2857 n = 0;
2858 while (align) {
2859 align >>= 1;
2860 n++;
2861 }
2862
2863 /* check for power of two */
2864 if (!(xfer->max_frame_size &
2865 (xfer->max_frame_size - 1))) {
2866 n--;
2867 }
2868 /*
2869 * We don't allow alignments of
2870 * less than 8 bytes:
2871 *
2872 * NOTE: Allocating using an alignment
2873 * of 1 byte has special meaning!
2874 */
2875 if (n < 3) {
2876 n = 3;
2877 }
2878 align = (1 << n);
2879
2880 if (usbd_transfer_setup_sub_malloc(
2881 parm, &pc, xfer->max_frame_size,
2882 align, nfixup)) {
2883 parm->err = USB_ERR_NOMEM;
2884 return;
2885 }
2886 xfer->buf_fixup = pc;
2887
2888alloc_dma_set:
2889
2890 if (parm->err) {
2891 return;
2892 }
2893 last_obj = NULL;
2894
2895 if (usbd_transfer_setup_sub_malloc(
2896 parm, &pc, sizeof(uhci_td_t),
2897 UHCI_TD_ALIGN, ntd)) {
2898 parm->err = USB_ERR_NOMEM;
2899 return;
2900 }
2901 if (parm->buf) {
2902 for (n = 0; n != ntd; n++) {
2903 uhci_td_t *td;
2904
2905 usbd_get_page(pc + n, 0, &page_info);
2906
2907 td = page_info.buffer;
2908
2909 /* init TD */
2910 if ((parm->methods == &uhci_device_bulk_methods) ||
2911 (parm->methods == &uhci_device_ctrl_methods) ||
2912 (parm->methods == &uhci_device_intr_methods)) {
2913 /* set depth first bit */
2914 td->td_self = htole32(page_info.physaddr |
2915 UHCI_PTR_TD | UHCI_PTR_VF);
2916 } else {
2917 td->td_self = htole32(page_info.physaddr |
2918 UHCI_PTR_TD);
2919 }
2920
2921 td->obj_next = last_obj;
2922 td->page_cache = pc + n;
2923
2924 last_obj = td;
2925
2926 usb_pc_cpu_flush(pc + n);
2927 }
2928 }
2929 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
2930
2931 last_obj = NULL;
2932
2933 if (usbd_transfer_setup_sub_malloc(
2934 parm, &pc, sizeof(uhci_qh_t),
2935 UHCI_QH_ALIGN, nqh)) {
2936 parm->err = USB_ERR_NOMEM;
2937 return;
2938 }
2939 if (parm->buf) {
2940 for (n = 0; n != nqh; n++) {
2941 uhci_qh_t *qh;
2942
2943 usbd_get_page(pc + n, 0, &page_info);
2944
2945 qh = page_info.buffer;
2946
2947 /* init QH */
2948 qh->qh_self = htole32(page_info.physaddr | UHCI_PTR_QH);
2949 qh->obj_next = last_obj;
2950 qh->page_cache = pc + n;
2951
2952 last_obj = qh;
2953
2954 usb_pc_cpu_flush(pc + n);
2955 }
2956 }
2957 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
2958
2959 if (!xfer->flags_int.curr_dma_set) {
2960 xfer->flags_int.curr_dma_set = 1;
2961 goto alloc_dma_set;
2962 }
2963}
2964
2965static void
2966uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
2967 struct usb_endpoint *ep)
2968{
2969 uhci_softc_t *sc = UHCI_BUS2SC(udev->bus);
2970
2971 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
2972 ep, udev->address,
2973 edesc->bEndpointAddress, udev->flags.usb_mode,
2974 sc->sc_addr);
2975
2976 if (udev->device_index != sc->sc_addr) {
2977 switch (edesc->bmAttributes & UE_XFERTYPE) {
2978 case UE_CONTROL:
2979 ep->methods = &uhci_device_ctrl_methods;
2980 break;
2981 case UE_INTERRUPT:
2982 ep->methods = &uhci_device_intr_methods;
2983 break;
2984 case UE_ISOCHRONOUS:
2985 if (udev->speed == USB_SPEED_FULL) {
2986 ep->methods = &uhci_device_isoc_methods;
2987 }
2988 break;
2989 case UE_BULK:
2990 ep->methods = &uhci_device_bulk_methods;
2991 break;
2992 default:
2993 /* do nothing */
2994 break;
2995 }
2996 }
2997}
2998
2999static void
3000uhci_xfer_unsetup(struct usb_xfer *xfer)
3001{
3002 return;
3003}
3004
3005static void
3006uhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
3007{
3008 /*
3009 * Wait until hardware has finished any possible use of the
3010 * transfer descriptor(s) and QH
3011 */
3012 *pus = (1125); /* microseconds */
3013}
3014
3015static void
3016uhci_device_resume(struct usb_device *udev)
3017{
3018 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus);
3019 struct usb_xfer *xfer;
3020 const struct usb_pipe_methods *methods;
3021 uhci_qh_t *qh;
3022
3023 DPRINTF("\n");
3024
3025 USB_BUS_LOCK(udev->bus);
3026
3027 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3028 if (xfer->xroot->udev == udev) {
3029 methods = xfer->endpoint->methods;
3030 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
3031
3032 if (methods == &uhci_device_bulk_methods) {
3033 UHCI_APPEND_QH(qh, sc->sc_bulk_p_last);
3034 uhci_add_loop(sc);
3035 xfer->flags_int.bandwidth_reclaimed = 1;
3036 }
3037 if (methods == &uhci_device_ctrl_methods) {
3038 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
3039 UHCI_APPEND_QH(qh, sc->sc_ls_ctl_p_last);
3040 } else {
3041 UHCI_APPEND_QH(qh, sc->sc_fs_ctl_p_last);
3042 }
3043 }
3044 if (methods == &uhci_device_intr_methods) {
3045 UHCI_APPEND_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
3046 }
3047 }
3048 }
3049
3050 USB_BUS_UNLOCK(udev->bus);
3051
3052 return;
3053}
3054
3055static void
3056uhci_device_suspend(struct usb_device *udev)
3057{
3058 struct uhci_softc *sc = UHCI_BUS2SC(udev->bus);
3059 struct usb_xfer *xfer;
3060 const struct usb_pipe_methods *methods;
3061 uhci_qh_t *qh;
3062
3063 DPRINTF("\n");
3064
3065 USB_BUS_LOCK(udev->bus);
3066
3067 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3068 if (xfer->xroot->udev == udev) {
3069 methods = xfer->endpoint->methods;
3070 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
3071
3072 if (xfer->flags_int.bandwidth_reclaimed) {
3073 xfer->flags_int.bandwidth_reclaimed = 0;
3074 uhci_rem_loop(sc);
3075 }
3076 if (methods == &uhci_device_bulk_methods) {
3077 UHCI_REMOVE_QH(qh, sc->sc_bulk_p_last);
3078 }
3079 if (methods == &uhci_device_ctrl_methods) {
3080 if (xfer->xroot->udev->speed == USB_SPEED_LOW) {
3081 UHCI_REMOVE_QH(qh, sc->sc_ls_ctl_p_last);
3082 } else {
3083 UHCI_REMOVE_QH(qh, sc->sc_fs_ctl_p_last);
3084 }
3085 }
3086 if (methods == &uhci_device_intr_methods) {
3087 UHCI_REMOVE_QH(qh, sc->sc_intr_p_last[xfer->qh_pos]);
3088 }
3089 }
3090 }
3091
3092 USB_BUS_UNLOCK(udev->bus);
3093
3094 return;
3095}
3096
3097static void
3098uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
3099{
3100 struct uhci_softc *sc = UHCI_BUS2SC(bus);
3101
3102 switch (state) {
3103 case USB_HW_POWER_SUSPEND:
3104 case USB_HW_POWER_SHUTDOWN:
3105 uhci_suspend(sc);
3106 break;
3107 case USB_HW_POWER_RESUME:
3108 uhci_resume(sc);
3109 break;
3110 default:
3111 break;
3112 }
3113}
3114
3115static void
3116uhci_set_hw_power(struct usb_bus *bus)
3117{
3118 struct uhci_softc *sc = UHCI_BUS2SC(bus);
3119 uint32_t flags;
3120
3121 DPRINTF("\n");
3122
3123 USB_BUS_LOCK(bus);
3124
3125 flags = bus->hw_power_state;
3126
3127 /*
3128 * WARNING: Some FULL speed USB devices require periodic SOF
3129 * messages! If any USB devices are connected through the
3130 * UHCI, power save will be disabled!
3131 */
3132 if (flags & (USB_HW_POWER_CONTROL |
3133 USB_HW_POWER_NON_ROOT_HUB |
3134 USB_HW_POWER_BULK |
3135 USB_HW_POWER_INTERRUPT |
3136 USB_HW_POWER_ISOC)) {
3137 DPRINTF("Some USB transfer is "
3138 "active on unit %u.\n",
3139 device_get_unit(sc->sc_bus.bdev));
3140 uhci_restart(sc);
3141 } else {
3142 DPRINTF("Power save on unit %u.\n",
3143 device_get_unit(sc->sc_bus.bdev));
3144 UHCICMD(sc, UHCI_CMD_MAXP);
3145 }
3146
3147 USB_BUS_UNLOCK(bus);
3148
3149 return;
3150}
3151
3152static const struct usb_bus_methods uhci_bus_methods =
3153{
3154 .endpoint_init = uhci_ep_init,
3155 .xfer_setup = uhci_xfer_setup,
3156 .xfer_unsetup = uhci_xfer_unsetup,
3157 .get_dma_delay = uhci_get_dma_delay,
3158 .device_resume = uhci_device_resume,
3159 .device_suspend = uhci_device_suspend,
3160 .set_hw_power = uhci_set_hw_power,
3161 .set_hw_power_sleep = uhci_set_hw_power_sleep,
3162 .roothub_exec = uhci_roothub_exec,
3163 .xfer_poll = uhci_do_poll,
3164};
debug
static int debug
Definition: cfumass.c:73
SYSCTL_NODE
static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW|CTLFLAG_MPSAFE, 0, "USB DWC OTG")
SYSCTL_INT
SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2/3 - ULPI/HSIC/INTERNAL/UTMI+")
len
uint16_t len
Definition: ehci.h:41
n
uint8_t n
Definition: if_run.c:612
error
struct @109 error
td_self
uint32_t td_self
Definition: ohci.h:28
td_next
volatile uint32_t td_next
Definition: ohci.h:19
value
uint32_t value
index
u_int index
state
int state
bus
u_int bus
uhci_config_desc
Definition: uhci.h:172
uhci_config_desc::confd
struct usb_config_descriptor confd
Definition: uhci.h:173
uhci_hw_softc::last_td_pg
struct usb_page last_td_pg
Definition: uhci.h:201
uhci_hw_softc::bulk_start_pg
struct usb_page bulk_start_pg
Definition: uhci.h:199
uhci_hw_softc::last_qh_pg
struct usb_page last_qh_pg
Definition: uhci.h:200
uhci_hw_softc::pframes_pg
struct usb_page pframes_pg
Definition: uhci.h:194
uhci_hw_softc::intr_start_pg
struct usb_page intr_start_pg[UHCI_IFRAMELIST_COUNT]
Definition: uhci.h:196
uhci_hw_softc::ls_ctl_start_pc
struct usb_page_cache ls_ctl_start_pc
Definition: uhci.h:188
uhci_hw_softc::last_qh_pc
struct usb_page_cache last_qh_pc
Definition: uhci.h:191
uhci_hw_softc::fs_ctl_start_pc
struct usb_page_cache fs_ctl_start_pc
Definition: uhci.h:189
uhci_hw_softc::ls_ctl_start_pg
struct usb_page ls_ctl_start_pg
Definition: uhci.h:197
uhci_hw_softc::isoc_start_pg
struct usb_page isoc_start_pg[UHCI_VFRAMELIST_COUNT]
Definition: uhci.h:195
uhci_hw_softc::intr_start_pc
struct usb_page_cache intr_start_pc[UHCI_IFRAMELIST_COUNT]
Definition: uhci.h:187
uhci_hw_softc::pframes_pc
struct usb_page_cache pframes_pc
Definition: uhci.h:185
uhci_hw_softc::bulk_start_pc
struct usb_page_cache bulk_start_pc
Definition: uhci.h:190
uhci_hw_softc::fs_ctl_start_pg
struct usb_page fs_ctl_start_pg
Definition: uhci.h:198
uhci_hw_softc::isoc_start_pc
struct usb_page_cache isoc_start_pc[UHCI_VFRAMELIST_COUNT]
Definition: uhci.h:186
uhci_hw_softc::last_td_pc
struct usb_page_cache last_td_pc
Definition: uhci.h:192
uhci_mem_layout
Definition: uhci.c:126
uhci_mem_layout::fix_pc
struct usb_page_cache * fix_pc
Definition: uhci.c:131
uhci_mem_layout::fix_res
struct usb_page_search fix_res
Definition: uhci.c:128
uhci_mem_layout::max_frame_size
uint16_t max_frame_size
Definition: uhci.c:135
uhci_mem_layout::buf_pc
struct usb_page_cache * buf_pc
Definition: uhci.c:130
uhci_mem_layout::buf_offset
uint32_t buf_offset
Definition: uhci.c:133
uhci_mem_layout::buf_res
struct usb_page_search buf_res
Definition: uhci.c:127
uhci_qh
Definition: uhci.h:138
uhci_qh::qh_h_next
volatile uint32_t qh_h_next
Definition: uhci.h:142
uhci_qh::qh_e_next
volatile uint32_t qh_e_next
Definition: uhci.h:143
uhci_qh::h_next
struct uhci_qh * h_next
Definition: uhci.h:147
uhci_qh::e_next
struct uhci_td * e_next
Definition: uhci.h:150
uhci_qh::qh_self
uint32_t qh_self
Definition: uhci.h:152
uhci_qh::obj_next
struct uhci_qh * obj_next
Definition: uhci.h:149
uhci_qh::h_prev
struct uhci_qh * h_prev
Definition: uhci.h:148
uhci_qh::page_cache
struct usb_page_cache * page_cache
Definition: uhci.h:151
uhci_softc
Definition: uhci.h:204
uhci_softc::sc_addr
uint8_t sc_addr
Definition: uhci.h:236
uhci_softc::sc_isreset
uint8_t sc_isreset
Definition: uhci.h:238
uhci_softc::sc_hub_desc
union uhci_hub_desc sc_hub_desc
Definition: uhci.h:207
uhci_softc::sc_fs_ctl_p_last
struct uhci_qh * sc_fs_ctl_p_last
Definition: uhci.h:218
uhci_softc::sc_bus
struct usb_bus sc_bus
Definition: uhci.h:206
uhci_softc::sc_last_qh_p
struct uhci_qh * sc_last_qh_p
Definition: uhci.h:222
uhci_softc::sc_ls_ctl_p_last
struct uhci_qh * sc_ls_ctl_p_last
Definition: uhci.h:216
uhci_softc::sc_isresumed
uint8_t sc_isresumed
Definition: uhci.h:239
uhci_softc::sc_isoc_p_last
struct uhci_td * sc_isoc_p_last[UHCI_VFRAMELIST_COUNT]
Definition: uhci.h:212
uhci_softc::sc_loops
uint32_t sc_loops
Definition: uhci.h:232
uhci_softc::sc_intr_stat
uint16_t sc_intr_stat[UHCI_IFRAMELIST_COUNT]
Definition: uhci.h:234
uhci_softc::sc_vendor
char sc_vendor[16]
Definition: uhci.h:242
uhci_softc::sc_intr_p_last
struct uhci_qh * sc_intr_p_last[UHCI_IFRAMELIST_COUNT]
Definition: uhci.h:214
uhci_softc::sc_bulk_p_last
struct uhci_qh * sc_bulk_p_last
Definition: uhci.h:220
uhci_softc::sc_reclaim_qh_p
struct uhci_qh * sc_reclaim_qh_p
Definition: uhci.h:221
uhci_softc::sc_last_td_p
struct uhci_td * sc_last_td_p
Definition: uhci.h:223
uhci_softc::sc_hw
struct uhci_hw_softc sc_hw
Definition: uhci.h:205
uhci_softc::sc_conf
uint8_t sc_conf
Definition: uhci.h:237
uhci_softc::sc_hub_idata
uint8_t sc_hub_idata[1]
Definition: uhci.h:240
uhci_softc::sc_root_intr
struct usb_callout sc_root_intr
Definition: uhci.h:208
uhci_std_temp
Definition: uhci.c:138
uhci_std_temp::td
uhci_td_t * td
Definition: uhci.c:140
uhci_std_temp::max_frame_size
uint16_t max_frame_size
Definition: uhci.c:146
uhci_std_temp::setup_alt_next
uint8_t setup_alt_next
Definition: uhci.c:148
uhci_std_temp::td_status
uint32_t td_status
Definition: uhci.c:143
uhci_std_temp::td_next
uhci_td_t * td_next
Definition: uhci.c:141
uhci_std_temp::len
uint32_t len
Definition: uhci.c:145
uhci_std_temp::last_frame
uint8_t last_frame
Definition: uhci.c:149
uhci_std_temp::td_token
uint32_t td_token
Definition: uhci.c:144
uhci_std_temp::ml
struct uhci_mem_layout ml
Definition: uhci.c:139
uhci_std_temp::average
uint32_t average
Definition: uhci.c:142
uhci_std_temp::shortpkt
uint8_t shortpkt
Definition: uhci.c:147
uhci_td
Definition: uhci.h:68
uhci_td::prev
struct uhci_td * prev
Definition: uhci.h:110
uhci_td::td_buffer
volatile uint32_t td_buffer
Definition: uhci.h:105
uhci_td::len
uint16_t len
Definition: uhci.h:115
uhci_td::td_self
uint32_t td_self
Definition: uhci.h:114
uhci_td::page_cache
struct usb_page_cache * page_cache
Definition: uhci.h:112
uhci_td::fix_pc
struct usb_page_cache * fix_pc
Definition: uhci.h:113
uhci_td::td_token
volatile uint32_t td_token
Definition: uhci.h:90
uhci_td::obj_next
struct uhci_td * obj_next
Definition: uhci.h:111
uhci_td::td_status
volatile uint32_t td_status
Definition: uhci.h:74
uhci_td::next
struct uhci_td * next
Definition: uhci.h:109
uhci_td::td_next
volatile uint32_t td_next
Definition: uhci.h:73
usb_bus_methods
Definition: usb_controller.h:56
usb_bus_methods::endpoint_init
void(* endpoint_init)(struct usb_device *, struct usb_endpoint_descriptor *, struct usb_endpoint *)
Definition: usb_controller.h:61
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Definition: usb.h:389
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Definition: usb.h:386
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Definition: usb_core.h:136
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Definition: usb_core.h:142
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Definition: usb_core.h:174
uhci_init
usb_error_t uhci_init(uhci_softc_t *sc)
Definition: uhci.c:450
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static void uhci_add_loop(uhci_softc_t *sc)
Definition: uhci.c:831
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static usb_error_t uhci_roothub_exec(struct usb_device *udev, struct usb_device_request *req, const void **pptr, uint16_t *plength)
Definition: uhci.c:2418
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static void uhci_device_ctrl_start(struct usb_xfer *xfer)
Definition: uhci.c:1945
UHCI_BUS2SC
#define UHCI_BUS2SC(bus)
Definition: uhci.c:85
UREAD4
#define UREAD4(sc, r)
Definition: uhci.c:117
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static const struct usb_bus_methods uhci_bus_methods
Definition: uhci.c:152
UREAD2
#define UREAD2(sc, r)
Definition: uhci.c:116
uhci_xfer_setup
static void uhci_xfer_setup(struct usb_setup_params *parm)
Definition: uhci.c:2771
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static void uhci_check_transfer_sub(struct usb_xfer *xfer)
Definition: uhci.c:1236
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static void uhci_device_bulk_start(struct usb_xfer *xfer)
Definition: uhci.c:1888
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#define UHCI_RESET_TIMEOUT
Definition: uhci.c:122
_uhci_remove_qh
static uhci_qh_t * _uhci_remove_qh(uhci_qh_t *sqh, uhci_qh_t *last)
Definition: uhci.c:973
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static void uhci_device_ctrl_open(struct usb_xfer *xfer)
Definition: uhci.c:1927
UHCI_REMOVE_QH
#define UHCI_REMOVE_QH(sqh, last)
Definition: uhci.c:971
uhci_xfer_unsetup
static void uhci_xfer_unsetup(struct usb_xfer *xfer)
Definition: uhci.c:3000
uhci_device_bulk_open
static void uhci_device_bulk_open(struct usb_xfer *xfer)
Definition: uhci.c:1870
uhci_setup_standard_chain
static uhci_td_t * uhci_setup_standard_chain(struct usb_xfer *xfer)
Definition: uhci.c:1643
uhci_start
static void uhci_start(uhci_softc_t *sc)
Definition: uhci.c:388
uhci_devd
static const struct usb_device_descriptor uhci_devd
Definition: uhci.c:2254
UHCI_REMOVE_TD
#define UHCI_REMOVE_TD(std, last)
Definition: uhci.c:951
UHCI_INTR_ENDPT
#define UHCI_INTR_ENDPT
Definition: uhci.c:124
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static const struct usb_hub_descriptor_min uhci_hubd_piix
Definition: uhci.c:2298
_uhci_append_td
static uhci_td_t * _uhci_append_td(uhci_td_t *std, uhci_td_t *last)
Definition: uhci.c:891
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static void uhci_transfer_intr_enqueue(struct usb_xfer *)
Definition: uhci.c:874
uhci_device_intr_close
static void uhci_device_intr_close(struct usb_xfer *xfer)
Definition: uhci.c:2022
_uhci_append_qh
static uhci_qh_t * _uhci_append_qh(uhci_qh_t *sqh, uhci_qh_t *last)
Definition: uhci.c:917
uhci_portreset
static usb_error_t uhci_portreset(uhci_softc_t *sc, uint16_t index)
Definition: uhci.c:2319
UHCI_APPEND_QH
#define UHCI_APPEND_QH(sqh, last)
Definition: uhci.c:915
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static void uhci_do_poll(struct usb_bus *)
Definition: uhci.c:1498
uhci_device_isoc_enter
static void uhci_device_isoc_enter(struct usb_xfer *xfer)
Definition: uhci.c:2109
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static void uhci_mem_layout_init(struct uhci_mem_layout *ml, struct usb_xfer *xfer)
Definition: uhci.c:204
C
#define C(x, y)
UWRITE2
#define UWRITE2(sc, r, x)
Definition: uhci.c:109
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static void uhci_device_isoc_close(struct usb_xfer *xfer)
Definition: uhci.c:2103
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#define UWRITE1(sc, r, x)
Definition: uhci.c:106
uhci_check_transfer
static uint8_t uhci_check_transfer(struct usb_xfer *)
Definition: uhci.c:1295
uhci_device_intr_open
static void uhci_device_intr_open(struct usb_xfer *xfer)
Definition: uhci.c:1989
UREAD1
#define UREAD1(sc, r)
Definition: uhci.c:115
uhci_interrupt_poll
static void uhci_interrupt_poll(uhci_softc_t *sc)
Definition: uhci.c:1390
UHCI_APPEND_TD
#define UHCI_APPEND_TD(std, last)
Definition: uhci.c:889
uhci_root_intr
static void uhci_root_intr(uhci_softc_t *sc)
Definition: uhci.c:2743
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void uhci_interrupt(uhci_softc_t *sc)
Definition: uhci.c:1414
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static void uhci_device_isoc_open(struct usb_xfer *xfer)
Definition: uhci.c:2076
uhci_device_intr_enter
static void uhci_device_intr_enter(struct usb_xfer *xfer)
Definition: uhci.c:2032
uhci_device_intr_methods
static const struct usb_pipe_methods uhci_device_intr_methods
Definition: uhci.c:155
uhci_isoc_done
static void uhci_isoc_done(uhci_softc_t *sc, struct usb_xfer *xfer)
Definition: uhci.c:1000
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static const struct usb_pipe_methods uhci_device_bulk_methods
Definition: uhci.c:153
uhci_device_suspend
static void uhci_device_suspend(struct usb_device *udev)
Definition: uhci.c:3056
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static void uhci_device_bulk_close(struct usb_xfer *xfer)
Definition: uhci.c:1876
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static void uhci_resume(uhci_softc_t *sc)
Definition: uhci.c:678
uhci_mem_layout_fixup
static void uhci_mem_layout_fixup(struct uhci_mem_layout *ml, struct uhci_td *td)
Definition: uhci.c:215
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static void uhci_timeout(void *)
Definition: uhci.c:1485
UWRITE4
#define UWRITE4(sc, r, x)
Definition: uhci.c:112
uhci_device_resume
static void uhci_device_resume(struct usb_device *udev)
Definition: uhci.c:3016
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static const struct usb_pipe_methods uhci_device_ctrl_methods
Definition: uhci.c:154
uhci_device_ctrl_enter
static void uhci_device_ctrl_enter(struct usb_xfer *xfer)
Definition: uhci.c:1939
uhci_device_ctrl_close
static void uhci_device_ctrl_close(struct usb_xfer *xfer)
Definition: uhci.c:1933
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static const struct uhci_config_desc uhci_confd
Definition: uhci.c:2268
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void uhci_reset(uhci_softc_t *sc)
Definition: uhci.c:314
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static void uhci_device_intr_start(struct usb_xfer *xfer)
Definition: uhci.c:2038
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static void uhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, struct usb_endpoint *ep)
Definition: uhci.c:2966
uhci_device_isoc_start
static void uhci_device_isoc_start(struct usb_xfer *xfer)
Definition: uhci.c:2233
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static void uhci_device_bulk_enter(struct usb_xfer *xfer)
Definition: uhci.c:1882
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static usb_error_t uhci_non_isoc_done_sub(struct usb_xfer *xfer)
Definition: uhci.c:1066
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static void uhci_rem_loop(uhci_softc_t *sc)
Definition: uhci.c:855
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static uhci_td_t * _uhci_remove_td(uhci_td_t *std, uhci_td_t *last)
Definition: uhci.c:953
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static void uhci_device_done(struct usb_xfer *, usb_error_t)
Definition: uhci.c:1818
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Definition: uhci.c:656
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Definition: uhci.c:277
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Definition: uhci.c:167
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static void uhci_set_hw_power(struct usb_bus *bus)
Definition: uhci.c:3116
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Definition: uhci.c:3006
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static struct uhci_qh * uhci_init_qh(struct usb_page_cache *pc)
Definition: uhci.c:412
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static void uhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
Definition: uhci.c:3098
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static struct uhci_td * uhci_init_td(struct usb_page_cache *pc)
Definition: uhci.c:431
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static void uhci_non_isoc_done(struct usb_xfer *xfer)
Definition: uhci.c:1181
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static const struct usb_pipe_methods uhci_device_isoc_methods
Definition: uhci.c:156
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Definition: uhci.c:1508
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Definition: uhci.c:119
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Definition: uhci.h:25
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Definition: uhci.h:16
UHCI_TD_ACTIVE
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Definition: uhci.h:14
UHCI_QH_ALIGN
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Definition: uhci.h:44
UHCI_TD_BABBLE
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Definition: uhci.h:11
UHCI_TD_STALLED
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Definition: uhci.h:13
UHCI_TD_SET_MAXLEN
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Definition: uhci.h:33
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Definition: uhci.h:54
UHCI_TD_IOC
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Definition: uhci.h:15
UHCI_TD_SET_ERRCNT
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Definition: uhci.h:19
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Definition: uhci.h:17
UHCI_PTR_VF
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Definition: uhci.h:56
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#define UHCI_FRAMELIST_COUNT
Definition: uhci.h:39
UHCI_TD_GET_PID
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Definition: uhci.h:26
UHCI_TD_PID_OUT
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Definition: uhci.h:24
UHCI_TD_GET_ACTLEN
#define UHCI_TD_GET_ACTLEN(s)
Definition: uhci.h:6
qh_e_next
volatile uint32_t qh_e_next
Definition: uhci.h:4
UHCI_MAX_DEVICES
#define UHCI_MAX_DEVICES
Definition: uhci.h:37
UHCI_IFRAMELIST_COUNT
#define UHCI_IFRAMELIST_COUNT
Definition: uhci.h:160
UHCI_TD_GET_ENDPT
#define UHCI_TD_GET_ENDPT(s)
Definition: uhci.h:30
td_status
volatile uint32_t td_status
Definition: uhci.h:5
UHCI_TD_ERROR
#define UHCI_TD_ERROR
Definition: uhci.h:120
UHCI_TD_SET_ENDPT
#define UHCI_TD_SET_ENDPT(e)
Definition: uhci.h:29
qh_h_next
volatile uint32_t qh_h_next
Definition: uhci.h:3
UHCI_TD_NAK
#define UHCI_TD_NAK
Definition: uhci.h:10
UHCI_PTR_QH
#define UHCI_PTR_QH
Definition: uhci.h:55
UHCI_TD_SET_DT
#define UHCI_TD_SET_DT(t)
Definition: uhci.h:31
UHCI_FRAMELIST_ALIGN
#define UHCI_FRAMELIST_ALIGN
Definition: uhci.h:40
UHCI_TD_IN
#define UHCI_TD_IN(len, endp, dev, dt)
Definition: uhci.h:133
UHCI_PTR_T
#define UHCI_PTR_T
Definition: uhci.h:53
UHCI_TD_BITSTUFF
#define UHCI_TD_BITSTUFF
Definition: uhci.h:8
UHCI_TD_SPD
#define UHCI_TD_SPD
Definition: uhci.h:20
UHCI_TD_ZERO_ACTLEN
#define UHCI_TD_ZERO_ACTLEN(t)
Definition: uhci.h:7
UHCI_TD_GET_MAXLEN
#define UHCI_TD_GET_MAXLEN(s)
Definition: uhci.h:34
UHCI_TD_SET_DEVADDR
#define UHCI_TD_SET_DEVADDR(a)
Definition: uhci.h:27
UHCI_VFRAMELIST_COUNT
#define UHCI_VFRAMELIST_COUNT
Definition: uhci.h:159
UHCI_TD_CRCTO
#define UHCI_TD_CRCTO
Definition: uhci.h:9
UHCI_TD_MAXLEN_MASK
#define UHCI_TD_MAXLEN_MASK
Definition: uhci.h:35
UHCI_TD_GET_DT
#define UHCI_TD_GET_DT(s)
Definition: uhci.h:32
UHCI_TD_DBUFFER
#define UHCI_TD_DBUFFER
Definition: uhci.h:12
td_token
volatile uint32_t td_token
Definition: uhci.h:21
UHCI_TD_ALIGN
#define UHCI_TD_ALIGN
Definition: uhci.h:43
UHCI_TD_GET_ERRCNT
#define UHCI_TD_GET_ERRCNT(s)
Definition: uhci.h:18
UHCI_TD_OUT
#define UHCI_TD_OUT(len, endp, dev, dt)
Definition: uhci.h:128
UHCI_TD_GET_DEVADDR
#define UHCI_TD_GET_DEVADDR(s)
Definition: uhci.h:28
UHCI_TD_PID_IN
#define UHCI_TD_PID_IN
Definition: uhci.h:23
UHCI_TD_PID
#define UHCI_TD_PID
Definition: uhci.h:22
UHCI_CMD_EGSM
#define UHCI_CMD_EGSM
Definition: uhcireg.h:55
UHCI_CMD
#define UHCI_CMD
Definition: uhcireg.h:51
UHCI_PORTSC_LS_SHIFT
#define UHCI_PORTSC_LS_SHIFT
Definition: uhcireg.h:85
UHCI_PORTSC1
#define UHCI_PORTSC1
Definition: uhcireg.h:78
UHCI_PORTSC_CCS
#define UHCI_PORTSC_CCS
Definition: uhcireg.h:80
UHCI_INTR_IOCE
#define UHCI_INTR_IOCE
Definition: uhcireg.h:71
UHCI_STS_USBEI
#define UHCI_STS_USBEI
Definition: uhcireg.h:62
UHCI_STS_HCPE
#define UHCI_STS_HCPE
Definition: uhcireg.h:65
UHCI_FLBASEADDR
#define UHCI_FLBASEADDR
Definition: uhcireg.h:75
UHCI_STS_RD
#define UHCI_STS_RD
Definition: uhcireg.h:63
UHCI_PORTSC_POEDC
#define UHCI_PORTSC_POEDC
Definition: uhcireg.h:83
UHCI_INTR_SPIE
#define UHCI_INTR_SPIE
Definition: uhcireg.h:72
UHCI_INTR_TOCRCIE
#define UHCI_INTR_TOCRCIE
Definition: uhcireg.h:69
UHCI_SOF
#define UHCI_SOF
Definition: uhcireg.h:76
UHCI_PORTSC_LS
#define UHCI_PORTSC_LS
Definition: uhcireg.h:84
UHCI_PORTSC_PR
#define UHCI_PORTSC_PR
Definition: uhcireg.h:88
UHCI_PORTSC2
#define UHCI_PORTSC2
Definition: uhcireg.h:79
UHCI_STS_HCH
#define UHCI_STS_HCH
Definition: uhcireg.h:66
UHCI_PORTSC_OCI
#define UHCI_PORTSC_OCI
Definition: uhcireg.h:89
UHCI_CMD_FGR
#define UHCI_CMD_FGR
Definition: uhcireg.h:56
UHCI_INTR_RIE
#define UHCI_INTR_RIE
Definition: uhcireg.h:70
UHCI_PORTSC_LSDA
#define UHCI_PORTSC_LSDA
Definition: uhcireg.h:87
UHCI_PORTSC_RD
#define UHCI_PORTSC_RD
Definition: uhcireg.h:86
UHCI_STS_USBINT
#define UHCI_STS_USBINT
Definition: uhcireg.h:61
UHCI_STS_ALLINTRS
#define UHCI_STS_ALLINTRS
Definition: uhcireg.h:67
UHCI_FRNUM
#define UHCI_FRNUM
Definition: uhcireg.h:73
UHCI_CMD_RS
#define UHCI_CMD_RS
Definition: uhcireg.h:52
UHCI_PORTSC_SUSP
#define UHCI_PORTSC_SUSP
Definition: uhcireg.h:91
UHCI_STS_HSE
#define UHCI_STS_HSE
Definition: uhcireg.h:64
UHCI_CMD_MAXP
#define UHCI_CMD_MAXP
Definition: uhcireg.h:59
UHCI_PORTSC_OCIC
#define UHCI_PORTSC_OCIC
Definition: uhcireg.h:90
URWMASK
#define URWMASK(x)
Definition: uhcireg.h:93
UHCI_CMD_HCRESET
#define UHCI_CMD_HCRESET
Definition: uhcireg.h:53
UHCI_CMD_GRESET
#define UHCI_CMD_GRESET
Definition: uhcireg.h:54
UHCI_STS
#define UHCI_STS
Definition: uhcireg.h:60
UHCI_PORTSC_CSC
#define UHCI_PORTSC_CSC
Definition: uhcireg.h:81
UHCI_INTR
#define UHCI_INTR
Definition: uhcireg.h:68
UHCI_PORTSC_PE
#define UHCI_PORTSC_PE
Definition: uhcireg.h:82
DPRINTF
#define DPRINTF(...)
Definition: umass.c:179
uhci_hub_desc::temp
uint8_t temp[128]
Definition: uhci.h:181
uhci_hub_desc::ps
struct usb_port_status ps
Definition: uhci.h:180
uhci_hub_desc::stat
struct usb_status stat
Definition: uhci.h:179
UE_INTERRUPT
#define UE_INTERRUPT
Definition: usb.h:544
UR_SET_CONFIG
#define UR_SET_CONFIG
Definition: usb.h:219
UPS_C_PORT_RESET
#define UPS_C_PORT_RESET
Definition: usb.h:740
UDSUBCLASS_HUB
#define UDSUBCLASS_HUB
Definition: usb.h:374
UHF_PORT_OVER_CURRENT
#define UHF_PORT_OVER_CURRENT
Definition: usb.h:251
UC_SELF_POWERED
#define UC_SELF_POWERED
Definition: usb.h:395
UT_WRITE_INTERFACE
#define UT_WRITE_INTERFACE
Definition: usb.h:170
UR_SET_DESCRIPTOR
#define UR_SET_DESCRIPTOR
Definition: usb.h:217
UE_BULK
#define UE_BULK
Definition: usb.h:543
UHF_PORT_POWER
#define UHF_PORT_POWER
Definition: usb.h:254
UR_GET_CONFIG
#define UR_GET_CONFIG
Definition: usb.h:218
UT_WRITE_CLASS_OTHER
#define UT_WRITE_CLASS_OTHER
Definition: usb.h:178
UISUBCLASS_HUB
#define UISUBCLASS_HUB
Definition: usb.h:480
UT_WRITE_CLASS_DEVICE
#define UT_WRITE_CLASS_DEVICE
Definition: usb.h:176
UR_SET_ADDRESS
#define UR_SET_ADDRESS
Definition: usb.h:193
UPS_C_PORT_ENABLED
#define UPS_C_PORT_ENABLED
Definition: usb.h:737
UT_WRITE_DEVICE
#define UT_WRITE_DEVICE
Definition: usb.h:169
UDESC_CONFIG
#define UDESC_CONFIG
Definition: usb.h:196
UR_GET_INTERFACE
#define UR_GET_INTERFACE
Definition: usb.h:220
UPS_C_OVERCURRENT_INDICATOR
#define UPS_C_OVERCURRENT_INDICATOR
Definition: usb.h:739
UDCLASS_HUB
#define UDCLASS_HUB
Definition: usb.h:373
UHF_PORT_LOW_SPEED
#define UHF_PORT_LOW_SPEED
Definition: usb.h:255
UR_GET_STATUS
#define UR_GET_STATUS
Definition: usb.h:190
UHF_C_PORT_SUSPEND
#define UHF_C_PORT_SUSPEND
Definition: usb.h:259
UR_CLEAR_FEATURE
#define UR_CLEAR_FEATURE
Definition: usb.h:191
UDESC_ENDPOINT
#define UDESC_ENDPOINT
Definition: usb.h:200
UPS_LOW_SPEED
#define UPS_LOW_SPEED
Definition: usb.h:729
UE_GET_ADDR
#define UE_GET_ADDR(a)
Definition: usb.h:538
UDS_SELF_POWERED
#define UDS_SELF_POWERED
Definition: usb.h:688
UPS_PORT_POWER
#define UPS_PORT_POWER
Definition: usb.h:727
USB_BUS_RESET_DELAY
#define USB_BUS_RESET_DELAY
Definition: usb.h:129
UDESC_HUB
#define UDESC_HUB
Definition: usb.h:214
UDESC_STRING
#define UDESC_STRING
Definition: usb.h:197
UHF_C_PORT_OVER_CURRENT
#define UHF_C_PORT_OVER_CURRENT
Definition: usb.h:260
UHF_PORT_SUSPEND
#define UHF_PORT_SUSPEND
Definition: usb.h:250
UE_DIR_IN
#define UE_DIR_IN
Definition: usb.h:531
UR_SYNCH_FRAME
#define UR_SYNCH_FRAME
Definition: usb.h:222
UT_READ_DEVICE
#define UT_READ_DEVICE
Definition: usb.h:166
UR_GET_BUS_STATE
#define UR_GET_BUS_STATE
Definition: usb.h:227
UE_XFERTYPE
#define UE_XFERTYPE
Definition: usb.h:540
UHF_PORT_ENABLE
#define UHF_PORT_ENABLE
Definition: usb.h:249
UICLASS_HUB
#define UICLASS_HUB
Definition: usb.h:479
UDESC_DEVICE
#define UDESC_DEVICE
Definition: usb.h:195
UDESC_INTERFACE
#define UDESC_INTERFACE
Definition: usb.h:199
USB_SPEED_LOW
@ USB_SPEED_LOW
Definition: usb.h:753
USB_SPEED_FULL
@ USB_SPEED_FULL
Definition: usb.h:754
UE_DIR_OUT
#define UE_DIR_OUT
Definition: usb.h:532
UE_GET_DIR
#define UE_GET_DIR(a)
Definition: usb.h:529
UHD_OC_INDIVIDUAL
#define UHD_OC_INDIVIDUAL
Definition: usb.h:614
UPS_PORT_ENABLED
#define UPS_PORT_ENABLED
Definition: usb.h:706
UT_WRITE_ENDPOINT
#define UT_WRITE_ENDPOINT
Definition: usb.h:171
UT_READ_CLASS_DEVICE
#define UT_READ_CLASS_DEVICE
Definition: usb.h:172
UHF_PORT_RESET
#define UHF_PORT_RESET
Definition: usb.h:252
UDPROTO_FSHUB
#define UDPROTO_FSHUB
Definition: usb.h:375
UR_SET_INTERFACE
#define UR_SET_INTERFACE
Definition: usb.h:221
UT_READ_CLASS_OTHER
#define UT_READ_CLASS_OTHER
Definition: usb.h:174
UE_CONTROL
#define UE_CONTROL
Definition: usb.h:541
UT_READ_ENDPOINT
#define UT_READ_ENDPOINT
Definition: usb.h:168
UHF_C_PORT_RESET
#define UHF_C_PORT_RESET
Definition: usb.h:261
UPS_C_SUSPEND
#define UPS_C_SUSPEND
Definition: usb.h:738
UHD_PWR_NO_SWITCH
#define UHD_PWR_NO_SWITCH
Definition: usb.h:610
UPS_C_CONNECT_STATUS
#define UPS_C_CONNECT_STATUS
Definition: usb.h:736
UPS_CURRENT_CONNECT_STATUS
#define UPS_CURRENT_CONNECT_STATUS
Definition: usb.h:705
UHF_PORT_CONNECTION
#define UHF_PORT_CONNECTION
Definition: usb.h:248
UE_ISOCHRONOUS
#define UE_ISOCHRONOUS
Definition: usb.h:542
UHF_C_PORT_ENABLE
#define UHF_C_PORT_ENABLE
Definition: usb.h:258
UIPROTO_FSHUB
#define UIPROTO_FSHUB
Definition: usb.h:481
UR_SET_FEATURE
#define UR_SET_FEATURE
Definition: usb.h:192
UPS_OVERCURRENT_INDICATOR
#define UPS_OVERCURRENT_INDICATOR
Definition: usb.h:708
UPS_SUSPEND
#define UPS_SUSPEND
Definition: usb.h:707
UT_READ_INTERFACE
#define UT_READ_INTERFACE
Definition: usb.h:167
UR_GET_DESCRIPTOR
#define UR_GET_DESCRIPTOR
Definition: usb.h:194
UHF_C_PORT_CONNECTION
#define UHF_C_PORT_CONNECTION
Definition: usb.h:257
usb_bus.h
usbd_get_page
void usbd_get_page(struct usb_page_cache *pc, usb_frlength_t offset, struct usb_page_search *res)
Definition: usb_busdma.c:86
usbd_copy_in
void usbd_copy_in(struct usb_page_cache *cache, usb_frlength_t offset, const void *ptr, usb_frlength_t len)
Definition: usb_busdma.c:166
usbd_copy_out
void usbd_copy_out(struct usb_page_cache *cache, usb_frlength_t offset, void *ptr, usb_frlength_t len)
Definition: usb_busdma.c:283
usb_busdma.h
usb_pc_cpu_invalidate
void usb_pc_cpu_invalidate(struct usb_page_cache *pc)
usb_pc_cpu_flush
void usb_pc_cpu_flush(struct usb_page_cache *pc)
usb_bdma_post_sync
void usb_bdma_post_sync(struct usb_xfer *xfer)
USB_PAGE_SIZE
#define USB_PAGE_SIZE
Definition: usb_busdma.h:41
usb_controller.h
USB_HW_POWER_RESUME
#define USB_HW_POWER_RESUME
Definition: usb_controller.h:102
usb_bus_mem_flush_all
void usb_bus_mem_flush_all(struct usb_bus *bus, usb_bus_mem_cb_t *cb)
USB_HW_POWER_BULK
#define USB_HW_POWER_BULK
Definition: usb_controller.h:79
USB_HW_POWER_NON_ROOT_HUB
#define USB_HW_POWER_NON_ROOT_HUB
Definition: usb_controller.h:94
USB_HW_POWER_CONTROL
#define USB_HW_POWER_CONTROL
Definition: usb_controller.h:74
USB_HW_POWER_SUSPEND
#define USB_HW_POWER_SUSPEND
Definition: usb_controller.h:98
USB_HW_POWER_SHUTDOWN
#define USB_HW_POWER_SHUTDOWN
Definition: usb_controller.h:106
usb_bus_mem_sub_cb_t
void() usb_bus_mem_sub_cb_t(struct usb_bus *bus, struct usb_page_cache *pc, struct usb_page *pg, usb_size_t size, usb_size_t align)
Definition: usb_controller.h:49
USB_HW_POWER_ISOC
#define USB_HW_POWER_ISOC
Definition: usb_controller.h:89
USB_HW_POWER_INTERRUPT
#define USB_HW_POWER_INTERRUPT
Definition: usb_controller.h:84
usb_core.h
USB_BUS_LOCK
#define USB_BUS_LOCK(_b)
Definition: usb_core.h:45
USB_BUS_UNLOCK
#define USB_BUS_UNLOCK(_b)
Definition: usb_core.h:46
USB_BUS_LOCK_ASSERT
#define USB_BUS_LOCK_ASSERT(_b, _t)
Definition: usb_core.h:47
usb_debug.h
usb_port_reset_delay
#define usb_port_reset_delay
Definition: usb_debug.h:76
usb_port_root_reset_delay
#define usb_port_root_reset_delay
Definition: usb_debug.h:77
usbd_get_speed
enum usb_dev_speed usbd_get_speed(struct usb_device *udev)
Definition: usb_device.c:2589
usb_device.h
USETW
#define USETW(w, v)
Definition: usb_endian.h:77
UGETW
#define UGETW(w)
Definition: usb_endian.h:53
uhub_root_intr
void uhub_root_intr(struct usb_bus *bus, const uint8_t *ptr, uint8_t len)
Definition: usb_hub.c:960
usb_hub.h
pptr
void ** pptr
Definition: usb_if.m:52
plen
uint16_t * plen
Definition: usb_if.m:53
offset
uint16_t offset
Definition: usb_if.m:54
req
const void * req
Definition: usb_if.m:51
usb_process.h
usbd_transfer_setup_sub
void usbd_transfer_setup_sub(struct usb_setup_params *parm)
Definition: usb_transfer.c:457
usbd_transfer_done
void usbd_transfer_done(struct usb_xfer *xfer, usb_error_t error)
Definition: usb_transfer.c:2593
usbd_xfer_set_frame_len
void usbd_xfer_set_frame_len(struct usb_xfer *xfer, usb_frcount_t frindex, usb_frlength_t len)
Definition: usb_transfer.c:2316
usbd_transfer_enqueue
void usbd_transfer_enqueue(struct usb_xfer_queue *pq, struct usb_xfer *xfer)
Definition: usb_transfer.c:2569
usbd_xfer_get_isochronous_start_frame
uint8_t usbd_xfer_get_isochronous_start_frame(struct usb_xfer *xfer, uint32_t frame_curr, uint32_t frame_min, uint32_t frame_ms, uint32_t frame_mask, uint32_t *p_frame_start)
Definition: usb_transfer.c:3692
usbd_transfer_timeout_ms
void usbd_transfer_timeout_ms(struct usb_xfer *xfer, void(*cb)(void *arg), usb_timeout_t ms)
Definition: usb_transfer.c:2934
usb_transfer.h
usbd_transfer_setup_sub_malloc
uint8_t usbd_transfer_setup_sub_malloc(struct usb_setup_params *parm, struct usb_page_cache **ppc, usb_size_t size, usb_size_t align, usb_size_t count)
usb_pause_mtx
void usb_pause_mtx(struct mtx *mtx, int timo)
Definition: usb_util.c:135
usb_make_str_desc
uint8_t usb_make_str_desc(void *ptr, uint16_t max_len, const char *s)
Definition: usb_util.c:193
usb_util.h
usb_callout_init_mtx
#define usb_callout_init_mtx(c, m, f)
Definition: usbdi.h:480
usb_callout_reset
#define usb_callout_reset(c,...)
Definition: usbdi.h:481
usb_error_t
usb_error_t
Definition: usbdi.h:45
USB_ERR_NORMAL_COMPLETION
@ USB_ERR_NORMAL_COMPLETION
Definition: usbdi.h:46
USB_ERR_STALLED
@ USB_ERR_STALLED
Definition: usbdi.h:68
USB_ERR_IOERROR
@ USB_ERR_IOERROR
Definition: usbdi.h:64
USB_ERR_NOMEM
@ USB_ERR_NOMEM
Definition: usbdi.h:50
USB_ERR_CANCELLED
@ USB_ERR_CANCELLED
Definition: usbdi.h:51
USB_ERR_TIMEOUT
@ USB_ERR_TIMEOUT
Definition: usbdi.h:66
usb_callout_drain
#define usb_callout_drain(c)
Definition: usbdi.h:497
USB_MS_TO_TICKS
#define USB_MS_TO_TICKS(ms)
Definition: usbdi.h:120
status
uint8_t status
Definition: xhci.h:14