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Macros
#define	TR_REG_CIR 0xa0

#define	TR_CIR_MASK 0x0000003f

#define	TR_CIR_ADDRENA 0x00001000

#define	TR_CIR_MIDENA 0x00002000

#define	TR_REG_MISCINT 0xb0

#define	TR_INT_ADDR 0x00000020

#define	TR_INT_SB 0x00000004

#define	TR_REG_DMAR0 0x00

#define	TR_REG_DMAR4 0x04

#define	TR_REG_DMAR11 0x0b

#define	TR_REG_DMAR15 0x0f

#define	TR_REG_SBR4 0x14

#define	TR_REG_SBR5 0x15

#define	TR_SB_INTSTATUS 0x82

#define	TR_REG_SBR9 0x1e

#define	TR_REG_SBR10 0x1f

#define	TR_REG_SBBL 0xc0

#define	TR_REG_SBCTRL 0xc4

#define	TR_REG_SBDELTA 0xac

#define	TR_CDC_DATA 16

#define	TDX_REG_CODECWR 0x40

#define	TDX_REG_CODECRD 0x44

#define	TDX_CDC_RWSTAT 0x00008000

#define	TDX_REG_CODECST 0x48

#define	TDX_CDC_SBCTRL 0x40

#define	TDX_CDC_ACTIVE 0x20

#define	TDX_CDC_READY 0x10

#define	TDX_CDC_ADCON 0x08

#define	TDX_CDC_DACON 0x02

#define	TDX_CDC_RESET 0x01

#define	TDX_CDC_ON (TDX_CDC_ADCON\|TDX_CDC_DACON)

#define	SPA_REG_CODECRD 0x44

#define	SPA_REG_CODECWR 0x40

#define	SPA_REG_CODECST 0x48

#define	SPA_RST_OFF 0x0f0000

#define	SPA_REG_GPIO 0x48

#define	SPA_CDC_RWSTAT 0x00008000

#define	TNX_REG_CODECWR 0x44

#define	TNX_REG_CODEC1RD 0x48

#define	TNX_REG_CODEC2RD 0x4c

#define	TNX_CDC_RWSTAT 0x00000c00

#define	TNX_CDC_SEC 0x00000100

#define	TNX_REG_CODECST 0x40

#define	TNX_CDC_READY2 0x40

#define	TNX_CDC_ADC2ON 0x20

#define	TNX_CDC_DAC2ON 0x10

#define	TNX_CDC_READY1 0x08

#define	TNX_CDC_ADC1ON 0x04

#define	TNX_CDC_DAC1ON 0x02

#define	TNX_CDC_RESET 0x01

#define	TNX_CDC_ON (TNX_CDC_ADC1ON\|TNX_CDC_DAC1ON)

#define	TR_REG_STARTA 0x80

#define	TR_REG_STOPA 0x84

#define	TR_REG_CSPF_A 0x90

#define	TR_REG_ADDRINTA 0x98

#define	TR_REG_INTENA 0xa4

#define	TR_REG_STARTB 0xb4

#define	TR_REG_STOPB 0xb8

#define	TR_REG_CSPF_B 0xbc

#define	TR_REG_ADDRINTB 0xd8

#define	TR_REG_INTENB 0xdc

#define	TR_REG_CHNBASE 0xe0

#define	TR_CHN_REGS 5

Macro Definition Documentation

◆ SPA_CDC_RWSTAT

#define SPA_CDC_RWSTAT 0x00008000

Definition at line 73 of file t4dwave.h.

◆ SPA_REG_CODECRD

#define SPA_REG_CODECRD 0x44

Definition at line 68 of file t4dwave.h.

◆ SPA_REG_CODECST

#define SPA_REG_CODECST 0x48

Definition at line 70 of file t4dwave.h.

◆ SPA_REG_CODECWR

#define SPA_REG_CODECWR 0x40

Definition at line 69 of file t4dwave.h.

◆ SPA_REG_GPIO

#define SPA_REG_GPIO 0x48

Definition at line 72 of file t4dwave.h.

◆ SPA_RST_OFF

#define SPA_RST_OFF 0x0f0000

Definition at line 71 of file t4dwave.h.

◆ TDX_CDC_ACTIVE

#define TDX_CDC_ACTIVE 0x20

Definition at line 61 of file t4dwave.h.

◆ TDX_CDC_ADCON

#define TDX_CDC_ADCON 0x08

Definition at line 63 of file t4dwave.h.

◆ TDX_CDC_DACON

#define TDX_CDC_DACON 0x02

Definition at line 64 of file t4dwave.h.

◆ TDX_CDC_ON

#define TDX_CDC_ON (TDX_CDC_ADCON|TDX_CDC_DACON)

Definition at line 66 of file t4dwave.h.

◆ TDX_CDC_READY

#define TDX_CDC_READY 0x10

Definition at line 62 of file t4dwave.h.

◆ TDX_CDC_RESET

#define TDX_CDC_RESET 0x01

Definition at line 65 of file t4dwave.h.

◆ TDX_CDC_RWSTAT

#define TDX_CDC_RWSTAT 0x00008000

Definition at line 58 of file t4dwave.h.

◆ TDX_CDC_SBCTRL

#define TDX_CDC_SBCTRL 0x40

Definition at line 60 of file t4dwave.h.

◆ TDX_REG_CODECRD

#define TDX_REG_CODECRD 0x44

Definition at line 57 of file t4dwave.h.

◆ TDX_REG_CODECST

#define TDX_REG_CODECST 0x48

Definition at line 59 of file t4dwave.h.

◆ TDX_REG_CODECWR

#define TDX_REG_CODECWR 0x40

Definition at line 56 of file t4dwave.h.

◆ TNX_CDC_ADC1ON

#define TNX_CDC_ADC1ON 0x04

Definition at line 85 of file t4dwave.h.

◆ TNX_CDC_ADC2ON

#define TNX_CDC_ADC2ON 0x20

Definition at line 82 of file t4dwave.h.

◆ TNX_CDC_DAC1ON

#define TNX_CDC_DAC1ON 0x02

Definition at line 86 of file t4dwave.h.

◆ TNX_CDC_DAC2ON

#define TNX_CDC_DAC2ON 0x10

Definition at line 83 of file t4dwave.h.

◆ TNX_CDC_ON

#define TNX_CDC_ON (TNX_CDC_ADC1ON|TNX_CDC_DAC1ON)

Definition at line 88 of file t4dwave.h.

◆ TNX_CDC_READY1

#define TNX_CDC_READY1 0x08

Definition at line 84 of file t4dwave.h.

◆ TNX_CDC_READY2

#define TNX_CDC_READY2 0x40

Definition at line 81 of file t4dwave.h.

◆ TNX_CDC_RESET

#define TNX_CDC_RESET 0x01

Definition at line 87 of file t4dwave.h.

◆ TNX_CDC_RWSTAT

#define TNX_CDC_RWSTAT 0x00000c00

Definition at line 78 of file t4dwave.h.

◆ TNX_CDC_SEC

#define TNX_CDC_SEC 0x00000100

Definition at line 79 of file t4dwave.h.

◆ TNX_REG_CODEC1RD

#define TNX_REG_CODEC1RD 0x48

Definition at line 76 of file t4dwave.h.

◆ TNX_REG_CODEC2RD

#define TNX_REG_CODEC2RD 0x4c

Definition at line 77 of file t4dwave.h.

◆ TNX_REG_CODECST

#define TNX_REG_CODECST 0x40

Definition at line 80 of file t4dwave.h.

◆ TNX_REG_CODECWR

#define TNX_REG_CODECWR 0x44

Definition at line 75 of file t4dwave.h.

◆ TR_CDC_DATA

#define TR_CDC_DATA 16

Definition at line 55 of file t4dwave.h.

◆ TR_CHN_REGS

#define TR_CHN_REGS 5

Definition at line 103 of file t4dwave.h.

◆ TR_CIR_ADDRENA

#define TR_CIR_ADDRENA 0x00001000

Definition at line 36 of file t4dwave.h.

◆ TR_CIR_MASK

#define TR_CIR_MASK 0x0000003f

Definition at line 35 of file t4dwave.h.

◆ TR_CIR_MIDENA

#define TR_CIR_MIDENA 0x00002000

Definition at line 37 of file t4dwave.h.

◆ TR_INT_ADDR

#define TR_INT_ADDR 0x00000020

Definition at line 39 of file t4dwave.h.

◆ TR_INT_SB

#define TR_INT_SB 0x00000004

Definition at line 40 of file t4dwave.h.

◆ TR_REG_ADDRINTA

#define TR_REG_ADDRINTA 0x98

Definition at line 93 of file t4dwave.h.

◆ TR_REG_ADDRINTB

#define TR_REG_ADDRINTB 0xd8

Definition at line 99 of file t4dwave.h.

◆ TR_REG_CHNBASE

#define TR_REG_CHNBASE 0xe0

Definition at line 102 of file t4dwave.h.

◆ TR_REG_CIR

#define TR_REG_CIR 0xa0

Definition at line 34 of file t4dwave.h.

◆ TR_REG_CSPF_A

#define TR_REG_CSPF_A 0x90

Definition at line 92 of file t4dwave.h.

◆ TR_REG_CSPF_B

#define TR_REG_CSPF_B 0xbc

Definition at line 98 of file t4dwave.h.

◆ TR_REG_DMAR0

#define TR_REG_DMAR0 0x00

Definition at line 42 of file t4dwave.h.

◆ TR_REG_DMAR11

#define TR_REG_DMAR11 0x0b

Definition at line 44 of file t4dwave.h.

◆ TR_REG_DMAR15

#define TR_REG_DMAR15 0x0f

Definition at line 45 of file t4dwave.h.

◆ TR_REG_DMAR4

#define TR_REG_DMAR4 0x04

Definition at line 43 of file t4dwave.h.

◆ TR_REG_INTENA

#define TR_REG_INTENA 0xa4

Definition at line 94 of file t4dwave.h.

◆ TR_REG_INTENB

#define TR_REG_INTENB 0xdc

Definition at line 100 of file t4dwave.h.

◆ TR_REG_MISCINT

#define TR_REG_MISCINT 0xb0

Definition at line 38 of file t4dwave.h.

◆ TR_REG_SBBL

#define TR_REG_SBBL 0xc0

Definition at line 51 of file t4dwave.h.

◆ TR_REG_SBCTRL

#define TR_REG_SBCTRL 0xc4

Definition at line 52 of file t4dwave.h.

◆ TR_REG_SBDELTA

#define TR_REG_SBDELTA 0xac

Definition at line 53 of file t4dwave.h.

◆ TR_REG_SBR10

#define TR_REG_SBR10 0x1f

Definition at line 50 of file t4dwave.h.

◆ TR_REG_SBR4

#define TR_REG_SBR4 0x14

Definition at line 46 of file t4dwave.h.

◆ TR_REG_SBR5

#define TR_REG_SBR5 0x15

Definition at line 47 of file t4dwave.h.

◆ TR_REG_SBR9

#define TR_REG_SBR9 0x1e

Definition at line 49 of file t4dwave.h.

◆ TR_REG_STARTA

#define TR_REG_STARTA 0x80

Definition at line 90 of file t4dwave.h.

◆ TR_REG_STARTB

#define TR_REG_STARTB 0xb4

Definition at line 96 of file t4dwave.h.

◆ TR_REG_STOPA

#define TR_REG_STOPA 0x84

Definition at line 91 of file t4dwave.h.

◆ TR_REG_STOPB

#define TR_REG_STOPB 0xb8

Definition at line 97 of file t4dwave.h.

◆ TR_SB_INTSTATUS

#define TR_SB_INTSTATUS 0x82

Definition at line 48 of file t4dwave.h.

Macros