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| #define | PCI_VENDOR_XILINX 0x10ee |
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| #define | PCI_DEVICE_XILINX_HDSPE 0x3fc6 /* AIO, MADI, AES, RayDAT */ |
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| #define | PCI_CLASS_REVISION 0x08 |
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| #define | PCI_REVISION_AIO 212 |
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| #define | PCI_REVISION_RAYDAT 211 |
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| #define | AIO 0 |
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| #define | RAYDAT 1 |
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| #define | HDSPE_OUT_ENABLE_BASE 512 |
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| #define | HDSPE_IN_ENABLE_BASE 768 |
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| #define | HDSPE_MIXER_BASE 32768 |
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| #define | HDSPE_MAX_GAIN 32768 |
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| #define | HDSPE_PAGE_ADDR_BUF_OUT 8192 |
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| #define | HDSPE_PAGE_ADDR_BUF_IN (HDSPE_PAGE_ADDR_BUF_OUT + 64 * 16 * 4) |
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| #define | HDSPE_BUF_POSITION_MASK 0x000FFC0 |
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| #define | HDSPE_FREQ_0 (1 << 6) |
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| #define | HDSPE_FREQ_1 (1 << 7) |
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| #define | HDSPE_FREQ_DOUBLE (1 << 8) |
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| #define | HDSPE_FREQ_QUAD (1 << 31) |
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| #define | HDSPE_FREQ_32000 HDSPE_FREQ_0 |
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| #define | HDSPE_FREQ_44100 HDSPE_FREQ_1 |
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| #define | HDSPE_FREQ_48000 (HDSPE_FREQ_0 | HDSPE_FREQ_1) |
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| #define | HDSPE_FREQ_MASK |
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| #define | HDSPE_FREQ_MASK_DEFAULT HDSPE_FREQ_48000 |
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| #define | HDSPE_FREQ_REG 256 |
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| #define | HDSPE_FREQ_AIO 104857600000000ULL |
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| #define | HDSPE_SPEED_DEFAULT 48000 |
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| #define | HDSPE_LAT_0 (1 << 1) |
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| #define | HDSPE_LAT_1 (1 << 2) |
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| #define | HDSPE_LAT_2 (1 << 3) |
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| #define | HDSPE_LAT_MASK (HDSPE_LAT_0 | HDSPE_LAT_1 | HDSPE_LAT_2) |
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| #define | HDSPE_LAT_BYTES_MAX (4096 * 4) |
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| #define | HDSPE_LAT_BYTES_MIN (32 * 4) |
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| #define | hdspe_encode_latency(x) (((x)<<1) & HDSPE_LAT_MASK) |
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| #define | HDSP_ADGain0 (1 << 25) |
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| #define | HDSP_ADGain1 (1 << 26) |
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| #define | HDSP_DAGain0 (1 << 27) |
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| #define | HDSP_DAGain1 (1 << 28) |
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| #define | HDSP_PhoneGain0 (1 << 29) |
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| #define | HDSP_PhoneGain1 (1 << 30) |
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| #define | HDSP_ADGainMask (HDSP_ADGain0 | HDSP_ADGain1) |
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| #define | HDSP_ADGainMinus10dBV (HDSP_ADGainMask) |
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| #define | HDSP_ADGainPlus4dBu (HDSP_ADGain0) |
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| #define | HDSP_ADGainLowGain 0 |
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| #define | HDSP_DAGainMask (HDSP_DAGain0 | HDSP_DAGain1) |
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| #define | HDSP_DAGainHighGain (HDSP_DAGainMask) |
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| #define | HDSP_DAGainPlus4dBu (HDSP_DAGain0) |
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| #define | HDSP_DAGainMinus10dBV 0 |
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| #define | HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) |
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| #define | HDSP_PhoneGain0dB HDSP_PhoneGainMask |
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| #define | HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) |
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| #define | HDSP_PhoneGainMinus12dB 0 |
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| #define | HDSPM_statusRegister 0 |
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| #define | HDSPM_statusRegister2 192 |
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| #define | HDSPE_SETTINGS_REG 0 |
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| #define | HDSPE_CONTROL_REG 64 |
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| #define | HDSPE_STATUS_REG 0 |
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| #define | HDSPE_ENABLE (1 << 0) |
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| #define | HDSPM_CLOCK_MODE_MASTER (1 << 4) |
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| #define | HDSPE_AUDIO_IRQ_PENDING (1 << 0) |
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| #define | HDSPE_AUDIO_INT_ENABLE (1 << 5) |
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| #define | HDSPE_INTERRUPT_ACK 96 |
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| #define | HDSPE_MAX_SLOTS 64 /* Mono channels */ |
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| #define | HDSPE_MAX_CHANS (HDSPE_MAX_SLOTS / 2) /* Stereo pairs */ |
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| #define | HDSPE_CHANBUF_SAMPLES (16 * 1024) |
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| #define | HDSPE_CHANBUF_SIZE (4 * HDSPE_CHANBUF_SAMPLES) |
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| #define | HDSPE_DMASEGSIZE (HDSPE_CHANBUF_SIZE * HDSPE_MAX_SLOTS) |
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| #define | hdspe_read_1(sc, regno) bus_space_read_1((sc)->cst, (sc)->csh, (regno)) |
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| #define | hdspe_read_2(sc, regno) bus_space_read_2((sc)->cst, (sc)->csh, (regno)) |
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| #define | hdspe_read_4(sc, regno) bus_space_read_4((sc)->cst, (sc)->csh, (regno)) |
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| #define | hdspe_write_1(sc, regno, data) bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data)) |
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| #define | hdspe_write_2(sc, regno, data) bus_space_write_2((sc)->cst, (sc)->csh, (regno), (data)) |
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| #define | hdspe_write_4(sc, regno, data) bus_space_write_4((sc)->cst, (sc)->csh, (regno), (data)) |
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