39#define MSGU_IBDB_SET 0x20
40#define MSGU_HOST_INT_STATUS 0x30
41#define MSGU_HOST_INT_MASK 0x34
42#define MSGU_IOPIB_INT_STATUS 0x40
43#define MSGU_IOPIB_INT_MASK 0x44
44#define MSGU_IBDB_CLEAR 0x70
45#define MSGU_MSGU_CONTROL 0x74
48#define MSGU_SCRATCH_PAD_0 0xB0
49#define MSGU_SCRATCH_PAD_1 0xB4
50#define MSGU_SCRATCH_PAD_2 0xB8
51#define MSGU_SCRATCH_PAD_3 0xBC
54#define MSGU_IBDB_SET 0x04
55#define MSGU_HOST_INT_STATUS 0x08
56#define MSGU_HOST_INT_MASK 0x0C
57#define MSGU_IOPIB_INT_STATUS 0x18
58#define MSGU_IOPIB_INT_MASK 0x1C
59#define MSGU_IBDB_CLEAR 0x20
60#define MSGU_MSGU_CONTROL 0x24
63#define MSGU_SCRATCH_PAD_0 0x44
64#define MSGU_SCRATCH_PAD_1 0x48
65#define MSGU_SCRATCH_PAD_2 0x4C
66#define MSGU_SCRATCH_PAD_3 0x50
67#define MSGU_HOST_SCRATCH_PAD_0 0x54
68#define MSGU_HOST_SCRATCH_PAD_1 0x58
69#define MSGU_HOST_SCRATCH_PAD_2 0x5C
70#define MSGU_HOST_SCRATCH_PAD_3 0x60
71#define MSGU_HOST_SCRATCH_PAD_4 0x64
72#define MSGU_HOST_SCRATCH_PAD_5 0x68
73#define MSGU_HOST_SCRATCH_PAD_6 0x6C
74#define MSGU_HOST_SCRATCH_PAD_7 0x70
86#define V_Inbound_Doorbell_Set_Register 0x00
87#define V_Inbound_Doorbell_Set_RegisterU 0x04
88#define V_Inbound_Doorbell_Clear_Register 0x08
89#define V_Inbound_Doorbell_Clear_RegisterU 0x0C
90#define V_Inbound_Doorbell_Mask_Set_Register 0x10
91#define V_Inbound_Doorbell_Mask_Set_RegisterU 0x14
92#define V_Inbound_Doorbell_Mask_Clear_Register 0x18
93#define V_Inbound_Doorbell_Mask_Clear_RegisterU 0x1C
94#define V_Outbound_Doorbell_Set_Register 0x20
95#define V_Outbound_Doorbell_Set_RegisterU 0x24
96#define V_Outbound_Doorbell_Clear_Register 0x28
97#define V_Outbound_Doorbell_Clear_RegisterU 0x2C
98#define V_Outbound_Doorbell_Mask_Set_Register 0x30
99#define V_Outbound_Doorbell_Mask_Set_RegisterU 0x34
100#define V_Outbound_Doorbell_Mask_Clear_Register 0x38
101#define V_Outbound_Doorbell_Mask_Clear_RegisterU 0x3C
103#define V_Scratchpad_0_Register 0x44
104#define V_Scratchpad_1_Register 0x48
105#define V_Scratchpad_2_Register 0x4C
106#define V_Scratchpad_3_Register 0x50
107#define V_Host_Scratchpad_0_Register 0x54
108#define V_Host_Scratchpad_1_Register 0x58
109#define V_Host_Scratchpad_2_Register 0x5C
110#define V_Host_Scratchpad_3_Register 0x60
111#define V_Host_Scratchpad_4_Register 0x64
112#define V_Host_Scratchpad_5_Register 0x68
113#define V_Scratchpad_Rsvd_0_Register 0x6C
114#define V_Scratchpad_Rsvd_1_Register 0x70
116#define V_Outbound_Queue_Consumer_Indices_Base 0x100
117#define V_Inbound_Queue_Producer_Indices 0x200
141#define V_RamEccDbErr 0x00000018
142#define V_SoftResetRegister 0x1000
143#define V_MEMBASE_II_ShiftRegister 0x1010
145#define V_GsmConfigReset 0
146#define V_GsmReadAddrParityCheck 0x38
147#define V_GsmWriteAddrParityCheck 0x40
148#define V_GsmWriteDataParityCheck 0x48
149#define V_GsmReadAddrParityIndic 0x58
150#define V_GsmWriteAddrParityIndic 0x60
151#define V_GsmWriteDataParityIndic 0x68
154#define SPCv_Reset_Reserved 0xFFFFFF3C
155#define SPCv_Reset_Read_Mask 0xC0
156#define SPCv_Reset_Read_NoReset 0x0
157#define SPCv_Reset_Read_NormalResetOccurred 0x40
158#define SPCv_Reset_Read_SoftResetHDAOccurred 0x80
159#define SPCv_Reset_Read_ChipResetOccurred 0xC0
162#define SPCv_Reset_Write_NormalReset 0x1
163#define SPCv_Reset_Write_SoftResetHDA 0x2
164#define SPCv_Reset_Write_ChipReset 0x3
196#define SPC_ODAR 0x00335C
197#define SPC_ICTIMER 0x0033C0
198#define SPC_ICCONTROL 0x0033C4
201#define MSGU_XCBI_IBDB_REG 0x003034
202#define MSGU_XCBI_OBDB_REG 0x003354
203#define MSGU_XCBI_OBDB_MASK 0x003358
204#define MSGU_XCBI_OBDB_CLEAR 0x00303C
207#define SPC_RB6_OFFSET 0x80C0
209#define RB6_MAGIC_NUMBER_RST 0x1234
211#ifdef MSGU_ACCESS_VIA_XCBI
212#define MSGU_READ_IDR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_IBDB_REG)
213#define MSGU_READ_ODMR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_MASK)
214#define MSGU_READ_ODR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_REG)
215#define MSGU_READ_ODCR ossaHwRegReadExt(agRoot, PCIBAR1, MSGU_XCBI_OBDB_CLEAR)
217#define MSGU_READ_IDR siHalRegReadExt(agRoot, GEN_MSGU_IBDB_SET, MSGU_IBDB_SET)
218#define MSGU_READ_ODMR siHalRegReadExt(agRoot, GEN_MSGU_ODMR, MSGU_ODMR)
219#define MSGU_READ_ODR siHalRegReadExt(agRoot, GEN_MSGU_ODR, MSGU_ODR)
220#define MSGU_READ_ODCR siHalRegReadExt(agRoot, GEN_MSGU_ODCR, MSGU_ODCR)
224#define ODMR_MASK_ALL 0xFFFFFFFF
225#define ODMR_CLEAR_ALL 0
227#define ODCR_CLEAR_ALL 0xFFFFFFFF
230#define IBDB_IBQ_UNFREEZE 0x08
231#define IBDB_IBQ_FREEZE 0x04
232#define IBDB_CFG_TABLE_RESET 0x02
233#define IBDB_CFG_TABLE_UPDATE 0x01
235#define IBDB_MPIIU 0x08
236#define IBDB_MPIIF 0x04
237#define IBDB_MPICT 0x02
238#define IBDB_MPIINI 0x01
241#define SCRATCH_PAD0_BAR_MASK 0xFC000000
242#define SCRATCH_PAD0_OFFSET_MASK 0x03FFFFFF
243#define SCRATCH_PAD0_AAPERR_MASK 0xFFFFFFFF
246#define SCRATCH_PAD1_POR 0x00
247#define SCRATCH_PAD1_SFR 0x01
248#define SCRATCH_PAD1_ERR 0x02
249#define SCRATCH_PAD1_RDY 0x03
250#define SCRATCH_PAD1_RST 0x04
251#define SCRATCH_PAD1_AAP1RDY_RST 0x08
252#define SCRATCH_PAD1_STATE_MASK 0xFFFFFFF0
253#define SCRATCH_PAD1_RESERVED 0x000000F0
257#define SCRATCH_PAD1_V_RAAE_MASK 0x00000003
258#define SCRATCH_PAD1_V_RAAE_ERR 0x00000002
259#define SCRATCH_PAD1_V_ILA_MASK 0x0000000C
260#define SCRATCH_PAD1_V_ILA_ERR 0x00000008
261#define SCRATCH_PAD1_V_BOOTSTATE_MASK 0x00000070
262#define SCRATCH_PAD1_V_BOOTSTATE_SUCESS 0x00000000
263#define SCRATCH_PAD1_V_BOOTSTATE_HDA_SEEPROM 0x00000010
264#define SCRATCH_PAD1_V_BOOTSTATE_HDA_BOOTSTRAP 0x00000020
265#define SCRATCH_PAD1_V_BOOTSTATE_HDA_SOFTRESET 0x00000030
266#define SCRATCH_PAD1_V_BOOTSTATE_CRIT_ERROR 0x00000040
267#define SCRATCH_PAD1_V_BOOTSTATE_R1 0x00000050
268#define SCRATCH_PAD1_V_BOOTSTATE_R2 0x00000060
269#define SCRATCH_PAD1_V_BOOTSTATE_FATAL 0x00000070
272#define SCRATCH_PAD1_V_ILA_IMAGE 0x00000080
273#define SCRATCH_PAD1_V_FW_IMAGE 0x00000100
274#define SCRATCH_PAD1_V_BIT9_RESERVED 0x00000200
275#define SCRATCH_PAD1_V_IOP0_MASK 0x00000C00
276#define SCRATCH_PAD1_V_IOP0_ERR 0x00000800
277#define SCRATCH_PAD1_V_IOP1_MASK 0x00003000
278#define SCRATCH_PAD1_V_IOP1_ERR 0x00002000
279#define SCRATCH_PAD1_V_RESERVED 0xFFFFC000
281#define SCRATCH_PAD1_V_READY ( SCRATCH_PAD1_V_RAAE_MASK | SCRATCH_PAD1_V_ILA_MASK | SCRATCH_PAD1_V_IOP0_MASK )
282#define SCRATCH_PAD1_V_ERROR ( SCRATCH_PAD1_V_RAAE_ERR | SCRATCH_PAD1_V_ILA_ERR | SCRATCH_PAD1_V_IOP0_ERR | SCRATCH_PAD1_V_IOP1_ERR )
284#define SCRATCH_PAD1_V_ILA_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_ILA_MASK ) == SCRATCH_PAD1_V_ILA_MASK) ? 0: \
285 (((ScratchPad1) & SCRATCH_PAD1_V_ILA_MASK ) == SCRATCH_PAD1_V_ILA_ERR ) ? SCRATCH_PAD1_V_ILA_ERR : 0 )
287#define SCRATCH_PAD1_V_RAAE_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_RAAE_MASK ) == SCRATCH_PAD1_V_RAAE_MASK) ? 0: \
288 (((ScratchPad1) & SCRATCH_PAD1_V_RAAE_MASK ) == SCRATCH_PAD1_V_RAAE_ERR) ? SCRATCH_PAD1_V_RAAE_ERR : 0 )
290#define SCRATCH_PAD1_V_IOP0_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_IOP0_MASK ) == SCRATCH_PAD1_V_IOP0_MASK) ? 0: \
291 (((ScratchPad1) & SCRATCH_PAD1_V_IOP0_MASK ) == SCRATCH_PAD1_V_IOP0_ERR) ? SCRATCH_PAD1_V_IOP0_ERR : 0 )
293#define SCRATCH_PAD1_V_IOP1_ERROR_STATE(ScratchPad1) ((((ScratchPad1) & SCRATCH_PAD1_V_IOP1_MASK ) == SCRATCH_PAD1_V_IOP1_MASK) ? 0: \
294 (((ScratchPad1) & SCRATCH_PAD1_V_IOP1_MASK ) == SCRATCH_PAD1_V_IOP1_ERR) ? SCRATCH_PAD1_V_IOP1_ERR : 0 )
296#define SCRATCH_PAD1_V_ERROR_STATE(ScratchPad1) ( SCRATCH_PAD1_V_ILA_ERROR_STATE(ScratchPad1) | \
297 SCRATCH_PAD1_V_RAAE_ERROR_STATE(ScratchPad1) | \
298 SCRATCH_PAD1_V_IOP0_ERROR_STATE(ScratchPad1) | \
299 SCRATCH_PAD1_V_IOP1_ERROR_STATE(ScratchPad1) )
301#define SCRATCH_PAD1_V_BOOTLDR_ERROR 0x00000070
305#define SCRATCH_PAD1_BDMA_ERR 0x80000000
306#define SCRATCH_PAD1_GSM_ERR 0x40000000
307#define SCRATCH_PAD1_MBIC1_ERR 0x20000000
308#define SCRATCH_PAD1_MBIC1_SET0_ERR 0x10000000
309#define SCRATCH_PAD1_MBIC1_SET1_ERR 0x08000000
310#define SCRATCH_PAD1_PMIC1_ERR 0x04000000
311#define SCRATCH_PAD1_PMIC2_ERR 0x02000000
312#define SCRATCH_PAD1_PMIC_EVENT_ERR 0x01000000
313#define SCRATCH_PAD1_OSSP_ERR 0x00800000
314#define SCRATCH_PAD1_SSPA_ERR 0x00400000
315#define SCRATCH_PAD1_SSPL_ERR 0x00200000
316#define SCRATCH_PAD1_HSST_ERR 0x00100000
317#define SCRATCH_PAD1_PCS_ERR 0x00080000
318#define SCRATCH_PAD1_FW_INIT_ERR 0x00008000
319#define SCRATCH_PAD1_FW_ASRT_ERR 0x00004000
320#define SCRATCH_PAD1_FW_WDG_ERR 0x00002000
321#define SCRATCH_PAD1_AAP_ERROR_STATE 0x00000002
322#define SCRATCH_PAD1_AAP_READY 0x00000003
326#define SCRATCH_PAD2_POR 0x00
327#define SCRATCH_PAD2_SFR 0x01
328#define SCRATCH_PAD2_ERR 0x02
329#define SCRATCH_PAD2_RDY 0x03
330#define SCRATCH_PAD2_FWRDY_RST 0x04
331#define SCRATCH_PAD2_IOPRDY_RST 0x08
332#define SCRATCH_PAD2_STATE_MASK 0xFFFFFFF0
333#define SCRATCH_PAD2_RESERVED 0x000000F0
336#define SCRATCH_PAD2_BDMA_ERR 0x80000000
337#define SCRATCH_PAD2_GSM_ERR 0x40000000
338#define SCRATCH_PAD2_MBIC3_ERR 0x20000000
339#define SCRATCH_PAD2_MBIC3_SET0_ERR 0x10000000
340#define SCRATCH_PAD2_MBIC3_SET1_ERR 0x08000000
341#define SCRATCH_PAD2_PMIC1_ERR 0x04000000
342#define SCRATCH_PAD2_PMIC2_ERR 0x02000000
343#define SCRATCH_PAD2_PMIC_EVENT_ERR 0x01000000
344#define SCRATCH_PAD2_OSSP_ERR 0x00800000
345#define SCRATCH_PAD2_SSPA_ERR 0x00400000
346#define SCRATCH_PAD2_SSPL_ERR 0x00200000
347#define SCRATCH_PAD2_HSST_ERR 0x00100000
348#define SCRATCH_PAD2_PCS_ERR 0x00080000
350#define SCRATCH_PAD2_FW_BOOT_ROM_ERROR 0x00010000
351#define SCRATCH_PAD2_FW_ILA_ERR 0x00008000
352#define SCRATCH_PAD2_FW_FLM_ERR 0x00004000
353#define SCRATCH_PAD2_FW_FW_ASRT_ERR 0x00002000
354#define SCRATCH_PAD2_FW_HW_WDG_ERR 0x00001000
355#define SCRATCH_PAD2_FW_GEN_EXCEPTION_ERR 0x00000800
356#define SCRATCH_PAD2_FW_UNDTMN_ERR 0x00000400
357#define SCRATCH_PAD2_FW_HW_FATAL_ERR 0x00000200
358#define SCRATCH_PAD2_FW_HW_NON_FATAL_ERR 0x00000100
359#define SCRATCH_PAD2_FW_HW_MASK 0x000000FF
360#define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCS_ERR 0x00
361#define SCRATCH_PAD2_HW_ERROR_INT_INDX_GSM_ERR 0x01
362#define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP0_ERR 0x02
363#define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP1_ERR 0x03
364#define SCRATCH_PAD2_HW_ERROR_INT_INDX_OSSP2_ERR 0x04
365#define SCRATCH_PAD2_HW_ERROR_INT_INDX_ERAAE_ERR 0x05
366#define SCRATCH_PAD2_HW_ERROR_INT_INDX_SDS_ERR 0x06
367#define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_CORE_ERR 0x08
368#define SCRATCH_PAD2_HW_ERROR_INT_INDX_PCIE_AL_ERR 0x0C
369#define SCRATCH_PAD2_HW_ERROR_INT_INDX_MSGU_ERR 0x0E
370#define SCRATCH_PAD2_HW_ERROR_INT_INDX_SPBC_ERR 0x0F
371#define SCRATCH_PAD2_HW_ERROR_INT_INDX_BDMA_ERR 0x10
372#define SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSL2B_ERR 0x13
373#define SCRATCH_PAD2_HW_ERROR_INT_INDX_MCPSDC_ERR 0x14
374#define SCRATCH_PAD2_HW_ERROR_INT_INDX_UNDETERMINED_ERROR_OCCURRED 0xFF
378#define SCRATCH_PAD_ERROR_MASK 0xFFFFFF00
379#define SCRATCH_PAD_STATE_MASK 0x00000003
381#define SPCV_RAAE_STATE_MASK 0x3
382#define SPCV_IOP0_STATE_MASK ((1 << 10) | (1 << 11))
383#define SPCV_IOP1_STATE_MASK ((1 << 12) | (1 << 13))
384#define SPCV_ERROR_VALUE 0x2
387#define SCRATCH_PAD3_FW_IMAGE_MASK 0x0000000F
388#define SCRATCH_PAD3_FW_IMAGE_FLAG_VALID 0x00000008
389#define SCRATCH_PAD3_FW_IMAGE_B_VALID 0x00000004
390#define SCRATCH_PAD3_FW_IMAGE_A_VALID 0x00000002
391#define SCRATCH_PAD3_FW_IMAGE_B_ACTIVE 0x00000001
394#define SCRATCH_PAD3_V_ 0x00000001
396#define SCRATCH_PAD3_V_ENC_DISABLED 0x00000000
397#define SCRATCH_PAD3_V_ENC_DIS_ERR 0x00000001
398#define SCRATCH_PAD3_V_ENC_ENA_ERR 0x00000002
399#define SCRATCH_PAD3_V_ENC_READY 0x00000003
400#define SCRATCH_PAD3_V_ENC_MASK SCRATCH_PAD3_V_ENC_READY
402#define SCRATCH_PAD3_V_AUT 0x00000008
403#define SCRATCH_PAD3_V_ARF 0x00000004
405#define SCRATCH_PAD3_V_XTS_ENABLED (1 << SHIFT14)
406#define SCRATCH_PAD3_V_SMA_ENABLED (1 << SHIFT4 )
407#define SCRATCH_PAD3_V_SMB_ENABLED (1 << SHIFT5 )
408#define SCRATCH_PAD3_V_SMF_ENABLED 0
409#define SCRATCH_PAD3_V_SM_MASK 0x000000F0
410#define SCRATCH_PAD3_V_ERR_CODE 0x00FF0000
414#define GSM_CONFIG_RESET 0x00000000
415#define RAM_ECC_DB_ERR 0x00000018
416#define GSM_READ_ADDR_PARITY_INDIC 0x00000058
417#define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
418#define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
419#define GSM_READ_ADDR_PARITY_CHECK 0x00000038
420#define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
421#define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
424#define SPC_SOFT_RESET_SIGNATURE 0x252acbcd
425#define SPC_HDASOFT_RESET_SIGNATURE 0xa5aa27d7
430#define SPC_REG_RESET 0x000000
431#define SPC_REG_DEVICE_LCLK 0x000058
433#define SPC_READ_RESET_REG siHalRegReadExt(agRoot, GEN_SPC_REG_RESET, SPC_REG_RESET)
435#define SPC_WRITE_RESET_REG(value) ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_REG_RESET, value);
439#define MBIC_NMI_ENABLE_VPE0_IOP 0x000418
440#define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418
443#define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
444#define PCIE_EVENT_INTERRUPT 0x003044
445#define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
446#define PCIE_ERROR_INTERRUPT 0x00304C
449#define SPC_REG_MSGU_CONFIG 0x003018
450#define PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE 0x00000010
453#define SPC_REG_RESET_OSSP 0x00000001
454#define SPC_REG_RESET_RAAE 0x00000002
455#define SPC_REG_RESET_PCS_SPBC 0x00000004
456#define SPC_REG_RESET_PCS_IOP_SS 0x00000008
457#define SPC_REG_RESET_PCS_AAP1_SS 0x00000010
458#define SPC_REG_RESET_PCS_AAP2_SS 0x00000020
459#define SPC_REG_RESET_PCS_LM 0x00000040
460#define SPC_REG_RESET_PCS 0x00000080
461#define SPC_REG_RESET_GSM 0x00000100
462#define SPC_REG_RESET_DDR2 0x00010000
463#define SPC_REG_RESET_BDMA_CORE 0x00020000
464#define SPC_REG_RESET_BDMA_SXCBI 0x00040000
465#define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000
466#define SPC_REG_RESET_PCIE_PWR 0x00100000
467#define SPC_REG_RESET_PCIE_SFT 0x00200000
468#define SPC_REG_RESET_PCS_SXCBI 0x00400000
469#define SPC_REG_RESET_LMS_SXCBI 0x00800000
470#define SPC_REG_RESET_PMIC_SXCBI 0x01000000
471#define SPC_REG_RESET_PMIC_CORE 0x02000000
472#define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000
473#define SPC_REG_RESET_DEVICE 0x80000000
476#define SPC_REG_DEVICE_REV 0x000024
477#define SPC_REG_DEVICE_REV_MASK 0x0000000F
481#define SPC_REG_TOP_DEVICE_ID 0x20
482#define SPC_TOP_DEVICE_ID 0x8001
484#define SPC_REG_TOP_BOOT_STRAP 0x8
485#define SPC_TOP_BOOT_STRAP 0x02C0A682
489#define COUNT_OFFSET 0x4000
490#define LCLK_CLEAR 0x2
492#define CNTL_OFFSET 0x100
493#define L0_LCLK_CLEAR 0x2
495#define DEVICE_LCLK_CLEAR 0x40
499#define SPC_SSPL_COUNTER_CNTL 0x001030
500#define SPC_INVALID_DW_COUNT 0x001034
501#define SPC_RUN_DISP_ERROR_COUNT 0x001038
502#define SPC_CODE_VIOLATION_COUNT 0x00103C
503#define SPC_LOSS_DW_SYNC_COUNT 0x001040
504#define SPC_PHY_RESET_PROBLEM_COUNT 0x001044
505#define SPC_READ_DEV_REV ossaHwRegReadExt(agRoot, PCIBAR2, SPC_REG_DEVICE_REV);
507#define SPC_READ_COUNTER_CNTL(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_SSPL_COUNTER_CNTL + (COUNT_OFFSET * phyId))
508#define SPC_WRITE_COUNTER_CNTL(phyId, value) ossaHwRegWriteExt(agRoot, PCIBAR2, SPC_SSPL_COUNTER_CNTL + (COUNT_OFFSET * phyId), value)
509#define SPC_READ_INV_DW_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_INVALID_DW_COUNT + (COUNT_OFFSET * phyId))
510#define SPC_READ_DISP_ERR_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_RUN_DISP_ERROR_COUNT + (COUNT_OFFSET * phyId))
511#define SPC_READ_CODE_VIO_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_CODE_VIOLATION_COUNT + (COUNT_OFFSET * phyId))
512#define SPC_READ_LOSS_DW_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_LOSS_DW_SYNC_COUNT + (COUNT_OFFSET * phyId))
513#define SPC_READ_PHY_RESET_COUNT(phyId) ossaHwRegReadExt(agRoot, PCIBAR2, SPC_PHY_RESET_PROBLEM_COUNT + (COUNT_OFFSET * phyId))
515#define SPC_L0_ERR_CNT_CNTL 0x0041B0
516#define SPC_READ_L0ERR_CNT_CNTL(phyId) ossaHwRegReadExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId))
517#define SPC_WRITE_L0ERR_CNT_CNTL(phyId, value) ossaHwRegWriteExt(agRoot, PCIBAR1, SPC_L0_ERR_CNT_CNTL + (CNTL_OFFSET * phyId), value)
520#define SPC_IBW_AXI_TRANSLATION_LOW 0x003258
524#define HDA_CMD_OFFSET256K 0x0003FFC0
525#define HDA_RSP_OFFSET256K 0x0003FFE0
528#define HDA_CMD_OFFSET512K 0x0007FFC0
529#define HDA_RSP_OFFSET512K 0x0007FFE0
532#define HDA_CMD_OFFSET768K 0x000BFFC0
533#define HDA_RSP_OFFSET768K 0x000BFFE0
536#define HDA_CMD_OFFSET1MB 0x0000FEC0
537#define HDA_RSP_OFFSET1MB 0x0000FEE0
567#define SPC_V_HDA_COMMAND_OFFSET 0x000042c0
568#define SPC_V_HDA_RESPONSE_OFFSET 0x000042e0
571#define HDA_C_PA_OFFSET 0x1F
572#define HDA_SEQ_ID_OFFSET 0x1E
573#define HDA_PAR_LEN_OFFSET 0x04
574#define HDA_CMD_CODE_OFFSET 0x1C
575#define HDA_RSP_CODE_OFFSET 0x1C
576#define SM_HDA_RSP_OFFSET1MB_PLUS_HDA_RSP_CODE_OFFSET (HDA_RSP_OFFSET1MB + HDA_RSP_CODE_OFFSET)
579#define SPC_V_HDAC_PA 0xCB
580#define SPC_V_HDAC_BUF_INFO 0x0001
581#define SPC_V_HDAC_EXEC 0x0002
582#define SPC_V_HDAC_RESET 0x0003
583#define SPC_V_HDAC_DMA 0x0004
585#define SPC_V_HDAC_PA_MASK 0xFF000000
586#define SPC_V_HDAC_SEQID_MASK 0x00FF0000
587#define SPC_V_HDAC_CMDCODE_MASK 0x0000FFFF
590#define SPC_V_HDAR_PA 0xDB
591#define SPC_V_HDAR_BUF_INFO 0x8001
592#define SPC_V_HDAR_IDLE 0x8002
593#define SPC_V_HDAR_BAD_IMG 0x8003
594#define SPC_V_HDAR_BAD_CMD 0x8004
595#define SPC_V_HDAR_INTL_ERR 0x8005
596#define SPC_V_HDAR_EXEC 0x8006
598#define SPC_V_HDAR_PA_MASK 0xFF000000
599#define SPC_V_HDAR_SEQID_MASK 0x00FF0000
600#define SPC_V_HDAR_RSPCODE_MASK 0x0000FFFF
602#define ILAHDA_RAAE_IMG_GET 0x11
603#define ILAHDA_IOP_IMG_GET 0x10
605#define ILAHDAC_RAAE_IMG_DONE 0x81
608#define HDA_AES_DIF_FUNC 0xFEDFAE1F
612#define PMIC_MU_CFG_1_BITMSK_MU_IO_ENABLE 0x00000001
613#define PMIC_MU_CFG_1_BITMSK_MU_IO_WIR 0x0000000C
614#define PMIC_MU_CFG_1_BITMSK_MU_MEM_ENABLE 0x00000010
615#define PMIC_MU_CFG_1_BITMSK_MU_MEM_OFFSET 0xFFFFFC00
618#define MU_MEM_OFFSET 0x0
619#define MSGU_MU_IO_WIR 0x8
621#define BOOTTLOADERHDA_IDLE 0x8002
622#define HDAR_BAD_IMG 0x8003
623#define HDAR_BAD_CMD 0x8004
624#define HDAR_EXEC 0x8006
626#define CEILING(X, rem) ((((bit32)X % rem) > 0) ? (bit32)(X/rem+1) : (bit32)(X/rem))
628#define GSMSM_AXI_LOWERADDR 0x00400000
629#define SHIFT_MASK 0xFFFF0000
630#define OFFSET_MASK 0x0000FFFF
631#define SIZE_64KB 0x00010000
632#define ILA_ISTR_ADDROFFSETHDA 0x0007E000
633#define HDA_STATUS_BITS 0x0000FFFF
637#define ILAHDA_IOP_IMG_GET 0x10
638#define ILAHDA_AAP1_IMG_GET 0x11
639#define ILAHDA_AAP2_IMG_GET 0x12
640#define ILAHDA_EXITGOOD 0x1F
643#define ILAHDAC_IOP_IMG_DONE 0x00000080
644#define ILAHDAC_AAP1_IMG_DONE 0x00000081
645#define ILAHDAC_AAP2_IMG_DONE 0x00000082
646#define ILAHDAC_ISTR_IMG_DONE 0x00000083
647#define ILAHDAC_GOTOHDA 0x000000ff
649#define HDA_ISTR_DONE (bit32)(ILAHDAC_ISTR_IMG_DONE << 24)
650#define HDA_AAP1_DONE (bit32)(ILAHDAC_AAP1_IMG_DONE << 24)
651#define HDA_IOP_DONE (bit32)(ILAHDAC_IOP_IMG_DONE << 24)
653#define RB6_ACCESS_REG 0x6A0000
654#define HDAC_EXEC_CMD 0x0002
656#define HDA_SEQ_ID_BITS 0x00ff0000
657#define HDA_GSM_OFFSET_BITS 0x00FFFFFF
658#define MBIC_AAP1_ADDR_BASE 0x060000
659#define MBIC_GSM_SM_BASE 0x04F0000
660#define MBIC_IOP_ADDR_BASE 0x070000
661#define GSM_ADDR_BASE 0x0700000
662#define SPC_TOP_LEVEL_ADDR_BASE 0x000000
663#define GSM_CONFIG_RESET_VALUE 0x00003b00
664#define GPIO_ADDR_BASE 0x00090000
665#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c
669#define SA_FATAL_ERROR_SP1_AAP1_ERR_MASK 0x3
670#define SA_FATAL_ERROR_SP2_IOP_ERR_MASK 0x3
671#define SA_FATAL_ERROR_FATAL_ERROR 0x2
674#define PCIE_TRIGGER_ON_REGISTER_READ V_Host_Scratchpad_2_Register
676#define PCI_TRIGGER_INIT_TEST 1
677#define PCI_TRIGGER_OFFSET_MISMATCH 2
678#define PCI_TRIGGER_COAL_IOMB_ERROR 4
679#define PCI_TRIGGER_COAL_INVALID 8
struct spcv_hda_cmd_s spcv_hda_cmd_t
struct spcv_hda_rsp_s spcv_hda_rsp_t
@ GEN_MSGU_HOST_SCRATCH_PAD_3
@ GEN_MSGU_HOST_SCRATCH_PAD_1
@ GEN_MSGU_HOST_SCRATCH_PAD_0
@ GEN_MSGU_HOST_SCRATCH_PAD_2
bit32 C_PA_SEQ_ID_CMD_CODE
bit32 R_PA_SEQ_ID_RSP_CODE