42MALLOC_DEFINE(M_IXGBE_SRIOV,
"ix_sriov",
"ix SR-IOV allocations");
50 return pci_iov_detach(dev);
59 nvlist_t *pf_schema, *vf_schema;
61 pf_schema = pci_iov_schema_alloc_node();
62 vf_schema = pci_iov_schema_alloc_node();
63 pci_iov_schema_add_unicast_mac(vf_schema,
"mac-addr", 0, NULL);
64 pci_iov_schema_add_bool(vf_schema,
"mac-anti-spoof",
65 IOV_SCHEMA_HASDEFAULT,
true);
66 pci_iov_schema_add_bool(vf_schema,
"allow-set-mac",
67 IOV_SCHEMA_HASDEFAULT,
false);
68 pci_iov_schema_add_bool(vf_schema,
"allow-promisc",
69 IOV_SCHEMA_HASDEFAULT,
false);
70 *error = pci_iov_attach(dev, pf_schema, vf_schema);
73 "Error %d setting up SR-IOV\n", *error);
86 for (i = 0; i < sc->num_rx_queues; i++) {
91 for (i = 0; i < sc->num_tx_queues; i++) {
101 if (vf->
flags & IXGBE_VF_CTS)
110 msg &= IXGBE_VT_MSG_MASK;
117 msg &= IXGBE_VT_MSG_MASK;
124 if (!(vf->
flags & IXGBE_VF_CTS))
125 ixgbe_send_vf_nack(sc, vf, 0);
128static inline boolean_t
129ixgbe_vf_mac_changed(
struct ixgbe_vf *vf,
const uint8_t *mac)
131 return (bcmp(mac, vf->
ether_addr, ETHER_ADDR_LEN) != 0);
135ixgbe_vf_queues(
int mode)
151 return ((vfnum * ixgbe_vf_queues(mode)) + num);
155ixgbe_update_max_frame(
struct ixgbe_softc * sc,
int max_frame)
157 if (sc->max_frame_size < max_frame)
158 sc->max_frame_size = max_frame;
177 panic(
"Unexpected SR-IOV mode %d", iov_mode);
200 panic(
"Unexpected SR-IOV mode %d", iov_mode);
211 for (
int i = 0; i < sc->
num_vfs; i++) {
213 if (vf->
flags & IXGBE_VF_ACTIVE)
224 uint32_t vmolr, vmvir;
236 vmolr &= ~IXGBE_VMOLR_MPE;
249 vmolr &= ~IXGBE_VMOLR_AUPE;
272 case IXGBE_API_VER_1_0:
273 case IXGBE_API_VER_UNKNOWN:
278 if (sc->max_frame_size > ETHER_MAX_LEN ||
285 case IXGBE_API_VER_1_1:
298 if (sc->max_frame_size <= ETHER_MAX_LEN)
315 vf->
api_ver = IXGBE_API_VER_UNKNOWN;
323 uint32_t vf_index, vfte;
327 vf_index = IXGBE_VF_INDEX(vf->
pool);
329 vfte |= IXGBE_VF_BIT(vf->
pool);
338 uint32_t vf_index, vfre;
342 vf_index = IXGBE_VF_INDEX(vf->
pool);
344 if (ixgbe_vf_frame_size_compatible(sc, vf))
345 vfre |= IXGBE_VF_BIT(vf->
pool);
347 vfre &= ~IXGBE_VF_BIT(vf->
pool);
361 ixgbe_process_vf_reset(sc, vf);
370 ixgbe_vf_enable_transmit(sc, vf);
371 ixgbe_vf_enable_receive(sc, vf);
373 vf->
flags |= IXGBE_VF_CTS;
376 bcopy(vf->
ether_addr, &resp[1], ETHER_ADDR_LEN);
387 mac = (uint8_t*)&msg[1];
390 if (!(vf->
flags & IXGBE_VF_CAP_MAC) && ixgbe_vf_mac_changed(vf,
mac)) {
391 ixgbe_send_vf_nack(sc, vf, msg[0]);
396 ixgbe_send_vf_nack(sc, vf, msg[0]);
405 ixgbe_send_vf_ack(sc, vf, msg[0]);
416 u16 *list = (
u16*)&msg[1];
418 u32 vmolr, vec_bit, vec_reg, mta_reg;
428 for (
int i = 0; i < entries; i++) {
430 vec_reg = (vf->
mc_hash[i] >> 5) & 0x7F;
431 vec_bit = vf->
mc_hash[i] & 0x1F;
433 mta_reg |= (1 << vec_bit);
439 ixgbe_send_vf_ack(sc, vf, msg[0]);
451 enable = IXGBE_VT_MSGINFO(msg[0]);
454 if (!(vf->
flags & IXGBE_VF_CAP_VLAN)) {
455 ixgbe_send_vf_nack(sc, vf, msg[0]);
460 if (tag == 0 && enable != 0) {
461 ixgbe_send_vf_nack(sc, vf, msg[0]);
466 ixgbe_send_vf_ack(sc, vf, msg[0]);
474 uint32_t vf_max_size, pf_max_size, mhadd;
477 vf_max_size = msg[1];
479 if (vf_max_size < ETHER_CRC_LEN) {
481 ixgbe_send_vf_ack(sc, vf, msg[0]);
485 vf_max_size -= ETHER_CRC_LEN;
489 ixgbe_send_vf_ack(sc, vf, msg[0]);
500 ixgbe_vf_enable_receive(sc, vf);
506 mhadd &= ~IXGBE_MHADD_MFS_MASK;
511 ixgbe_send_vf_ack(sc, vf, msg[0]);
520 ixgbe_send_vf_nack(sc, vf, msg[0]);
530 case IXGBE_API_VER_1_0:
531 case IXGBE_API_VER_1_1:
533 ixgbe_send_vf_ack(sc, vf, msg[0]);
536 vf->
api_ver = IXGBE_API_VER_UNKNOWN;
537 ixgbe_send_vf_nack(sc, vf, msg[0]);
547 uint32_t resp[IXGBE_VF_GET_QUEUES_RESP_LEN];
554 case IXGBE_API_VER_1_0:
555 case IXGBE_API_VER_UNKNOWN:
556 ixgbe_send_vf_nack(sc, vf, msg[0]);
563 num_queues = ixgbe_vf_queues(sc->
iov_mode);
574ixgbe_process_vf_msg(if_ctx_t ctx,
struct ixgbe_vf *vf)
578 struct ifnet *ifp = iflib_get_ifp(ctx);
591 CTR3(KTR_MALLOC,
"%s: received msg %x from %d", ifp->if_xname,
594 ixgbe_vf_reset_msg(sc, vf, msg);
598 if (!(vf->
flags & IXGBE_VF_CTS)) {
599 ixgbe_send_vf_nack(sc, vf, msg[0]);
603 switch (msg[0] & IXGBE_VT_MSG_MASK) {
605 ixgbe_vf_set_mac(sc, vf, msg);
608 ixgbe_vf_set_mc_addr(sc, vf, msg);
611 ixgbe_vf_set_vlan(sc, vf, msg);
614 ixgbe_vf_set_lpe(sc, vf, msg);
617 ixgbe_vf_set_macvlan(sc, vf, msg);
620 ixgbe_vf_api_negotiate(sc, vf, msg);
623 ixgbe_vf_get_queues(sc, vf, msg);
626 ixgbe_send_vf_nack(sc, vf, msg[0]);
635 if_ctx_t ctx = context;
643 for (i = 0; i < sc->
num_vfs; i++) {
646 if (vf->
flags & IXGBE_VF_ACTIVE) {
648 ixgbe_process_vf_reset(sc, vf);
651 ixgbe_process_vf_msg(ctx, vf);
654 ixgbe_process_vf_ack(sc, vf);
660ixgbe_if_iov_init(if_ctx_t ctx,
u16 num_vfs,
const nvlist_t *config)
665 sc = iflib_get_softc(
ctx);
696 if (sc->
vfs == NULL) {
716ixgbe_if_iov_uninit(if_ctx_t
ctx)
720 uint32_t pf_reg, vf_reg;
722 sc = iflib_get_softc(
ctx);
726 pf_reg = IXGBE_VF_INDEX(sc->
pool);
739 free(sc->
vfs, M_IXGBE_SRIOV);
742 sc->
feat_en &= ~IXGBE_FEATURE_SRIOV;
749 uint32_t vf_index, pfmbimr;
753 if (!(vf->
flags & IXGBE_VF_ACTIVE))
756 vf_index = IXGBE_VF_INDEX(vf->
pool);
758 pfmbimr |= IXGBE_VF_BIT(vf->
pool);
761 ixgbe_vf_set_default_vlan(sc, vf, vf->
vlan_tag);
770 ixgbe_vf_enable_transmit(sc, vf);
771 ixgbe_vf_enable_receive(sc, vf);
780 uint32_t mrqc, mtqc, vt_ctl, vf_reg, gcr_ext, gpie;
792 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
795 gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
796 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
811 panic(
"Unexpected SR-IOV mode %d", sc->
iov_mode);
820 vf_reg = IXGBE_VF_INDEX(sc->
pool);
831 for (i = 0; i < sc->
num_vfs; i++)
832 ixgbe_init_vf(sc, &sc->
vfs[i]);
842 for (
int i = 0; i < sc->
num_vfs; i++) {
844 if (vf->
flags & IXGBE_VF_ACTIVE)
850ixgbe_if_iov_vf_add(if_ctx_t ctx,
u16 vfnum,
const nvlist_t *config)
856 sc = iflib_get_softc(ctx);
858 KASSERT(vfnum < sc->num_vfs, (
"VF index %d is out of range %d",
861 vf = &sc->
vfs[vfnum];
870 if (nvlist_exists_binary(config,
"mac-addr")) {
871 mac = nvlist_get_binary(config,
"mac-addr", NULL);
873 if (nvlist_get_bool(config,
"allow-set-mac"))
874 vf->
flags |= IXGBE_VF_CAP_MAC;
880 vf->
flags |= IXGBE_VF_CAP_MAC;
882 vf->
flags |= IXGBE_VF_ACTIVE;
884 ixgbe_init_vf(sc, vf);
MALLOC_DEFINE(M_IXGBE, "ix", "ix driver allocations")
void ixgbe_if_init(if_ctx_t ctx)
void ixgbe_handle_mbx(void *context)
#define IXGBE_MAX_FRAME_SIZE
s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, u32 enable_addr)
s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, bool vlvf_bypass)
s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
s32 ixgbe_validate_mac_addr(u8 *mac_addr)
#define IXGBE_FEATURE_SRIOV
#define IXGBE_VT_MSGTYPE_ACK
#define IXGBE_VF_GET_QUEUES
#define IXGBE_VT_MSGINFO_MASK
#define IXGBE_VF_SET_VLAN
#define IXGBE_VT_MSGTYPE_NACK
#define IXGBE_VF_TX_QUEUES
#define IXGBE_VT_MSGINFO_SHIFT
#define IXGBE_VF_RX_QUEUES
#define IXGBE_VFMAILBOX_SIZE
#define IXGBE_VF_API_NEGOTIATE
#define IXGBE_VF_SET_MACVLAN
#define IXGBE_VF_DEF_QUEUE
#define IXGBE_VF_PERMADDR_MSG_LEN
#define IXGBE_VF_TRANS_VLAN
#define IXGBE_VT_MSGTYPE_CTS
#define IXGBE_PF_CONTROL_MSG
#define IXGBE_VF_SET_MULTICAST
#define IXGBE_VF_SET_MAC_ADDR
#define IXGBE_READ_REG(a, reg)
#define UNREFERENCED_PARAMETER(_p)
#define IXGBE_WRITE_REG(a, reg, val)
#define ixgbe_vf_que_index(_a, _b, _c)
#define ixgbe_get_mrqc(_a)
#define ixgbe_align_all_queue_indices(_a)
#define ixgbe_pci_iov_detach(_a)
#define ixgbe_ping_all_vfs(_a)
#define ixgbe_define_iov_schemas(_a, _b)
#define ixgbe_initialize_iov(_a)
#define ixgbe_get_mtqc(_a)
#define ixgbe_recalculate_max_frame(_a)
#define IXGBE_MTQC_VT_ENA
#define IXGBE_MHADD_MFS_MASK
#define IXGBE_VMOLR_ROMPE
#define IXGBE_MHADD_MFS_SHIFT
#define IXGBE_MRQC_VMDQRSS64EN
#define IXGBE_VT_CTL_VT_ENABLE
#define IXGBE_GCR_EXT_MSIX_EN
#define IXGBE_VT_CTL_REPLEN
#define IXGBE_GPIE_VTMODE_32
#define IXGBE_GCR_EXT_VT_MODE_32
#define IXGBE_GPIE_VTMODE_64
#define IXGBE_MRQC_VMDQRSS32EN
#define IXGBE_VMVIR_VLANA_DEFAULT
#define IXGBE_VLVF_VLANID_MASK
#define IXGBE_VT_CTL_POOL_SHIFT
#define IXGBE_GCR_EXT_VT_MODE_64
#define IXGBE_PFDTXGSWC_VT_LBEN
#define IXGBE_PFMBIMR(_i)
#define IXGBE_MTQC_64Q_1PB
struct ixgbe_mac_info mac
struct ixgbe_mbx_info mbx
struct ixgbe_mbx_operations ops
s32(* check_for_ack)(struct ixgbe_hw *, u16)
s32(* check_for_msg)(struct ixgbe_hw *, u16)
s32(* check_for_rst)(struct ixgbe_hw *, u16)
s32(* read)(struct ixgbe_hw *, u32 *, u16, u16)
s32(* write)(struct ixgbe_hw *, u32 *, u16, u16)
struct ix_tx_queue * tx_queues
struct ix_rx_queue * rx_queues
struct ixgbevf_hw_stats vf
uint16_t mc_hash[IXGBE_MAX_VF_MC]
uint8_t ether_addr[ETHER_ADDR_LEN]