43#include <net/netmap.h>
44#include <dev/netmap/netmap_kern.h>
135 DEVMETHOD(device_probe, iflib_device_probe),
136 DEVMETHOD(device_attach, iflib_device_attach),
137 DEVMETHOD(device_detach, iflib_device_detach),
138 DEVMETHOD(device_shutdown, iflib_device_shutdown),
210 .isc_magic = IFLIB_MAGIC,
211 .isc_q_align = PAGE_SIZE,
212 .isc_tx_maxsize =
IXGBE_TSO_SIZE +
sizeof(
struct ether_vlan_header),
213 .isc_tx_maxsegsize = PAGE_SIZE,
214 .isc_tso_maxsize =
IXGBE_TSO_SIZE +
sizeof(
struct ether_vlan_header),
215 .isc_tso_maxsegsize = PAGE_SIZE,
216 .isc_rx_maxsize = MJUM16BYTES,
217 .isc_rx_nsegments = 1,
218 .isc_rx_maxsegsize = MJUM16BYTES,
222 .isc_admin_intrcnt = 1,
226 .isc_flags = IFLIB_IS_VF | IFLIB_TSO_INIT_IP,
247 int ntxqs,
int ntxqsets)
250 if_softc_ctx_t scctx = sc->
shared;
254 MPASS(
sc->num_tx_queues == ntxqsets);
260 M_DEVBUF, M_NOWAIT | M_ZERO);
262 device_printf(iflib_get_dev(ctx),
263 "Unable to allocate TX ring memory\n");
267 for (i = 0, que =
sc->
tx_queues; i < ntxqsets; i++, que++) {
274 if (!(txr->
tx_rsq = (qidx_t *)malloc(
sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
278 for (j = 0; j < scctx->isc_ntxd[0]; j++)
279 txr->
tx_rsq[j] = QIDX_INVALID;
290 device_printf(iflib_get_dev(ctx),
"allocated for %d queues\n",
306 int nrxqs,
int nrxqsets)
312 MPASS(
sc->num_rx_queues == nrxqsets);
318 M_DEVBUF, M_NOWAIT | M_ZERO);
320 device_printf(iflib_get_dev(ctx),
321 "Unable to allocate TX ring memory\n");
326 for (i = 0, que =
sc->
rx_queues; i < nrxqsets; i++, que++) {
340 device_printf(iflib_get_dev(ctx),
"allocated for %d rx queues\n",
364 for (i = 0; i <
sc->num_tx_queues; i++, que++) {
369 free(txr->
tx_rsq, M_DEVBUF);
395 if_softc_ctx_t scctx;
402 dev = iflib_get_dev(ctx);
403 sc = iflib_get_softc(ctx);
407 scctx = sc->
shared = iflib_get_softc_ctx(ctx);
408 sc->
media = iflib_get_media(ctx);
413 device_printf(dev,
"ixv_allocate_pci_resources() failed!\n");
419 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
420 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
"debug",
421 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
431 device_printf(dev,
"ixgbe_init_ops_vf() failed!\n");
441 device_printf(dev,
"...reset_hw() failure: Reset Failed!\n");
443 device_printf(dev,
"...reset_hw() failed with error %d\n",
452 device_printf(dev,
"...init_hw() failed with error %d\n",
462 "Mailbox API negotiation failed during attach!\n");
475 ether_gen_addr(iflib_get_ifp(ctx),
476 (
struct ether_addr *)hw->
mac.
addr);
483 iflib_set_mac(ctx, hw->
mac.
addr);
488 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 2;
491 scctx->isc_ntxqsets_max = scctx->isc_nrxqsets_max = 1;
493 scctx->isc_txqsizes[0] =
496 scctx->isc_rxqsizes[0] =
500 scctx->isc_tx_csum_flags = CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_TSO |
501 CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_IP6_TSO;
503 scctx->isc_msix_bar = pci_msix_table_bar(dev);
504 scctx->isc_tx_tso_segments_max = scctx->isc_tx_nsegments;
506 scctx->isc_tx_tso_segsize_max = PAGE_SIZE;
516 scctx->isc_capabilities ^= IFCAP_WOL;
517 scctx->isc_capenable = scctx->isc_capabilities;
533 device_t
dev = iflib_get_dev(
ctx);
539 device_printf(
dev,
"Interface setup failed: %d\n", error);
578 struct ifnet *ifp = iflib_get_ifp(ctx);
606 struct ifnet *ifp = iflib_get_ifp(ctx);
607 device_t dev = iflib_get_dev(ctx);
628 "Mailbox API negotiation failed in if_init!\n");
663 device_printf(dev,
"VF is disabled by PF\n");
681 u32 queue = 1 << vector;
695 u64 queue = (
u64)(1 << vector);
715 return (FILTER_SCHEDULE_THREAD);
737 iflib_admin_intr_deferred(sc->
ctx);
741 return (FILTER_HANDLED);
757 iflib_admin_intr_deferred(
ctx);
759 ifmr->ifm_status = IFM_AVALID;
760 ifmr->ifm_active = IFM_ETHER;
765 ifmr->ifm_status |= IFM_ACTIVE;
769 ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
772 ifmr->ifm_active |= IFM_10G_T | IFM_FDX;
775 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
778 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
793 struct ifmedia *ifm = iflib_get_media(ctx);
797 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
800 switch (IFM_SUBTYPE(ifm->ifm_media)) {
804 device_printf(sc->
dev,
"Only auto media type\n");
849 struct ifmultiaddr *ifma;
850 if_t ifp = iflib_get_ifp(ctx);
855 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
856 if (ifma->ifma_addr->sa_family != AF_LINK)
858 bcopy(LLADDR((
struct sockaddr_dl *)ifma->ifma_addr),
880 u8 *addr = *update_ptr;
886 *update_ptr = newptr;
904 iflib_admin_intr_deferred(ctx);
918 device_t
dev = iflib_get_dev(
ctx);
929 iflib_get_ifp(
ctx)->if_init(
ctx);
935 device_printf(
dev,
"Link is up %d Gbps %s \n",
939 iflib_link_state_change(
ctx, LINK_STATE_UP,
945 device_printf(
dev,
"Link is Down\n");
946 iflib_link_state_change(
ctx, LINK_STATE_DOWN, 0);
992 device_t
dev = iflib_get_dev(
ctx);
1020 device_printf(dev,
"unknown mac type\n");
1033 device_t
dev = iflib_get_dev(
ctx);
1036 int error, rid, vector = 0;
1039 for (
int i = 0; i <
sc->num_rx_queues; i++, vector++, rx_que++) {
1042 snprintf(buf,
sizeof(buf),
"rxq%d", i);
1043 error = iflib_irq_alloc_generic(ctx, &rx_que->
que_irq, rid,
1047 device_printf(iflib_get_dev(ctx),
1048 "Failed to allocate que int %d err: %d", i, error);
1049 sc->num_rx_queues = i + 1;
1053 rx_que->
msix = vector;
1056 for (
int i = 0; i <
sc->num_tx_queues; i++) {
1057 snprintf(buf,
sizeof(buf),
"txq%d", i);
1059 tx_que->
msix = i %
sc->num_rx_queues;
1060 iflib_softirq_alloc_generic(ctx,
1062 IFLIB_INTR_TX, tx_que, tx_que->
txr.
me, buf);
1065 error = iflib_irq_alloc_generic(ctx, &
sc->
irq, rid,
1068 device_printf(iflib_get_dev(ctx),
1069 "Failed to register admin handler");
1083 pci_find_cap(dev, PCIY_MSIX, &rid);
1084 rid += PCIR_MSIX_CTRL;
1085 msix_ctrl = pci_read_config(dev, rid, 2);
1086 msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1087 pci_write_config(dev, rid, msix_ctrl, 2);
1093 iflib_irq_free(ctx, &
sc->
irq);
1095 for (
int i = 0; i <
sc->num_rx_queues; i++, rx_que++)
1096 iflib_irq_free(ctx, &rx_que->
que_irq);
1108 device_t
dev = iflib_get_dev(
ctx);
1112 sc->
pci_mem = bus_alloc_resource_any(
dev, SYS_RES_MEMORY, &rid,
1116 device_printf(
dev,
"Unable to allocate bus resource: memory\n");
1122 rman_get_bushandle(sc->
pci_mem);
1136 device_t dev = iflib_get_dev(ctx);
1139 if (
sc->intr_type == IFLIB_INTR_MSIX)
1140 iflib_irq_free(ctx, &
sc->
irq);
1143 for (
int i = 0; i <
sc->num_rx_queues; i++, que++) {
1144 iflib_irq_free(ctx, &que->
que_irq);
1149 bus_release_resource(dev, SYS_RES_MEMORY,
1162 if_softc_ctx_t scctx = sc->
shared;
1163 struct ifnet *ifp = iflib_get_ifp(ctx);
1167 if_setbaudrate(ifp, IF_Gbps(10));
1168 ifp->if_snd.ifq_maxlen = scctx->isc_ntxd[0] - 2;
1172 ifmedia_add(sc->
media, IFM_ETHER | IFM_AUTO, 0, NULL);
1173 ifmedia_set(sc->
media, IFM_ETHER | IFM_AUTO);
1185 if_t
ifp = iflib_get_ifp(
ctx);
1188 case IFCOUNTER_IPACKETS:
1190 case IFCOUNTER_OPACKETS:
1192 case IFCOUNTER_IBYTES:
1194 case IFCOUNTER_OBYTES:
1196 case IFCOUNTER_IMCASTS:
1199 return (if_get_counter_default(
ifp, cnt));
1215 case IFLIB_RESTART_VLAN_CONFIG:
1230 if_softc_ctx_t scctx = sc->
shared;
1234 for (i = 0; i <
sc->num_tx_queues; i++, que++) {
1242 txdctl |= (8 << 16);
1259 for (
int k = 0; k < scctx->isc_ntxd[0]; k++)
1260 txr->
tx_rsq[k] = QIDX_INVALID;
1264 (tdba & 0x00000000ffffffffULL));
1269 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
1288 u32 reta = 0, mrqc, rss_key[10];
1291 u32 rss_hash_config;
1298 arc4rand(&rss_key,
sizeof(rss_key), 0);
1302 for (i = 0; i < 10; i++)
1306 for (i = 0, j = 0; i < 64; i++, j++) {
1307 if (j == sc->num_rx_queues)
1317 queue_id = queue_id % sc->num_rx_queues;
1326 reta |= ((uint32_t)queue_id) << 24;
1358 device_printf(sc->
dev,
"%s: RSS_HASHTYPE_RSS_IPV6_EX defined, but not supported\n",
1361 device_printf(sc->
dev,
"%s: RSS_HASHTYPE_RSS_TCP_IPV6_EX defined, but not supported\n",
1368 device_printf(sc->
dev,
"%s: RSS_HASHTYPE_RSS_UDP_IPV6_EX defined, but not supported\n",
1381 if_softc_ctx_t scctx;
1383 struct ifnet *ifp = iflib_get_ifp(ctx);
1387 if (ifp->if_mtu > ETHERMTU)
1398 if (
sc->num_rx_queues > 1)
1405 device_printf(
sc->
dev,
"There is a problem with the PF setup. It is likely the receive unit for this VF will not function correctly.\n");
1409 for (
int i = 0; i <
sc->num_rx_queues; i++, que++) {
1417 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
1419 for (
int k = 0; k < 10; k++) {
1429 (rdba & 0x00000000ffffffffULL));
1440 reg &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1441 reg &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1452 for (
int l = 0; l < 10; l++) {
1478 if (ifp->if_capenable & IFCAP_NETMAP) {
1479 struct netmap_adapter *na = NA(ifp);
1480 struct netmap_kring *kring = na->rx_rings[j];
1481 int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring);
1487 scctx->isc_nrxd[0] - 1);
1504 struct ifnet *ifp = iflib_get_ifp(ctx);
1507 u32 ctrl, vid, vfta, retry;
1518 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1520 for (
int i = 0; i < sc->num_rx_queues; i++) {
1536 if ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0)
1552 for (
int j = 0; j < 32; j++) {
1554 if ((vfta & (1 << j)) == 0)
1580 index = (vtag >> 5) & 0x7F;
1598 index = (vtag >> 5) & 0x7F;
1621 for (
int i = 0; i <
sc->num_rx_queues; i++, que++)
1675 index = (16 * (entry & 1)) + (8 * type);
1677 ivar &= ~(0xFF << index);
1678 ivar |= (vector << index);
1691 MPASS(
sc->num_rx_queues ==
sc->num_tx_queues);
1693 for (
int i = 0; i <
sc->num_rx_queues; i++, que++) {
1759#define UPDATE_STAT_32(reg, last, count) \
1761 u32 current = IXGBE_READ_REG(hw, reg); \
1762 if (current < last) \
1763 count += 0x100000000LL; \
1765 count &= 0xFFFFFFFF00000000LL; \
1769#define UPDATE_STAT_36(lsb, msb, last, count) \
1771 u64 cur_lsb = IXGBE_READ_REG(hw, lsb); \
1772 u64 cur_msb = IXGBE_READ_REG(hw, msb); \
1773 u64 current = ((cur_msb << 32) | cur_lsb); \
1774 if (current < last) \
1775 count += 0x1000000000LL; \
1777 count &= 0xFFFFFFF000000000LL; \
1815 device_t dev = sc->
dev;
1818 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
1819 struct sysctl_oid *tree = device_get_sysctl_tree(dev);
1820 struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
1822 struct sysctl_oid *stat_node, *queue_node;
1823 struct sysctl_oid_list *stat_list, *queue_list;
1825#define QUEUE_NAME_LEN 32
1829 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO,
"watchdog_events",
1831 SYSCTL_ADD_ULONG(ctx, child, OID_AUTO,
"link_irq",
1832 CTLFLAG_RD, &sc->
link_irq,
"Link MSI-X IRQ Handled");
1834 for (
int i = 0; i < sc->num_tx_queues; i++, tx_que++) {
1837 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
1838 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
"Queue Name");
1839 queue_list = SYSCTL_CHILDREN(queue_node);
1841 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO,
"tso_tx",
1842 CTLFLAG_RD, &(txr->
tso_tx),
"TSO Packets");
1843 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO,
"tx_packets",
1847 for (
int i = 0; i <
sc->num_rx_queues; i++, rx_que++) {
1850 queue_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, namebuf,
1851 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
"Queue Name");
1852 queue_list = SYSCTL_CHILDREN(queue_node);
1854 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO,
"irqs",
1855 CTLFLAG_RD, &(rx_que->
irqs),
"IRQs on queue");
1856 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO,
"rx_packets",
1857 CTLFLAG_RD, &(rxr->
rx_packets),
"RX packets");
1858 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO,
"rx_bytes",
1859 CTLFLAG_RD, &(rxr->
rx_bytes),
"RX bytes");
1860 SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO,
"rx_discarded",
1861 CTLFLAG_RD, &(rxr->
rx_discarded),
"Discarded RX packets");
1864 stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO,
"mac",
1865 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1866 "VF Statistics (read from HW registers)");
1867 stat_list = SYSCTL_CHILDREN(stat_node);
1869 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO,
"good_pkts_rcvd",
1870 CTLFLAG_RD, &stats->
vfgprc,
"Good Packets Received");
1871 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO,
"good_octets_rcvd",
1872 CTLFLAG_RD, &stats->
vfgorc,
"Good Octets Received");
1873 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO,
"mcast_pkts_rcvd",
1874 CTLFLAG_RD, &stats->
vfmprc,
"Multicast Packets Received");
1875 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO,
"good_pkts_txd",
1876 CTLFLAG_RD, &stats->
vfgptc,
"Good Packets Transmitted");
1877 SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO,
"good_octets_txd",
1878 CTLFLAG_RD, &stats->
vfgotc,
"Good Octets Transmitted");
1891 device_t dev =
sc->
dev;
1894 device_printf(dev,
"Error Byte Count = %u \n",
1897 device_printf(dev,
"MBX IRQ Handled: %lu\n", (
long)sc->
link_irq);
1910 error = sysctl_handle_int(oidp, &result, 0, req);
1912 if (error || !req->newptr)
static void ixv_if_update_admin_status(if_ctx_t)
static void ixv_free_pci_resources(if_ctx_t)
static int ixv_setup_interface(if_ctx_t)
static int ixv_msix_que(void *)
static int ixv_if_attach_pre(if_ctx_t)
static int ixv_flow_control
static void ixv_initialize_rss_mapping(struct ixgbe_softc *)
static void ixv_update_stats(struct ixgbe_softc *)
static void ixv_print_debug_info(struct ixgbe_softc *sc)
static int ixv_msix_mbx(void *)
static void ixv_setup_vlan_support(if_ctx_t)
#define UPDATE_STAT_36(lsb, msb, last, count)
static int ixv_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int)
static int ixv_sysctl_debug(SYSCTL_HANDLER_ARGS)
static int ixv_negotiate_api(struct ixgbe_softc *)
static void ixv_if_enable_intr(if_ctx_t)
static device_method_t ixv_if_methods[]
static void ixv_initialize_receive_units(if_ctx_t)
static int ixv_if_msix_intr_assign(if_ctx_t, int)
#define UPDATE_STAT_32(reg, last, count)
static void ixv_init_device_features(struct ixgbe_softc *)
static void ixv_init_stats(struct ixgbe_softc *)
static struct if_shared_ctx ixv_sctx_init
static int ixv_if_detach(if_ctx_t)
static void ixv_if_disable_intr(if_ctx_t)
char ixv_driver_version[]
static void ixv_if_queues_free(if_ctx_t)
static uint64_t ixv_if_get_counter(if_ctx_t, ift_counter)
static int ixv_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int)
MODULE_DEPEND(ixv, iflib, 1, 1, 1)
static int ixv_if_mtu_set(if_ctx_t, uint32_t)
static void ixv_set_ivar(struct ixgbe_softc *, u8, u8, s8)
static pci_vendor_info_t ixv_vendor_info_array[]
static int ixv_if_media_change(if_ctx_t)
IFLIB_PNP_INFO(pci, ixv_driver, ixv_vendor_info_array)
static void ixv_disable_queue(struct ixgbe_softc *sc, u32 vector)
TUNABLE_INT("hw.ixv.flow_control", &ixv_flow_control)
static int ixv_if_rx_queue_intr_enable(if_ctx_t, uint16_t)
static driver_t ixv_driver
static void ixv_if_register_vlan(if_ctx_t, u16)
static int ixv_if_attach_post(if_ctx_t)
DRIVER_MODULE(ixv, pci, ixv_driver, ixv_devclass, 0, 0)
static void ixv_configure_ivars(struct ixgbe_softc *)
static void ixv_if_multi_set(if_ctx_t)
static void * ixv_register(device_t)
static int ixv_header_split
static void ixv_save_stats(struct ixgbe_softc *)
static void ixv_if_media_status(if_ctx_t, struct ifmediareq *)
static bool ixv_if_needs_restart(if_ctx_t, enum iflib_restart_event)
static void ixv_enable_queue(struct ixgbe_softc *sc, u32 vector)
static int ixv_allocate_pci_resources(if_ctx_t)
static void ixv_identify_hardware(if_ctx_t)
struct if_txrx ixgbe_txrx
static void ixv_if_unregister_vlan(if_ctx_t, u16)
static void ixv_if_stop(if_ctx_t)
static void ixv_if_init(if_ctx_t)
static void ixv_add_stats_sysctls(struct ixgbe_softc *)
static void ixv_if_local_timer(if_ctx_t, uint16_t)
static u32 ixv_shadow_vfta[IXGBE_VFTA_SIZE]
static void ixv_initialize_transmit_units(if_ctx_t)
static device_method_t ixv_methods[]
static driver_t ixv_if_driver
static u8 * ixv_mc_array_itr(struct ixgbe_hw *, u8 **, u32 *)
#define IXGBE_MAX_FRAME_SIZE
#define IXGBE_SET_OBYTES(sc, count)
#define IXGBE_SET_IMCASTS(sc, count)
#define IXGBE_SET_IBYTES(sc, count)
#define IXGBE_EITR_DEFAULT
#define IOCTL_DEBUGOUT(S)
#define MAX_NUM_MULTICAST_ADDRESSES
#define IXGBE_82599_SCATTER
#define IXGBE_SET_OPACKETS(sc, count)
#define IXGBE_SET_IPACKETS(sc, count)
static bool ixv_check_ether_addr(u8 *addr)
s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete)
s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw)
#define IXGBE_FEATURE_LEGACY_TX
#define IXGBE_FEATURE_NETMAP
#define IXGBE_FEATURE_NEEDS_CTXD
#define IXGBE_FEATURE_RSS
void ixgbe_init_mbx_params_vf(struct ixgbe_hw *hw)
#define IXGBE_READ_REG(a, reg)
#define IXGBE_INTEL_VENDOR_ID
#define IXGBE_WRITE_FLUSH(a)
#define IXGBE_WRITE_REG(a, reg, val)
#define IXGBE_RXDCTL_ENABLE
#define IXGBE_DEV_ID_X550EM_A_VF
#define IXGBE_DEV_ID_X540_VF
#define IXGBE_EICS_RTX_QUEUE
#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP
#define IXGBE_ETH_LENGTH_OF_ADDRESS
#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP
#define IXGBE_IVAR_ALLOC_VAL
#define IXGBE_DEV_ID_82599_VF
#define IXGBE_PSRTYPE_UDPHDR
#define IXGBE_MRQC_RSS_FIELD_IPV4
#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
#define IXGBE_PSRTYPE_L2HDR
#define IXGBE_LINK_SPEED_10_FULL
#define IXGBE_TXDCTL_ENABLE
#define IXGBE_PSRTYPE_IPV4HDR
#define IXGBE_DEV_ID_X550_VF
#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP
#define IXGBE_LINK_SPEED_100_FULL
#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP
#define IXGBE_LINK_SPEED_1GB_FULL
#define IXGBE_PSRTYPE_TCPHDR
#define IXGBE_DEV_ID_X550EM_X_VF
#define IXGBE_EIMS_RTX_QUEUE
#define IXGBE_SRRCTL_BSIZEPKT_SHIFT
#define IXGBE_LINK_SPEED_10GB_FULL
#define IXGBE_EIMS_ENABLE_MASK
#define IXGBE_PSRTYPE_IPV6HDR
#define IXGBE_MRQC_RSS_FIELD_IPV6
#define IXGBE_ERR_RESET_FAILED
int ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api)
s32 ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size)
#define IXGBE_VFTXDCTL(x)
#define IXGBE_VFSRRCTL(x)
#define IXGBE_VFDCA_TXCTRL(x)
#define IXGBE_VFRXDCTL(x)
#define IXGBE_VTIVAR_MISC
struct ixgbe_mac_info mac
u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]
u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]
struct ixgbe_mac_operations ops
s32(* reset_hw)(struct ixgbe_hw *)
s32(* init_hw)(struct ixgbe_hw *)
s32(* set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32)
s32(* check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool)
s32(* set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool)
s32(* get_link_state)(struct ixgbe_hw *hw, bool *link_state)
s32(* update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, ixgbe_mc_addr_itr, bool clear)
s32(* start_hw)(struct ixgbe_hw *)
s32(* stop_adapter)(struct ixgbe_hw *)
bus_space_tag_t mem_bus_space_tag
bus_space_handle_t mem_bus_space_handle
union ixgbe_softc::@0 stats
struct resource * pci_mem
struct ix_tx_queue * tx_queues
struct ix_rx_queue * rx_queues
struct ixgbevf_hw_stats vf
unsigned long watchdog_events
union ixgbe_adv_rx_desc * rx_base
union ixgbe_adv_tx_desc * tx_base