This graph shows which files directly or indirectly include this file:

Data Structures
struct	iwm_tlv_calib_ctrl

struct	iwm_fw_cipher_scheme

struct	iwm_fw_cscheme_list

struct	iwm_ucode_header

struct	iwm_ucode_tlv

struct	iwm_ucode_api

struct	iwm_ucode_capa

struct	iwm_tlv_ucode_header

struct	iwm_rb_status

struct	iwm_tfd_tb

struct	iwm_tfd

struct	iwm_agn_scd_bc_tbl

struct	iwm_dqa_enable_cmd

struct	iwm_cmd_response

struct	iwm_tx_ant_cfg_cmd

struct	iwm_reduce_tx_power_cmd

struct	iwm_calib_ctrl

struct	iwm_phy_cfg_cmd

struct	iwm_ct_kill_notif

struct	iwm_temp_report_ths_cmd

struct	iwm_phy_db_cmd

struct	iwm_phy_db_chg_txp

struct	iwm_calib_res_notif_phy_db

struct	iwm_nvm_access_cmd

struct	iwm_fw_paging_cmd

struct	iwm_nvm_access_resp

struct	iwm_lmac_alive

struct	iwm_umac_alive

struct	iwm_alive_resp_v3

struct	iwm_alive_resp

struct	iwm_soc_configuration_cmd

struct	iwm_error_resp

struct	iwm_fw_cmd_version

struct	iwm_time_event_cmd

struct	iwm_time_event_resp

struct	iwm_time_event_notif

struct	iwm_binding_cmd_v1

struct	iwm_binding_cmd

struct	iwm_time_quota_data_v1

struct	iwm_time_quota_cmd_v1

struct	iwm_time_quota_data

struct	iwm_time_quota_cmd

struct	iwm_fw_channel_info_v1

struct	iwm_fw_channel_info

struct	iwm_phy_context_cmd_uhb

struct	iwm_phy_context_cmd

struct	iwm_rx_phy_info

struct	iwm_rx_mpdu_res_start

struct	iwm_rx_mpdu_desc_v1

struct	iwm_rx_mpdu_desc

struct	iwm_radio_version_notif

struct	iwm_card_state_notif

struct	iwm_missed_beacons_notif

struct	iwm_mfuart_load_notif

struct	iwm_set_calib_default_cmd

struct	iwm_mcast_filter_cmd

struct	iwm_statistics_dbg

struct	iwm_statistics_div

struct	iwm_statistics_general_common

struct	iwm_statistics_rx_non_phy

struct	iwm_statistics_rx_phy

struct	iwm_statistics_rx_ht_phy

struct	iwm_statistics_tx_non_phy_agg

struct	iwm_statistics_tx_channel_width

struct	iwm_statistics_tx

struct	iwm_statistics_bt_activity

struct	iwm_statistics_general

struct	iwm_statistics_rx

struct	iwm_notif_statistics

struct	iwm_sf_cfg_cmd

struct	iwm_mac_data_ap

struct	iwm_mac_data_ibss

struct	iwm_mac_data_sta

struct	iwm_mac_data_go

struct	iwm_mac_data_p2p_sta

struct	iwm_mac_data_pibss

struct	iwm_mac_data_p2p_dev

struct	iwm_ac_qos

struct	iwm_mac_ctx_cmd

struct	iwm_nonqos_seq_query_cmd

struct	iwm_ltr_config_cmd_v1

struct	iwm_ltr_config_cmd

struct	iwm_device_power_cmd

struct	iwm_mac_power_cmd

struct	iwm_uapsd_misbehaving_ap_notif

struct	iwm_beacon_filter_cmd

struct	iwm_lq_cmd

struct	iwm_tx_cmd

struct	iwm_agg_tx_status

struct	iwm_tx_resp

struct	iwm_ba_notif

struct	iwm_mac_beacon_cmd

struct	iwm_beacon_notif

struct	iwm_tx_path_flush_cmd_v1

struct	iwm_tx_path_flush_cmd

struct	iwm_scd_txq_cfg_cmd

struct	iwm_scd_txq_cfg_rsp

struct	iwm_ssid_ie

struct	iwm_scan_schedule_lmac

struct	iwm_scan_req_tx_cmd

struct	iwm_scan_channel_cfg_lmac

struct	iwm_scan_probe_segment

struct	iwm_scan_probe_req_v1

struct	iwm_scan_probe_req

struct	iwm_scan_channel_opt

struct	iwm_scan_req_lmac

struct	iwm_periodic_scan_complete

struct	iwm_scan_results_notif

struct	iwm_scan_offload_blacklist

struct	iwm_scan_offload_profile

struct	iwm_scan_offload_profile_cfg

struct	iwm_lmac_scan_complete_notif

struct	iwm_scan_config

struct	iwm_scan_channel_cfg_umac

struct	iwm_scan_umac_schedule

struct	iwm_scan_req_umac_tail_v1

struct	iwm_scan_req_umac_tail_v2

struct	iwm_scan_umac_chan_param

struct	iwm_scan_req_umac

struct	iwm_umac_scan_abort

struct	iwm_umac_scan_complete

struct	iwm_scan_offload_profile_match

struct	iwm_scan_offload_profiles_query

struct	iwm_umac_scan_iter_complete_notif

struct	iwm_keyinfo

struct	iwm_add_sta_cmd_v7

struct	iwm_add_sta_cmd

struct	iwm_add_sta_key_common

struct	iwm_add_sta_key_cmd_v1

struct	iwm_add_sta_key_cmd

struct	iwm_rm_sta_cmd

struct	iwm_mgmt_mcast_key_cmd

struct	iwm_wep_key

struct	iwm_wep_key_cmd

struct	iwm_bt_coex_cmd

struct	iwm_mcc_update_cmd_v1

struct	iwm_mcc_update_cmd

struct	iwm_mcc_update_resp_v1

struct	iwm_mcc_update_resp_v2

struct	iwm_mcc_update_resp_v3

struct	iwm_mcc_chub_notif

struct	iwm_dts_measurement_notif_v1

struct	iwm_dts_measurement_notif_v2

struct	iwm_cmd_header

struct	iwm_cmd_header_wide

struct	iwm_device_cmd

struct	iwm_rx_packet

Macros
#define	le16_to_cpup(_a_) (le16toh((const uint16_t )(_a_)))

#define	le32_to_cpup(_a_) (le32toh((const uint32_t )(_a_)))

#define	IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */

#define	IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */

#define	IWM_CSR_INT (0x008) /* host interrupt status/ack */

#define	IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */

#define	IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/

#define	IWM_CSR_GPIO_IN (0x018) /* read external chip pins */

#define	IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/

#define	IWM_CSR_GP_CNTRL (0x024)

#define	IWM_CSR_INT_PERIODIC_REG (0x005)

#define	IWM_CSR_HW_REV (0x028)

#define	IWM_CSR_EEPROM_REG (0x02c)

#define	IWM_CSR_EEPROM_GP (0x030)

#define	IWM_CSR_OTP_GP_REG (0x034)

#define	IWM_CSR_GIO_REG (0x03C)

#define	IWM_CSR_GP_UCODE_REG (0x048)

#define	IWM_CSR_GP_DRIVER_REG (0x050)

#define	IWM_CSR_UCODE_DRV_GP1 (0x054)

#define	IWM_CSR_UCODE_DRV_GP1_SET (0x058)

#define	IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)

#define	IWM_CSR_UCODE_DRV_GP2 (0x060)

#define	IWM_CSR_MBOX_SET_REG (0x088)

#define	IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20

#define	IWM_CSR_LED_REG (0x094)

#define	IWM_CSR_DRAM_INT_TBL_REG (0x0A0)

#define	IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */

#define	IWM_CSR_GIO_CHICKEN_BITS (0x100)

#define	IWM_CSR_ANA_PLL_CFG (0x20c)

#define	IWM_CSR_HW_REV_WA_REG (0x22C)

#define	IWM_CSR_DBG_HPET_MEM_REG (0x240)

#define	IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)

#define	IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)

#define	IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)

#define	IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)

#define	IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)

#define	IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)

#define	IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)

#define	IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)

#define	IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)

#define	IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)

#define	IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)

#define	IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)

#define	IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)

#define	IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)

#define	IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)

#define	IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)

#define	IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)

#define	IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */

#define	IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */

#define	IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */

#define	IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)

#define	IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */

#define	IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/

#define	IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 25532 usec ~ 8 msec/

#define	IWM_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */

#define	IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */

#define	IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */

#define	IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */

#define	IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */

#define	IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */

#define	IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */

#define	IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */

#define	IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */

#define	IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */

#define	IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */

#define	IWM_CSR_INI_SET_MASK

#define	IWM_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */

#define	IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */

#define	IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */

#define	IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */

#define	IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */

#define	IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */

#define	IWM_CSR_FH_INT_RX_MASK

#define	IWM_CSR_FH_INT_TX_MASK

#define	IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)

#define	IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)

#define	IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)

#define	IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)

#define	IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)

#define	IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)

#define	IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)

#define	IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)

#define	IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)

#define	IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)

#define	IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)

#define	IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)

#define	IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)

#define	IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)

#define	IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)

#define	IWM_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)

#define	IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)

#define	IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)

#define	IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)

#define	IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)

#define	IWM_CSR_HW_REV_TYPE_5300 (0x0000020)

#define	IWM_CSR_HW_REV_TYPE_5350 (0x0000030)

#define	IWM_CSR_HW_REV_TYPE_5100 (0x0000050)

#define	IWM_CSR_HW_REV_TYPE_5150 (0x0000040)

#define	IWM_CSR_HW_REV_TYPE_1000 (0x0000060)

#define	IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)

#define	IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)

#define	IWM_CSR_HW_REV_TYPE_6150 (0x0000084)

#define	IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)

#define	IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05

#define	IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05

#define	IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)

#define	IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)

#define	IWM_CSR_HW_REV_TYPE_105 (0x0000110)

#define	IWM_CSR_HW_REV_TYPE_135 (0x0000120)

#define	IWM_CSR_HW_REV_TYPE_7265D (0x0000210)

#define	IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)

#define	IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)

#define	IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)

#define	IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)

#define	IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)

#define	IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */

#define	IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)

#define	IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)

#define	IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)

#define	IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)

#define	IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)

#define	IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */

#define	IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */

#define	IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */

#define	IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */

#define	IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */

#define	IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)

#define	IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)

#define	IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)

#define	IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)

#define	IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)

#define	IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)

#define	IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)

#define	IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)

#define	IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)

#define	IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)

#define	IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)

#define	IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)

#define	IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)

#define	IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)

#define	IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)

#define	IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)

#define	IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)

#define	IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)

#define	IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)

#define	IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)

#define	IWM_CSR_LED_REG_TURN_ON (0x60)

#define	IWM_CSR_LED_REG_TURN_OFF (0x20)

#define	IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)

#define	IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)

#define	IWM_CSR_DRAM_INT_TBL_ENABLE (1U << 31)

#define	IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)

#define	IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)

#define	IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)

#define	IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP 0x00000001

#define	IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ 0x00000002

#define	IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)

#define	IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)

#define	IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS 0x00000003

#define	IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED 0x00000002

#define	IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS 0x00000004

#define	IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL 0x00000008

#define	IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL 0x00000010

#define	IWM_FH_UCODE_LOAD_STATUS 0x1af0

#define	IWM_FH_MEM_TB_MAX_LENGTH 0x20000

#define	IWM_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */

#define	IWM_RFH_Q_FRBDCB_BA_LSB(q) (IWM_RFH_Q0_FRBDCB_BA_LSB + (q) * 8)

#define	IWM_RFH_Q0_FRBDCB_WIDX 0xA08080

#define	IWM_RFH_Q_FRBDCB_WIDX(q) (IWM_RFH_Q0_FRBDCB_WIDX + (q) * 4)

#define	IWM_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80

#define	IWM_RFH_Q_FRBDCB_WIDX_TRG(q) (IWM_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4)

#define	IWM_RFH_Q0_FRBDCB_RIDX 0xA080C0

#define	IWM_RFH_Q_FRBDCB_RIDX(q) (IWM_RFH_Q0_FRBDCB_RIDX + (q) * 4)

#define	IWM_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */

#define	IWM_RFH_Q_URBDCB_BA_LSB(q) (IWM_RFH_Q0_URBDCB_BA_LSB + (q) * 8)

#define	IWM_RFH_Q0_URBDCB_WIDX 0xA08180

#define	IWM_RFH_Q_URBDCB_WIDX(q) (IWM_RFH_Q0_URBDCB_WIDX + (q) * 4)

#define	IWM_RFH_Q0_URBDCB_VAID 0xA081C0

#define	IWM_RFH_Q_URBDCB_VAID(q) (IWM_RFH_Q0_URBDCB_VAID + (q) * 4)

#define	IWM_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /64 bits address /

#define	IWM_RFH_Q_URBD_STTS_WPTR_LSB(q) (IWM_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)

#define	IWM_RFH_Q0_ORB_WPTR_LSB 0xA08280

#define	IWM_RFH_Q_ORB_WPTR_LSB(q) (IWM_RFH_Q0_ORB_WPTR_LSB + (q) * 8)

#define	IWM_RFH_RBDBUF_RBD0_LSB 0xA08300

#define	IWM_RFH_RBDBUF_RBD_LSB(q) (IWM_RFH_RBDBUF_RBD0_LSB + (q) * 8)

#define	IWM_RFH_GEN_STATUS 0xA09808

#define	IWM_RFH_GEN_STATUS_GEN3 0xA07824

#define	IWM_RBD_FETCH_IDLE (1 << 29)

#define	IWM_SRAM_DMA_IDLE (1 << 30)

#define	IWM_RXF_DMA_IDLE (1U << 31)

#define	IWM_RFH_RXF_DMA_CFG 0xA09820

#define	IWM_RFH_RXF_DMA_CFG_GEN3 0xA07880

#define	IWM_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */

#define	IWM_RFH_RXF_DMA_RB_SIZE_POS 16

#define	IWM_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWM_RFH_RXF_DMA_RB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWM_RFH_RXF_DMA_RB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWM_RFH_RXF_DMA_RB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWM_RFH_RXF_DMA_RB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWM_RFH_RXF_DMA_RB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWM_RFH_RXF_DMA_RB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWM_RFH_RXF_DMA_RB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWM_RFH_RXF_DMA_RB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWM_RFH_RXF_DMA_RB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWM_RFH_RXF_DMA_RB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */

#define	IWM_RFH_RXF_DMA_RBDCB_SIZE_POS 20

#define	IWM_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */

#define	IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS 24

#define	IWM_RFH_RXF_DMA_MIN_RB_4_8 (3 << IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS)

#define	IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */

#define	IWM_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */

#define	IWM_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/

#define	IWM_RFH_DMA_EN_ENABLE_VAL (1U << 31)

#define	IWM_RFH_RXF_RXQ_ACTIVE 0xA0980C

#define	IWM_RFH_GEN_CFG 0xA09800

#define	IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0)

#define	IWM_RFH_GEN_CFG_RFH_DMA_SNOOP (1 << 1)

#define	IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010

#define	IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000

#define	IWM_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00

#define	IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78

#define	IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c

#define	IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000

#define	IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400

#define	IWM_CSR_SECURE_TIME_OUT (100)

#define	IWM_FW_MEM_EXTENDED_START 0x40000

#define	IWM_FW_MEM_EXTENDED_END 0x57FFF

#define	IWM_LMPM_CHICK 0xa01ff8

#define	IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01

#define	IWM_FH_TCSR_0_REG0 (0x1D00)

#define	IWM_HBUS_BASE (0x400)

#define	IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)

#define	IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)

#define	IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)

#define	IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)

#define	IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)

#define	IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)

#define	IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)

#define	IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)

#define	IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)

#define	IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)

#define	IWM_WFPM_PS_CTL_CLR 0xa0300c

#define	IWM_WFMP_MAC_ADDR_0 0xa03080

#define	IWM_WFMP_MAC_ADDR_1 0xa03084

#define	IWM_LMPM_PMG_EN 0xa01cec

#define	IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078

#define	IWM_RFIC_REG_RD 0xad0470

#define	IWM_WFPM_CTRL_REG 0xa03030

#define	IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000

#define	IWM_ENABLE_WFPM 0x80000000

#define	IWM_AUX_MISC_REG 0xa200b0

#define	IWM_HW_STEP_LOCATION_BITS 24

#define	IWM_AUX_MISC_MASTER1_EN 0xa20818

#define	IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1

#define	IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800

#define	IWM_RSA_ENABLE 0xa24b08

#define	IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0

#define	IWM_PREG_PRPH_WPROT_9000 0xa04ce0

#define	IWM_PREG_PRPH_WPROT_22000 0xa04d00

#define	IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78

#define	IWM_SB_CFG_OVERRIDE_ENABLE 0x8000

#define	IWM_SB_CFG_BASE_OVERRIDE 0xa20000

#define	IWM_SB_MODIFY_CFG_FLAG 0xa03088

#define	IWM_SB_CPU_1_STATUS 0xa01e30

#define	IWM_SB_CPU_2_STATUS 0Xa01e34

#define	IWM_UREG_CHICK 0xa05c00

#define	IWM_UREG_CHICK_MSI_ENABLE (1 << 24)

#define	IWM_UREG_CHICK_MSIX_ENABLE (1 << 25)

#define	IWM_HPM_DEBUG 0xa03440

#define	IWM_HPM_PERSISTENCE_BIT (1 << 12)

#define	IWM_PREG_WFPM_ACCESS (1 << 12)

#define	IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)

#define	IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)

#define	IWM_HOST_INT_TIMEOUT_MAX (0xFF)

#define	IWM_HOST_INT_TIMEOUT_DEF (0x40)

#define	IWM_HOST_INT_TIMEOUT_MIN (0x0)

#define	IWM_HOST_INT_OPER_MODE (1U << 31)

#define	IWM_DTS_DIODE_REG_DIG_VAL 0x000000FF /* bits [7:0] */

#define	IWM_DTS_DIODE_REG_VREF_LOW 0x0000FF00 /* bits [15:8] */

#define	IWM_DTS_DIODE_REG_VREF_HIGH 0x00FF0000 /* bits [23:16] */

#define	IWM_DTS_DIODE_REG_VREF_ID 0x03000000 /* bits [25:24] */

#define	IWM_DTS_DIODE_REG_PASS_ONCE 0x80000000 /* bits [31:31] */

#define	IWM_DTS_DIODE_REG_FLAGS_MSK 0xFF000000 /* bits [31:24] */

#define	IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS 0

#define	IWM_DTS_DIODE_REG_FLAGS_VREFS_ID 0x00000003 /* bits [1:0] */

#define	IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS 7

#define	IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE 0x00000080 /* bits [7:7] */

#define	IWM_CSR_MSIX_BASE (0x2000)

#define	IWM_CSR_MSIX_FH_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x800)

#define	IWM_CSR_MSIX_FH_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x804)

#define	IWM_CSR_MSIX_HW_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x808)

#define	IWM_CSR_MSIX_HW_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x80C)

#define	IWM_CSR_MSIX_AUTOMASK_ST_AD (IWM_CSR_MSIX_BASE + 0x810)

#define	IWM_CSR_MSIX_RX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x880)

#define	IWM_CSR_MSIX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x890)

#define	IWM_CSR_MSIX_PENDING_PBA_AD (IWM_CSR_MSIX_BASE + 0x1000)

#define	IWM_CSR_MSIX_RX_IVAR(cause) (IWM_CSR_MSIX_RX_IVAR_AD_REG + (cause))

#define	IWM_CSR_MSIX_IVAR(cause) (IWM_CSR_MSIX_IVAR_AD_REG + (cause))

#define	IWM_MSIX_AUTO_CLEAR_CAUSE (0 << 7)

#define	IWM_MSIX_NON_AUTO_CLEAR_CAUSE (1 << 7)

#define	IWM_UCODE_TLV_FLAGS_PAN (1 << 0)

#define	IWM_UCODE_TLV_FLAGS_NEWSCAN (1 << 1)

#define	IWM_UCODE_TLV_FLAGS_MFP (1 << 2)

#define	IWM_UCODE_TLV_FLAGS_P2P (1 << 3)

#define	IWM_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4)

#define	IWM_UCODE_TLV_FLAGS_SHORT_BL (1 << 7)

#define	IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10)

#define	IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12)

#define	IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15)

#define	IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16)

#define	IWM_UCODE_TLV_FLAGS_P2P_PS (1 << 21)

#define	IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22)

#define	IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23)

#define	IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24)

#define	IWM_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25)

#define	IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26)

#define	IWM_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29)

#define	IWM_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30)

#define	IWM_UCODE_TLV_FLAGS_LTE_COEX (1U << 31)

#define	IWM_UCODE_TLV_FLAG_BITS "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"

#define	IWM_UCODE_TLV_API_FRAGMENTED_SCAN 8

#define	IWM_UCODE_TLV_API_WIFI_MCC_UPDATE 9

#define	IWM_UCODE_TLV_API_WIDE_CMD_HDR 14

#define	IWM_UCODE_TLV_API_LQ_SS_PARAMS 18

#define	IWM_UCODE_TLV_API_NEW_VERSION 20

#define	IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY 24

#define	IWM_UCODE_TLV_API_TX_POWER_CHAIN 27

#define	IWM_UCODE_TLV_API_SCAN_TSF_REPORT 28

#define	IWM_UCODE_TLV_API_TKIP_MIC_KEYS 29

#define	IWM_UCODE_TLV_API_STA_TYPE 30

#define	IWM_UCODE_TLV_API_NAN2_VER2 31

#define	IWM_UCODE_TLV_API_ADAPTIVE_DWELL 32

#define	IWM_UCODE_TLV_API_NEW_RX_STATS 35

#define	IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY 38

#define	IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2 42

#define	IWM_UCODE_TLV_API_SCAN_EXT_CHAN_VER 58

#define	IWM_NUM_UCODE_TLV_API 128

#define	IWM_UCODE_TLV_API_BITS "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS"

#define	IWM_UCODE_TLV_CAPA_D0I3_SUPPORT 0

#define	IWM_UCODE_TLV_CAPA_LAR_SUPPORT 1

#define	IWM_UCODE_TLV_CAPA_UMAC_SCAN 2

#define	IWM_UCODE_TLV_CAPA_BEAMFORMER 3

#define	IWM_UCODE_TLV_CAPA_TOF_SUPPORT 5

#define	IWM_UCODE_TLV_CAPA_TDLS_SUPPORT 6

#define	IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8

#define	IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9

#define	IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10

#define	IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11

#define	IWM_UCODE_TLV_CAPA_DQA_SUPPORT 12

#define	IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13

#define	IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17

#define	IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18

#define	IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19

#define	IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20

#define	IWM_UCODE_TLV_CAPA_CSUM_SUPPORT 21

#define	IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22

#define	IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26

#define	IWM_UCODE_TLV_CAPA_BT_COEX_PLCR 28

#define	IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC 29

#define	IWM_UCODE_TLV_CAPA_BT_COEX_RRC 30

#define	IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT 31

#define	IWM_UCODE_TLV_CAPA_NAN_SUPPORT 34

#define	IWM_UCODE_TLV_CAPA_UMAC_UPLOAD 35

#define	IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT 37

#define	IWM_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT 39

#define	IWM_UCODE_TLV_CAPA_CDB_SUPPORT 40

#define	IWM_UCODE_TLV_CAPA_DYNAMIC_QUOTA 44

#define	IWM_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS 48

#define	IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64

#define	IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65

#define	IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67

#define	IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68

#define	IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71

#define	IWM_UCODE_TLV_CAPA_BEACON_STORING 72

#define	IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 73

#define	IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW 74

#define	IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75

#define	IWM_UCODE_TLV_CAPA_CTDP_SUPPORT 76

#define	IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77

#define	IWM_UCODE_TLV_CAPA_LMAC_UPLOAD 79

#define	IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80

#define	IWM_UCODE_TLV_CAPA_LQM_SUPPORT 81

#define	IWM_NUM_UCODE_TLV_CAPA 128

#define	IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18

#define	IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19

#define	IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253

#define	IWM_DEFAULT_MAX_PROBE_LENGTH 200

#define	IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC

#define	IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB

#define	IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)

#define	IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)

#define	IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)

#define	IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)

#define	IWM_FW_PHY_CFG_RADIO_TYPE_POS 0

#define	IWM_FW_PHY_CFG_RADIO_TYPE (0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS)

#define	IWM_FW_PHY_CFG_RADIO_STEP_POS 2

#define	IWM_FW_PHY_CFG_RADIO_STEP (0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS)

#define	IWM_FW_PHY_CFG_RADIO_DASH_POS 4

#define	IWM_FW_PHY_CFG_RADIO_DASH (0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS)

#define	IWM_FW_PHY_CFG_TX_CHAIN_POS 16

#define	IWM_FW_PHY_CFG_TX_CHAIN (0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS)

#define	IWM_FW_PHY_CFG_RX_CHAIN_POS 20

#define	IWM_FW_PHY_CFG_RX_CHAIN (0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS)

#define	IWM_UCODE_MAX_CS 1

#define	IWM_UCODE_TLV_DEBUG_BASE 0x1000005

#define	IWM_UCODE_TLV_TYPE_DEBUG_INFO (IWM_UCODE_TLV_DEBUG_BASE + 0)

#define	IWM_UCODE_TLV_TYPE_BUFFER_ALLOCATION (IWM_UCODE_TLV_DEBUG_BASE + 1)

#define	IWM_UCODE_TLV_TYPE_HCMD (IWM_UCODE_TLV_DEBUG_BASE + 2)

#define	IWM_UCODE_TLV_TYPE_REGIONS (IWM_UCODE_TLV_DEBUG_BASE + 3)

#define	IWM_UCODE_TLV_TYPE_TRIGGERS (IWM_UCODE_TLV_DEBUG_BASE + 4)

#define	IWM_UCODE_TLV_DEBUG_MAX IWM_UCODE_TLV_TYPE_TRIGGERS

#define	IWM_TLV_UCODE_MAGIC 0x0a4c5749

#define	IWM_PRPH_BASE (0x00000)

#define	IWM_PRPH_END (0xFFFFF)

#define	IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)

#define	IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)

#define	IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)

#define	IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)

#define	IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)

#define	IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)

#define	IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)

#define	IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)

#define	IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)

#define	IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)

#define	IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)

#define	IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)

#define	IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)

#define	IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)

#define	IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)

#define	IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)

#define	IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)

#define	IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)

#define	IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)

#define	IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */

#define	IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)

#define	IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)

#define	IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)

#define	IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C

#define	IWM_DEVICE_SET_NMI_REG 0x00a01c30

#define	IWM_DEVICE_SET_NMI_VAL_HW 0x01

#define	IWM_DEVICE_SET_NMI_VAL_DRV 0x80

#define	IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24

#define	IWM_DEVICE_SET_NMI_8000_VAL 0x1000000

#define	IWM_RELEASE_CPU_RESET 0x300c

#define	IWM_RELEASE_CPU_RESET_BIT 0x1000000

#define	IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)

#define	IWM_DTSC_CFG_MODE (0x00a10604)

#define	IWM_DTSC_VREF_AVG (0x00a10648)

#define	IWM_DTSC_VREF5_AVG (0x00a1064c)

#define	IWM_DTSC_CFG_MODE_PERIODIC (0x2)

#define	IWM_DTSC_PTAT_AVG (0x00a10650)

#define	IWM_SCD_MEM_LOWER_BOUND (0x0000)

#define	IWM_SCD_WIN_SIZE 64

#define	IWM_SCD_FRAME_LIMIT 64

#define	IWM_SCD_TXFIFO_POS_TID (0)

#define	IWM_SCD_TXFIFO_POS_RA (4)

#define	IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)

#define	IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)

#define	IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)

#define	IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)

#define	IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)

#define	IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)

#define	IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)

#define	IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)

#define	IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)

#define	IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)

#define	IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)

#define	IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)

#define	IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)

#define	IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)

#define	IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0)

#define	IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18)

#define	IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)

#define	IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)

#define	IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)

#define	IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)

#define	IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)

#define	IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)

#define	IWM_SCD_CONTEXT_QUEUE_OFFSET(x) (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))

#define	IWM_SCD_TX_STTS_QUEUE_OFFSET(x) (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))

#define	IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)

#define	IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)

#define	IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)

#define	IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)

#define	IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)

#define	IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)

#define	IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)

#define	IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)

#define	IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)

#define	IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)

#define	IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)

#define	IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)

#define	IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)

#define	IWM_OSC_CLK (0xa04068)

#define	IWM_OSC_CLK_FORCE_CONTROL (0x8)

#define	IWM_FH_MEM_LOWER_BOUND (0x1000)

#define	IWM_FH_MEM_UPPER_BOUND (0x2000)

#define	IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)

#define	IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)

#define	IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)

#define	IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)

#define	IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)

#define	IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)

#define	IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)

#define	IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)

#define	IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)

#define	IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)

#define	IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)

#define	IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)

#define	IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)

#define	IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)

#define	IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)

#define	IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG

#define	IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)

#define	IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)

#define	IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)

#define	IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)

#define	IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)

#define	IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)

#define	IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */

#define	IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */

#define	IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */

#define	IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */

#define	IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */

#define	IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/

#define	IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)

#define	IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)

#define	IWM_RX_RB_TIMEOUT (0x11)

#define	IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)

#define	IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)

#define	IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)

#define	IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)

#define	IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)

#define	IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)

#define	IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)

#define	IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)

#define	IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)

#define	IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)

#define	IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)

#define	IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)

#define	IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)

#define	IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)

#define	IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)

#define	IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)

#define	IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28

#define	IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)

#define	IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)

#define	IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)

#define	IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))

#define	IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)

#define	IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)

#define	IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)

#define	IWM_FH_TCSR_CHNL_NUM (8)

#define	IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))

#define	IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)

#define	IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)

#define	IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)

#define	IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)

#define	IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)

#define	IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)

#define	IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)

#define	IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)

#define	IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)

#define	IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)

#define	IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)

#define	IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)

#define	IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)

#define	IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)

#define	IWM_FH_SRVC_CHNL (9)

#define	IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)

#define	IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)

#define	IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)

#define	IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)

#define	IWM_FH_TX_TRB_REG(_chan)

#define	IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)

#define	IWM_RX_QUEUE_SIZE 256

#define	IWM_RX_QUEUE_MASK 255

#define	IWM_RX_QUEUE_SIZE_LOG 8

#define	IWM_RX_FREE_BUFFERS 64

#define	IWM_RX_LOW_WATERMARK 8

#define	IWM_TFD_QUEUE_SIZE_MAX (256)

#define	IWM_TFD_QUEUE_SIZE_BC_DUP (64)

#define	IWM_TFD_QUEUE_BC_SIZE

#define	IWM_TX_DMA_MASK DMA_BIT_MASK(36)

#define	IWM_NUM_OF_TBS 20

#define	IWM_KW_SIZE 0x1000 /* 4k */

#define	IWM_TX_CRC_SIZE 4

#define	IWM_TX_DELIMITER_SIZE 4

#define	IWM_MAX_QUEUES 31

#define	IWM_DQA_CMD_QUEUE 0

#define	IWM_DQA_AUX_QUEUE 1

#define	IWM_DQA_P2P_DEVICE_QUEUE 2

#define	IWM_DQA_INJECT_MONITOR_QUEUE 2

#define	IWM_DQA_GCAST_QUEUE 3

#define	IWM_DQA_BSS_CLIENT_QUEUE 4

#define	IWM_DQA_MIN_MGMT_QUEUE 5

#define	IWM_DQA_MAX_MGMT_QUEUE 8

#define	IWM_DQA_AP_PROBE_RESP_QUEUE 9

#define	IWM_DQA_MIN_DATA_QUEUE 10

#define	IWM_DQA_MAX_DATA_QUEUE 31

#define	IWM_MAX_TID_COUNT 8

#define	IWM_FIRST_AGG_TX_QUEUE IWM_DQA_MIN_DATA_QUEUE

#define	IWM_LAST_AGG_TX_QUEUE (IWM_FIRST_AGG_TX_QUEUE + IWM_MAX_TID_COUNT - 1)

#define	IWM_OFFCHANNEL_QUEUE 8

#define	IWM_CMD_QUEUE 9

#define	IWM_AUX_QUEUE 15

#define	IWM_TX_FIFO_BK 0

#define	IWM_TX_FIFO_BE 1

#define	IWM_TX_FIFO_VI 2

#define	IWM_TX_FIFO_VO 3

#define	IWM_TX_FIFO_MCAST 5

#define	IWM_TX_FIFO_CMD 7

#define	IWM_STATION_COUNT 16

#define	IWM_ALIVE 0x1

#define	IWM_REPLY_ERROR 0x2

#define	IWM_INIT_COMPLETE_NOTIF 0x4

#define	IWM_PHY_CONTEXT_CMD 0x8

#define	IWM_DBG_CFG 0x9

#define	IWM_SCAN_ITERATION_COMPLETE_UMAC 0xb5

#define	IWM_SCAN_CFG_CMD 0xc

#define	IWM_SCAN_REQ_UMAC 0xd

#define	IWM_SCAN_ABORT_UMAC 0xe

#define	IWM_SCAN_COMPLETE_UMAC 0xf

#define	IWM_ADD_STA_KEY 0x17

#define	IWM_ADD_STA 0x18

#define	IWM_REMOVE_STA 0x19

#define	IWM_TX_CMD 0x1c

#define	IWM_TXPATH_FLUSH 0x1e

#define	IWM_MGMT_MCAST_KEY 0x1f

#define	IWM_SCD_QUEUE_CFG 0x1d

#define	IWM_WEP_KEY 0x20

#define	IWM_MAC_CONTEXT_CMD 0x28

#define	IWM_TIME_EVENT_CMD 0x29 /* both CMD and response */

#define	IWM_TIME_EVENT_NOTIFICATION 0x2a

#define	IWM_BINDING_CONTEXT_CMD 0x2b

#define	IWM_TIME_QUOTA_CMD 0x2c

#define	IWM_NON_QOS_TX_COUNTER_CMD 0x2d

#define	IWM_LQ_CMD 0x4e

#define	IWM_TEMPERATURE_NOTIFICATION 0x62

#define	IWM_CALIBRATION_CFG_CMD 0x65

#define	IWM_CALIBRATION_RES_NOTIFICATION 0x66

#define	IWM_CALIBRATION_COMPLETE_NOTIFICATION 0x67

#define	IWM_RADIO_VERSION_NOTIFICATION 0x68

#define	IWM_FW_PAGING_BLOCK_CMD 0x4f

#define	IWM_SCAN_OFFLOAD_REQUEST_CMD 0x51

#define	IWM_SCAN_OFFLOAD_ABORT_CMD 0x52

#define	IWM_HOT_SPOT_CMD 0x53

#define	IWM_SCAN_OFFLOAD_COMPLETE 0x6d

#define	IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD 0x6e

#define	IWM_SCAN_OFFLOAD_CONFIG_CMD 0x6f

#define	IWM_MATCH_FOUND_NOTIFICATION 0xd9

#define	IWM_SCAN_ITERATION_COMPLETE 0xe7

#define	IWM_PHY_CONFIGURATION_CMD 0x6a

#define	IWM_CALIB_RES_NOTIF_PHY_DB 0x6b

#define	IWM_PHY_DB_CMD 0x6c

#define	IWM_POWER_TABLE_CMD 0x77

#define	IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78

#define	IWM_LTR_CONFIG 0xee

#define	IWM_REPLY_THERMAL_MNG_BACKOFF 0x7e

#define	IWM_NVM_ACCESS_CMD 0x88

#define	IWM_SET_CALIB_DEFAULT_CMD 0x8e

#define	IWM_BEACON_NOTIFICATION 0x90

#define	IWM_BEACON_TEMPLATE_CMD 0x91

#define	IWM_TX_ANT_CONFIGURATION_CMD 0x98

#define	IWM_BT_CONFIG 0x9b

#define	IWM_STATISTICS_NOTIFICATION 0x9d

#define	IWM_REDUCE_TX_POWER_CMD 0x9f

#define	IWM_CARD_STATE_CMD 0xa0

#define	IWM_CARD_STATE_NOTIFICATION 0xa1

#define	IWM_MISSED_BEACONS_NOTIFICATION 0xa2

#define	IWM_MFUART_LOAD_NOTIFICATION 0xb1

#define	IWM_MAC_PM_POWER_TABLE 0xa9

#define	IWM_REPLY_RX_PHY_CMD 0xc0

#define	IWM_REPLY_RX_MPDU_CMD 0xc1

#define	IWM_BA_NOTIF 0xc5

#define	IWM_MCC_UPDATE_CMD 0xc8

#define	IWM_MCC_CHUB_UPDATE_CMD 0xc9

#define	IWM_BT_COEX_PRIO_TABLE 0xcc

#define	IWM_BT_COEX_PROT_ENV 0xcd

#define	IWM_BT_PROFILE_NOTIFICATION 0xce

#define	IWM_BT_COEX_CI 0x5d

#define	IWM_REPLY_SF_CFG_CMD 0xd1

#define	IWM_REPLY_BEACON_FILTERING_CMD 0xd2

#define	IWM_CMD_DTS_MEASUREMENT_TRIGGER 0xdc

#define	IWM_DTS_MEASUREMENT_NOTIFICATION 0xdd

#define	IWM_REPLY_DEBUG_CMD 0xf0

#define	IWM_DEBUG_LOG_MSG 0xf7

#define	IWM_MCAST_FILTER_CMD 0xd0

#define	IWM_D3_CONFIG_CMD 0xd3

#define	IWM_PROT_OFFLOAD_CONFIG_CMD 0xd4

#define	IWM_OFFLOADS_QUERY_CMD 0xd5

#define	IWM_REMOTE_WAKE_CONFIG_CMD 0xd6

#define	IWM_WOWLAN_PATTERNS 0xe0

#define	IWM_WOWLAN_CONFIGURATION 0xe1

#define	IWM_WOWLAN_TSC_RSC_PARAM 0xe2

#define	IWM_WOWLAN_TKIP_PARAM 0xe3

#define	IWM_WOWLAN_KEK_KCK_MATERIAL 0xe4

#define	IWM_WOWLAN_GET_STATUSES 0xe5

#define	IWM_WOWLAN_TX_POWER_PER_DB 0xe6

#define	IWM_NET_DETECT_CONFIG_CMD 0x54

#define	IWM_NET_DETECT_PROFILES_QUERY_CMD 0x56

#define	IWM_NET_DETECT_PROFILES_CMD 0x57

#define	IWM_NET_DETECT_HOTSPOTS_CMD 0x58

#define	IWM_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59

#define	IWM_FSEQ_VER_MISMATCH_NOTIFICATION 0xff

#define	IWM_REPLY_MAX 0xff

#define	IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE 0x0

#define	IWM_CTDP_CONFIG_CMD 0x03

#define	IWM_TEMP_REPORTING_THRESHOLDS_CMD 0x04

#define	IWM_CT_KILL_NOTIFICATION 0xFE

#define	IWM_DTS_MEASUREMENT_NOTIF_WIDE 0xFF

#define	IWM_LEGACY_GROUP 0x0

#define	IWM_LONG_GROUP 0x1

#define	IWM_SYSTEM_GROUP 0x2

#define	IWM_MAC_CONF_GROUP 0x3

#define	IWM_PHY_OPS_GROUP 0x4

#define	IWM_DATA_PATH_GROUP 0x5

#define	IWM_PROT_OFFLOAD_GROUP 0xb

#define	IWM_SHARED_MEM_CFG_CMD 0x00

#define	IWM_SOC_CONFIGURATION_CMD 0x01

#define	IWM_INIT_EXTENDED_CFG_CMD 0x03

#define	IWM_FW_ERROR_RECOVERY_CMD 0x07

#define	IWM_DQA_ENABLE_CMD 0x00

#define	IWM_CALIB_CFG_XTAL_IDX (1 << 0)

#define	IWM_CALIB_CFG_TEMPERATURE_IDX (1 << 1)

#define	IWM_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2)

#define	IWM_CALIB_CFG_PAPD_IDX (1 << 3)

#define	IWM_CALIB_CFG_TX_PWR_IDX (1 << 4)

#define	IWM_CALIB_CFG_DC_IDX (1 << 5)

#define	IWM_CALIB_CFG_BB_FILTER_IDX (1 << 6)

#define	IWM_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7)

#define	IWM_CALIB_CFG_TX_IQ_IDX (1 << 8)

#define	IWM_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9)

#define	IWM_CALIB_CFG_RX_IQ_IDX (1 << 10)

#define	IWM_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11)

#define	IWM_CALIB_CFG_SENSITIVITY_IDX (1 << 12)

#define	IWM_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13)

#define	IWM_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14)

#define	IWM_CALIB_CFG_ANT_COUPLING_IDX (1 << 15)

#define	IWM_CALIB_CFG_DAC_IDX (1 << 16)

#define	IWM_CALIB_CFG_ABS_IDX (1 << 17)

#define	IWM_CALIB_CFG_AGC_IDX (1 << 18)

#define	IWM_PHY_CFG_RADIO_TYPE ((1 << 0) \| (1 << 1))

#define	IWM_PHY_CFG_RADIO_STEP ((1 << 2) \| (1 << 3))

#define	IWM_PHY_CFG_RADIO_DASH ((1 << 4) \| (1 << 5))

#define	IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) \| (1 << 7))

#define	IWM_PHY_CFG_TX_CHAIN_A (1 << 8)

#define	IWM_PHY_CFG_TX_CHAIN_B (1 << 9)

#define	IWM_PHY_CFG_TX_CHAIN_C (1 << 10)

#define	IWM_PHY_CFG_RX_CHAIN_A (1 << 12)

#define	IWM_PHY_CFG_RX_CHAIN_B (1 << 13)

#define	IWM_PHY_CFG_RX_CHAIN_C (1 << 14)

#define	IWM_MAX_DTS_TRIPS 8

#define	IWM_HW_ADDR 0x15

#define	IWM_NVM_SW_SECTION 0x1C0

#define	IWM_NVM_VERSION 0

#define	IWM_RADIO_CFG 1

#define	IWM_SKU 2

#define	IWM_N_HW_ADDRS 3

#define	IWM_NVM_CHANNELS 0x1E0 - IWM_NVM_SW_SECTION

#define	IWM_NVM_CALIB_SECTION 0x2B8

#define	IWM_XTAL_CALIB (0x316 - IWM_NVM_CALIB_SECTION)

#define	IWM_HW_ADDR0_WFPM_8000 0x12

#define	IWM_HW_ADDR1_WFPM_8000 0x16

#define	IWM_HW_ADDR0_PCIE_8000 0x8A

#define	IWM_HW_ADDR1_PCIE_8000 0x8E

#define	IWM_MAC_ADDRESS_OVERRIDE_8000 1

#define	IWM_NVM_SW_SECTION_8000 0x1C0

#define	IWM_NVM_VERSION_8000 0

#define	IWM_RADIO_CFG_8000 0

#define	IWM_SKU_8000 2

#define	IWM_N_HW_ADDRS_8000 3

#define	IWM_NVM_CHANNELS_8000 0

#define	IWM_NVM_LAR_OFFSET_8000_OLD 0x4C7

#define	IWM_NVM_LAR_OFFSET_8000 0x507

#define	IWM_NVM_LAR_ENABLED_8000 0x7

#define	IWM_NVM_CALIB_SECTION_8000 0x2B8

#define	IWM_XTAL_CALIB_8000 (0x316 - IWM_NVM_CALIB_SECTION_8000)

#define	IWM_NVM_SKU_CAP_BAND_24GHZ (1 << 0)

#define	IWM_NVM_SKU_CAP_BAND_52GHZ (1 << 1)

#define	IWM_NVM_SKU_CAP_11N_ENABLE (1 << 2)

#define	IWM_NVM_SKU_CAP_11AC_ENABLE (1 << 3)

#define	IWM_NVM_SKU_CAP_MIMO_DISABLE (1 << 5)

#define	IWM_NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */

#define	IWM_NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */

#define	IWM_NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */

#define	IWM_NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */

#define	IWM_NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */

#define	IWM_NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */

#define	IWM_NVM_RF_CFG_PNUM_MSK_8000(x) (x & 0xF)

#define	IWM_NVM_RF_CFG_DASH_MSK_8000(x) ((x >> 4) & 0xF)

#define	IWM_NVM_RF_CFG_STEP_MSK_8000(x) ((x >> 8) & 0xF)

#define	IWM_NVM_RF_CFG_TYPE_MSK_8000(x) ((x >> 12) & 0xFFF)

#define	IWM_NVM_RF_CFG_TX_ANT_MSK_8000(x) ((x >> 24) & 0xF)

#define	IWM_NVM_RF_CFG_RX_ANT_MSK_8000(x) ((x >> 28) & 0xF)

#define	IWM_NVM_CHANNEL_VALID (1 << 0)

#define	IWM_NVM_CHANNEL_IBSS (1 << 1)

#define	IWM_NVM_CHANNEL_ACTIVE (1 << 3)

#define	IWM_NVM_CHANNEL_RADAR (1 << 4)

#define	IWM_NVM_CHANNEL_DFS (1 << 7)

#define	IWM_NVM_CHANNEL_WIDE (1 << 8)

#define	IWM_NVM_CHANNEL_40MHZ (1 << 9)

#define	IWM_NVM_CHANNEL_80MHZ (1 << 10)

#define	IWM_NVM_CHANNEL_160MHZ (1 << 11)

#define	IWM_NVM_ACCESS_TARGET_CACHE 0

#define	IWM_NVM_ACCESS_TARGET_OTP 1

#define	IWM_NVM_ACCESS_TARGET_EEPROM 2

#define	IWM_NVM_SECTION_TYPE_HW 0

#define	IWM_NVM_SECTION_TYPE_SW 1

#define	IWM_NVM_SECTION_TYPE_PAPD 2

#define	IWM_NVM_SECTION_TYPE_REGULATORY 3

#define	IWM_NVM_SECTION_TYPE_CALIBRATION 4

#define	IWM_NVM_SECTION_TYPE_PRODUCTION 5

#define	IWM_NVM_SECTION_TYPE_POST_FCS_CALIB 6

#define	IWM_NVM_SECTION_TYPE_REGULATORY_SDP 8

#define	IWM_NVM_SECTION_TYPE_HW_8000 10

#define	IWM_NVM_SECTION_TYPE_MAC_OVERRIDE 11

#define	IWM_NVM_SECTION_TYPE_PHY_SKU 12

#define	IWM_NVM_NUM_OF_SECTIONS 13

#define	IWM_PAGE_2_EXP_SIZE 12 /* 4K == 2^12 */

#define	IWM_FW_PAGING_SIZE (1 << IWM_PAGE_2_EXP_SIZE) /* page size is 4KB */

#define	IWM_PAGE_PER_GROUP_2_EXP_SIZE 3

#define	IWM_NUM_OF_PAGE_PER_GROUP (1 << IWM_PAGE_PER_GROUP_2_EXP_SIZE)

#define	IWM_PAGING_BLOCK_SIZE (IWM_NUM_OF_PAGE_PER_GROUP * IWM_FW_PAGING_SIZE)

#define	IWM_BLOCK_2_EXP_SIZE (IWM_PAGE_2_EXP_SIZE + IWM_PAGE_PER_GROUP_2_EXP_SIZE)

#define	IWM_BLOCK_PER_IMAGE_2_EXP_SIZE 5

#define	IWM_NUM_OF_BLOCK_PER_IMAGE (1 << IWM_BLOCK_PER_IMAGE_2_EXP_SIZE)

#define	IWM_MAX_PAGING_IMAGE_SIZE (IWM_NUM_OF_BLOCK_PER_IMAGE * IWM_PAGING_BLOCK_SIZE)

#define	IWM_PAGING_ADDR_SIG 0xAA000000

#define	IWM_PAGING_CMD_IS_SECURED (1 << 9)

#define	IWM_PAGING_CMD_IS_ENABLED (1 << 8)

#define	IWM_PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS 0

#define	IWM_PAGING_TLV_SECURE_MASK 1

#define	IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */

#define	IWM_ALIVE_RESP_UCODE_OK (1 << 0)

#define	IWM_ALIVE_RESP_RFKILL (1 << 1)

#define	IWM_FW_TYPE_HW 0

#define	IWM_FW_TYPE_PROT 1

#define	IWM_FW_TYPE_AP 2

#define	IWM_FW_TYPE_WOWLAN 3

#define	IWM_FW_TYPE_TIMING 4

#define	IWM_FW_TYPE_WIPAN 5

#define	IWM_FW_SUBTYPE_FULL_FEATURE 0

#define	IWM_FW_SUBTYPE_BOOTSRAP 1 /* Not valid */

#define	IWM_FW_SUBTYPE_REDUCED 2

#define	IWM_FW_SUBTYPE_ALIVE_ONLY 3

#define	IWM_FW_SUBTYPE_WOWLAN 4

#define	IWM_FW_SUBTYPE_AP_SUBTYPE 5

#define	IWM_FW_SUBTYPE_WIPAN 6

#define	IWM_FW_SUBTYPE_INITIALIZE 9

#define	IWM_ALIVE_STATUS_ERR 0xDEAD

#define	IWM_ALIVE_STATUS_OK 0xCAFE

#define	IWM_ALIVE_FLG_RFKILL (1 << 0)

#define	IWM_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0)

#define	IWM_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY (1 << 1)

#define	IWM_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc

#define	IWM_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0

#define	IWM_SOC_FLAGS_LTR_APPLY_DELAY_200 1

#define	IWM_SOC_FLAGS_LTR_APPLY_DELAY_2500 2

#define	IWM_SOC_FLAGS_LTR_APPLY_DELAY_1820 3

#define	IWM_FW_ERR_UNKNOWN_CMD 0x0

#define	IWM_FW_ERR_INVALID_CMD_PARAM 0x1

#define	IWM_FW_ERR_SERVICE 0x2

#define	IWM_FW_ERR_ARC_MEMORY 0x3

#define	IWM_FW_ERR_ARC_CODE 0x4

#define	IWM_FW_ERR_WATCH_DOG 0x5

#define	IWM_FW_ERR_WEP_GRP_KEY_INDX 0x10

#define	IWM_FW_ERR_WEP_KEY_SIZE 0x11

#define	IWM_FW_ERR_OBSOLETE_FUNC 0x12

#define	IWM_FW_ERR_UNEXPECTED 0xFE

#define	IWM_FW_ERR_FATAL 0xFF

#define	IWM_FW_CMD_VER_UNKNOWN 99

#define	IWM_MAX_MACS_IN_BINDING (3)

#define	IWM_MAX_BINDINGS (4)

#define	IWM_AUX_BINDING_INDEX (3)

#define	IWM_MAX_PHYS (4)

#define	IWM_FW_CTXT_ID_POS (0)

#define	IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)

#define	IWM_FW_CTXT_COLOR_POS (8)

#define	IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)

#define	IWM_FW_CTXT_INVALID (0xffffffff)

#define	IWM_FW_CMD_ID_AND_COLOR(_id, _color)

#define	IWM_FW_CTXT_ACTION_STUB 0

#define	IWM_FW_CTXT_ACTION_ADD 1

#define	IWM_FW_CTXT_ACTION_MODIFY 2

#define	IWM_FW_CTXT_ACTION_REMOVE 3

#define	IWM_FW_CTXT_ACTION_NUM 4

#define	IWM_TE_BSS_STA_AGGRESSIVE_ASSOC 0

#define	IWM_TE_BSS_STA_ASSOC 1

#define	IWM_TE_BSS_EAP_DHCP_PROT 2

#define	IWM_TE_BSS_QUIET_PERIOD 3

#define	IWM_TE_P2P_DEVICE_DISCOVERABLE 4

#define	IWM_TE_P2P_DEVICE_LISTEN 5

#define	IWM_TE_P2P_DEVICE_ACTION_SCAN 6

#define	IWM_TE_P2P_DEVICE_FULL_SCAN 7

#define	IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8

#define	IWM_TE_P2P_CLIENT_ASSOC 9

#define	IWM_TE_P2P_CLIENT_QUIET_PERIOD 10

#define	IWM_TE_P2P_GO_ASSOC_PROT 11

#define	IWM_TE_P2P_GO_REPETITIVE_NOA 12

#define	IWM_TE_P2P_GO_CT_WINDOW 13

#define	IWM_TE_WIDI_TX_SYNC 14

#define	IWM_TE_MAX 15

#define	IWM_TE_V1_FRAG_NONE 0

#define	IWM_TE_V1_FRAG_SINGLE 1

#define	IWM_TE_V1_FRAG_DUAL 2

#define	IWM_TE_V1_FRAG_ENDLESS 0xffffffff

#define	IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff

#define	IWM_TE_V1_REPEAT_ENDLESS 0xffffffff

#define	IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff

#define	IWM_TE_V1_INDEPENDENT 0

#define	IWM_TE_V1_DEP_OTHER (1 << 0)

#define	IWM_TE_V1_DEP_TSF (1 << 1)

#define	IWM_TE_V1_EVENT_SOCIOPATHIC (1 << 2)

#define	IWM_TE_V1_NOTIF_NONE 0

#define	IWM_TE_V1_NOTIF_HOST_EVENT_START (1 << 0)

#define	IWM_TE_V1_NOTIF_HOST_EVENT_END (1 << 1)

#define	IWM_TE_V1_NOTIF_INTERNAL_EVENT_START (1 << 2)

#define	IWM_TE_V1_NOTIF_INTERNAL_EVENT_END (1 << 3)

#define	IWM_TE_V1_NOTIF_HOST_FRAG_START (1 << 4)

#define	IWM_TE_V1_NOTIF_HOST_FRAG_END (1 << 5)

#define	IWM_TE_V1_NOTIF_INTERNAL_FRAG_START (1 << 6)

#define	IWM_TE_V1_NOTIF_INTERNAL_FRAG_END (1 << 7)

#define	IWM_TE_V2_FRAG_NONE 0

#define	IWM_TE_V2_FRAG_SINGLE 1

#define	IWM_TE_V2_FRAG_DUAL 2

#define	IWM_TE_V2_FRAG_MAX 0xfe

#define	IWM_TE_V2_FRAG_ENDLESS 0xff

#define	IWM_TE_V2_REPEAT_ENDLESS 0xff

#define	IWM_TE_V2_REPEAT_MAX 0xfe

#define	IWM_TE_V2_PLACEMENT_POS 12

#define	IWM_TE_V2_ABSENCE_POS 15

#define	IWM_TE_V2_DEFAULT_POLICY 0x0

#define	IWM_TE_V2_NOTIF_HOST_EVENT_START (1 << 0)

#define	IWM_TE_V2_NOTIF_HOST_EVENT_END (1 << 1)

#define	IWM_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2)

#define	IWM_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3)

#define	IWM_TE_V2_NOTIF_HOST_FRAG_START (1 << 4)

#define	IWM_TE_V2_NOTIF_HOST_FRAG_END (1 << 5)

#define	IWM_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6)

#define	IWM_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7)

#define	IWM_T2_V2_START_IMMEDIATELY (1 << 11)

#define	IWM_TE_V2_NOTIF_MSK 0xff

#define	IWM_TE_V2_DEP_OTHER (1 << IWM_TE_V2_PLACEMENT_POS)

#define	IWM_TE_V2_DEP_TSF (1 << (IWM_TE_V2_PLACEMENT_POS + 1))

#define	IWM_TE_V2_EVENT_SOCIOPATHIC (1 << (IWM_TE_V2_PLACEMENT_POS + 2))

#define	IWM_TE_V2_ABSENCE (1 << IWM_TE_V2_ABSENCE_POS)

#define	IWM_LMAC_24G_INDEX 0

#define	IWM_LMAC_5G_INDEX 1

#define	IWM_MAX_QUOTA 128

#define	IWM_QUOTA_LOW_LATENCY_NONE 0

#define	IWM_QUOTA_LOW_LATENCY_TX (1 << 0)

#define	IWM_QUOTA_LOW_LATENCY_RX (1 << 1)

#define	IWM_PHY_BAND_5 (0)

#define	IWM_PHY_BAND_24 (1)

#define	IWM_PHY_VHT_CHANNEL_MODE20 (0x0)

#define	IWM_PHY_VHT_CHANNEL_MODE40 (0x1)

#define	IWM_PHY_VHT_CHANNEL_MODE80 (0x2)

#define	IWM_PHY_VHT_CHANNEL_MODE160 (0x3)

#define	IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)

#define	IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)

#define	IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)

#define	IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)

#define	IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)

#define	IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)

#define	IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)

#define	IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)

#define	IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)

#define	IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)

#define	IWM_PHY_RX_CHAIN_VALID_POS (1)

#define	IWM_PHY_RX_CHAIN_VALID_MSK (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)

#define	IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)

#define	IWM_PHY_RX_CHAIN_FORCE_SEL_MSK (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)

#define	IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)

#define	IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)

#define	IWM_PHY_RX_CHAIN_CNT_POS (10)

#define	IWM_PHY_RX_CHAIN_CNT_MSK (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)

#define	IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)

#define	IWM_PHY_RX_CHAIN_MIMO_CNT_MSK (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)

#define	IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)

#define	IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)

#define	IWM_NUM_PHY_CTX 3

#define	IWM_RX_INFO_PHY_CNT 8

#define	IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1

#define	IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff

#define	IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00

#define	IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000

#define	IWM_RX_INFO_ENERGY_ANT_A_POS 0

#define	IWM_RX_INFO_ENERGY_ANT_B_POS 8

#define	IWM_RX_INFO_ENERGY_ANT_C_POS 16

#define	IWM_RX_INFO_AGC_IDX 1

#define	IWM_RX_INFO_RSSI_AB_IDX 2

#define	IWM_OFDM_AGC_A_MSK 0x0000007f

#define	IWM_OFDM_AGC_A_POS 0

#define	IWM_OFDM_AGC_B_MSK 0x00003f80

#define	IWM_OFDM_AGC_B_POS 7

#define	IWM_OFDM_AGC_CODE_MSK 0x3fe00000

#define	IWM_OFDM_AGC_CODE_POS 20

#define	IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff

#define	IWM_OFDM_RSSI_A_POS 0

#define	IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00

#define	IWM_OFDM_RSSI_ALLBAND_A_POS 8

#define	IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000

#define	IWM_OFDM_RSSI_B_POS 16

#define	IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000

#define	IWM_OFDM_RSSI_ALLBAND_B_POS 24

#define	IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)

#define	IWM_RX_RES_PHY_FLAGS_BAND_24 (1 << 0)

#define	IWM_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1)

#define	IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2)

#define	IWM_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3)

#define	IWM_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4)

#define	IWM_RX_RES_PHY_FLAGS_ANTENNA_POS 4

#define	IWM_RX_RES_PHY_FLAGS_AGG (1 << 7)

#define	IWM_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8)

#define	IWM_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9)

#define	IWM_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10)

#define	IWM_RX_MPDU_RES_STATUS_CRC_OK (1 << 0)

#define	IWM_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1)

#define	IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2)

#define	IWM_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3)

#define	IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4)

#define	IWM_RX_MPDU_RES_STATUS_ICV_OK (1 << 5)

#define	IWM_RX_MPDU_RES_STATUS_MIC_OK (1 << 6)

#define	IWM_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)

#define	IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7)

#define	IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8)

#define	IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8)

#define	IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8)

#define	IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8)

#define	IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8)

#define	IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8)

#define	IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8)

#define	IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8)

#define	IWM_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11)

#define	IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12)

#define	IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13)

#define	IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14)

#define	IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15)

#define	IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000)

#define	IWM_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000)

#define	IWM_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29)

#define	IWM_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000)

#define	IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000)

#define	IWM_RX_MPDU_MFLG1_ADDRTYPE_MASK 0x03

#define	IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK 0xf0

#define	IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT 3

#define	IWM_RX_MPDU_MFLG2_HDR_LEN_MASK 0x1f

#define	IWM_RX_MPDU_MFLG2_PAD 0x20

#define	IWM_RX_MPDU_MFLG2_AMSDU 0x40

#define	IWM_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK 0x7f

#define	IWM_RX_MPDU_AMSDU_LAST_SUBFRAME 0x80

#define	IWM_RX_MPDU_PHY_AMPDU (1 << 5)

#define	IWM_RX_MPDU_PHY_AMPDU_TOGGLE (1 << 6)

#define	IWM_RX_MPDU_PHY_SHORT_PREAMBLE (1 << 7)

#define	IWM_RX_MPDU_PHY_NCCK_ADDTL_NTFY (1 << 7)

#define	IWM_RX_MPDU_PHY_TSF_OVERLOAD (1 << 8)

#define	IWM_RX_REORDER_DATA_INVALID_BAID 0x7f

#define	IWM_RX_MPDU_REORDER_NSSN_MASK 0x00000fff

#define	IWM_RX_MPDU_REORDER_SN_MASK 0x00fff000

#define	IWM_RX_MPDU_REORDER_SN_SHIFT 12

#define	IWM_RX_MPDU_REORDER_BAID_MASK 0x7f000000

#define	IWM_RX_MPDU_REORDER_BAID_SHIFT 24

#define	IWM_RX_MPDU_REORDER_BA_OLD_SN 0x80000000

#define	IWM_CARD_ENABLED 0x00

#define	IWM_HW_CARD_DISABLED 0x01

#define	IWM_SW_CARD_DISABLED 0x02

#define	IWM_CT_KILL_CARD_DISABLED 0x04

#define	IWM_HALT_CARD_DISABLED 0x08

#define	IWM_CARD_DISABLED_MSK 0x0f

#define	IWM_CARD_IS_RX_ON 0x10

#define	IWM_MAX_PORT_ID_NUM 2

#define	IWM_MAX_MCAST_FILTERING_ADDRESSES 256

#define	IWM_MAX_CHAINS 3

#define	IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */

#define	IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */

#define	IWM_SF_W_MARK_SISO 4096

#define	IWM_SF_W_MARK_MIMO2 8192

#define	IWM_SF_W_MARK_MIMO3 6144

#define	IWM_SF_W_MARK_LEGACY 4096

#define	IWM_SF_W_MARK_SCAN 4096

#define	IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */

#define	IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */

#define	IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */

#define	IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */

#define	IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */

#define	IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */

#define	IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */

#define	IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */

#define	IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */

#define	IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */

#define	IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */

#define	IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */

#define	IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */

#define	IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */

#define	IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */

#define	IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */

#define	IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */

#define	IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */

#define	IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */

#define	IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */

#define	IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */

#define	IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)

#define	IWM_MAC_INDEX_AUX 4

#define	IWM_MAC_INDEX_MIN_DRIVER 0

#define	IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX

#define	IWM_AC_BK 0

#define	IWM_AC_BE 1

#define	IWM_AC_VI 2

#define	IWM_AC_VO 3

#define	IWM_AC_NUM 4

#define	IWM_MAC_PROT_FLG_TGG_PROTECT (1 << 3)

#define	IWM_MAC_PROT_FLG_HT_PROT (1 << 23)

#define	IWM_MAC_PROT_FLG_FAT_PROT (1 << 24)

#define	IWM_MAC_PROT_FLG_SELF_CTS_EN (1 << 30)

#define	IWM_MAC_FLG_SHORT_SLOT (1 << 4)

#define	IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)

#define	IWM_FW_MAC_TYPE_FIRST 1

#define	IWM_FW_MAC_TYPE_AUX IWM_FW_MAC_TYPE_FIRST

#define	IWM_FW_MAC_TYPE_LISTENER 2

#define	IWM_FW_MAC_TYPE_PIBSS 3

#define	IWM_FW_MAC_TYPE_IBSS 4

#define	IWM_FW_MAC_TYPE_BSS_STA 5

#define	IWM_FW_MAC_TYPE_P2P_DEVICE 6

#define	IWM_FW_MAC_TYPE_P2P_STA 7

#define	IWM_FW_MAC_TYPE_GO 8

#define	IWM_FW_MAC_TYPE_TEST 9

#define	IWM_FW_MAC_TYPE_MAX IWM_FW_MAC_TYPE_TEST

#define	IWM_TSF_ID_A 0

#define	IWM_TSF_ID_B 1

#define	IWM_TSF_ID_C 2

#define	IWM_TSF_ID_D 3

#define	IWM_NUM_TSF_IDS 4

#define	IWM_MAC_FILTER_IN_PROMISC (1 << 0)

#define	IWM_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1)

#define	IWM_MAC_FILTER_ACCEPT_GRP (1 << 2)

#define	IWM_MAC_FILTER_DIS_DECRYPT (1 << 3)

#define	IWM_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4)

#define	IWM_MAC_FILTER_IN_BEACON (1 << 6)

#define	IWM_MAC_FILTER_OUT_BCAST (1 << 8)

#define	IWM_MAC_FILTER_IN_CRC32 (1 << 11)

#define	IWM_MAC_FILTER_IN_PROBE_REQUEST (1 << 12)

#define	IWM_MAC_QOS_FLG_UPDATE_EDCA (1 << 0)

#define	IWM_MAC_QOS_FLG_TGN (1 << 1)

#define	IWM_MAC_QOS_FLG_TXOP_TYPE (1 << 4)

#define	IWM_NONQOS_SEQ_GET 0x1

#define	IWM_NONQOS_SEQ_SET 0x2

#define	IWM_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001

#define	IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002

#define	IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004

#define	IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008

#define	IWM_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010

#define	IWM_LTR_CFG_FLAG_SW_SET_LONG 0x00000020

#define	IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040

#define	IWM_LTR_VALID_STATES_NUM 4

#define	IWM_POWER_LPRX_RSSI_THRESHOLD 75

#define	IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94

#define	IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30

#define	IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)

#define	IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1)

#define	IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2)

#define	IWM_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5)

#define	IWM_POWER_FLAGS_BT_SCO_ENA (1 << 8)

#define	IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9)

#define	IWM_POWER_FLAGS_LPRX_ENA_MSK (1 << 11)

#define	IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12)

#define	IWM_POWER_VEC_SIZE 5

#define	IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)

#define	IWM_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13)

#define	IWM_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000)

#define	IWM_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000)

#define	IWM_BF_ENERGY_DELTA_DEFAULT 5

#define	IWM_BF_ENERGY_DELTA_MAX 255

#define	IWM_BF_ENERGY_DELTA_MIN 0

#define	IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1

#define	IWM_BF_ROAMING_ENERGY_DELTA_MAX 255

#define	IWM_BF_ROAMING_ENERGY_DELTA_MIN 0

#define	IWM_BF_ROAMING_STATE_DEFAULT 72

#define	IWM_BF_ROAMING_STATE_MAX 255

#define	IWM_BF_ROAMING_STATE_MIN 0

#define	IWM_BF_TEMP_THRESHOLD_DEFAULT 112

#define	IWM_BF_TEMP_THRESHOLD_MAX 255

#define	IWM_BF_TEMP_THRESHOLD_MIN 0

#define	IWM_BF_TEMP_FAST_FILTER_DEFAULT 1

#define	IWM_BF_TEMP_FAST_FILTER_MAX 255

#define	IWM_BF_TEMP_FAST_FILTER_MIN 0

#define	IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5

#define	IWM_BF_TEMP_SLOW_FILTER_MAX 255

#define	IWM_BF_TEMP_SLOW_FILTER_MIN 0

#define	IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1

#define	IWM_BF_DEBUG_FLAG_DEFAULT 0

#define	IWM_BF_ESCAPE_TIMER_DEFAULT 50

#define	IWM_BF_ESCAPE_TIMER_MAX 1024

#define	IWM_BF_ESCAPE_TIMER_MIN 0

#define	IWM_BA_ESCAPE_TIMER_DEFAULT 6

#define	IWM_BA_ESCAPE_TIMER_D3 9

#define	IWM_BA_ESCAPE_TIMER_MAX 1024

#define	IWM_BA_ESCAPE_TIMER_MIN 0

#define	IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1

#define	IWM_BF_CMD_CONFIG_DEFAULTS

#define	IWM_RATE_HT_SISO_MCS_0_PLCP 0

#define	IWM_RATE_HT_SISO_MCS_1_PLCP 1

#define	IWM_RATE_HT_SISO_MCS_2_PLCP 2

#define	IWM_RATE_HT_SISO_MCS_3_PLCP 3

#define	IWM_RATE_HT_SISO_MCS_4_PLCP 4

#define	IWM_RATE_HT_SISO_MCS_5_PLCP 5

#define	IWM_RATE_HT_SISO_MCS_6_PLCP 6

#define	IWM_RATE_HT_SISO_MCS_7_PLCP 7

#define	IWM_RATE_HT_MIMO2_MCS_8_PLCP 0x8

#define	IWM_RATE_HT_MIMO2_MCS_9_PLCP 0x9

#define	IWM_RATE_HT_MIMO2_MCS_10_PLCP 0xA

#define	IWM_RATE_HT_MIMO2_MCS_11_PLCP 0xB

#define	IWM_RATE_HT_MIMO2_MCS_12_PLCP 0xC

#define	IWM_RATE_HT_MIMO2_MCS_13_PLCP 0xD

#define	IWM_RATE_HT_MIMO2_MCS_14_PLCP 0xE

#define	IWM_RATE_HT_MIMO2_MCS_15_PLCP 0xF

#define	IWM_RATE_VHT_SISO_MCS_0_PLCP 0

#define	IWM_RATE_VHT_SISO_MCS_1_PLCP 1

#define	IWM_RATE_VHT_SISO_MCS_2_PLCP 2

#define	IWM_RATE_VHT_SISO_MCS_3_PLCP 3

#define	IWM_RATE_VHT_SISO_MCS_4_PLCP 4

#define	IWM_RATE_VHT_SISO_MCS_5_PLCP 5

#define	IWM_RATE_VHT_SISO_MCS_6_PLCP 6

#define	IWM_RATE_VHT_SISO_MCS_7_PLCP 7

#define	IWM_RATE_VHT_SISO_MCS_8_PLCP 8

#define	IWM_RATE_VHT_SISO_MCS_9_PLCP 9

#define	IWM_RATE_VHT_MIMO2_MCS_0_PLCP 0x10

#define	IWM_RATE_VHT_MIMO2_MCS_1_PLCP 0x11

#define	IWM_RATE_VHT_MIMO2_MCS_2_PLCP 0x12

#define	IWM_RATE_VHT_MIMO2_MCS_3_PLCP 0x13

#define	IWM_RATE_VHT_MIMO2_MCS_4_PLCP 0x14

#define	IWM_RATE_VHT_MIMO2_MCS_5_PLCP 0x15

#define	IWM_RATE_VHT_MIMO2_MCS_6_PLCP 0x16

#define	IWM_RATE_VHT_MIMO2_MCS_7_PLCP 0x17

#define	IWM_RATE_VHT_MIMO2_MCS_8_PLCP 0x18

#define	IWM_RATE_VHT_MIMO2_MCS_9_PLCP 0x19

#define	IWM_RATE_HT_SISO_MCS_INV_PLCP 0x20

#define	IWM_RATE_HT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP

#define	IWM_RATE_VHT_SISO_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP

#define	IWM_RATE_VHT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP

#define	IWM_RATE_HT_SISO_MCS_8_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP

#define	IWM_RATE_HT_SISO_MCS_9_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP

#define	IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))

#define	IWM_RATE_6M_PLCP 13

#define	IWM_RATE_9M_PLCP 15

#define	IWM_RATE_12M_PLCP 5

#define	IWM_RATE_18M_PLCP 7

#define	IWM_RATE_24M_PLCP 9

#define	IWM_RATE_36M_PLCP 11

#define	IWM_RATE_48M_PLCP 1

#define	IWM_RATE_54M_PLCP 3

#define	IWM_RATE_1M_PLCP 10

#define	IWM_RATE_2M_PLCP 20

#define	IWM_RATE_5M_PLCP 55

#define	IWM_RATE_11M_PLCP 110

#define	IWM_RATE_INVM_PLCP 0xff

#define	IWM_RATE_MCS_HT_POS 8

#define	IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)

#define	IWM_RATE_MCS_CCK_POS 9

#define	IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)

#define	IWM_RATE_MCS_VHT_POS 26

#define	IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)

#define	IWM_RATE_MCS_RTS_REQUIRED_POS 30

#define	IWM_RATE_MCS_RTS_REQUIRED_MSK (1 << IWM_RATE_MCS_RTS_REQUIRED_POS)

#define	IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7

#define	IWM_RATE_HT_MCS_NSS_POS 3

#define	IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)

#define	IWM_RATE_HT_MCS_GF_POS 10

#define	IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)

#define	IWM_RATE_HT_MCS_INDEX_MSK 0x3f

#define	IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf

#define	IWM_RATE_VHT_MCS_NSS_POS 4

#define	IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)

#define	IWM_RATE_LEGACY_RATE_MSK 0xff

#define	IWM_RATE_MCS_CHAN_WIDTH_POS 11

#define	IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)

#define	IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)

#define	IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)

#define	IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)

#define	IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)

#define	IWM_RATE_MCS_SGI_POS 13

#define	IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)

#define	IWM_RATE_MCS_ANT_POS 14

#define	IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)

#define	IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)

#define	IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)

#define	IWM_RATE_MCS_ANT_AB_MSK

#define	IWM_RATE_MCS_ANT_ABC_MSK

#define	IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK

#define	IWM_RATE_MCS_ANT_NUM 3

#define	IWM_RATE_MCS_STBC_POS 17

#define	IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)

#define	IWM_RATE_MCS_BF_POS 19

#define	IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)

#define	IWM_RATE_MCS_ZLF_POS 20

#define	IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)

#define	IWM_RATE_MCS_DUP_POS 24

#define	IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)

#define	IWM_RATE_MCS_LDPC_POS 27

#define	IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)

#define	IWM_LQ_MAX_RETRY_NUM 16

#define	IWM_LQ_FLAG_USE_RTS_POS 0

#define	IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)

#define	IWM_LQ_FLAG_COLOR_POS 1

#define	IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)

#define	IWM_LQ_FLAG_RTS_BW_SIG_POS 4

#define	IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)

#define	IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)

#define	IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)

#define	IWM_LQ_FLAG_DYNAMIC_BW_POS 6

#define	IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)

#define	IWM_ANT_A (1 << 0)

#define	IWM_ANT_B (1 << 1)

#define	IWM_ANT_C (1 << 2)

#define	IWM_ANT_AB (IWM_ANT_A \| IWM_ANT_B)

#define	IWM_ANT_BC (IWM_ANT_B \| IWM_ANT_C)

#define	IWM_ANT_ABC (IWM_ANT_A \| IWM_ANT_B \| IWM_ANT_C)

#define	IWM_TX_CMD_FLG_PROT_REQUIRE (1 << 0)

#define	IWM_TX_CMD_FLG_ACK (1 << 3)

#define	IWM_TX_CMD_FLG_STA_RATE (1 << 4)

#define	IWM_TX_CMD_FLG_BA (1 << 5)

#define	IWM_TX_CMD_FLG_BAR (1 << 6)

#define	IWM_TX_CMD_FLG_TXOP_PROT (1 << 7)

#define	IWM_TX_CMD_FLG_VHT_NDPA (1 << 8)

#define	IWM_TX_CMD_FLG_HT_NDPA (1 << 9)

#define	IWM_TX_CMD_FLG_CSI_FDBK2HOST (1 << 10)

#define	IWM_TX_CMD_FLG_BT_DIS (1 << 12)

#define	IWM_TX_CMD_FLG_SEQ_CTL (1 << 13)

#define	IWM_TX_CMD_FLG_MORE_FRAG (1 << 14)

#define	IWM_TX_CMD_FLG_NEXT_FRAME (1 << 15)

#define	IWM_TX_CMD_FLG_TSF (1 << 16)

#define	IWM_TX_CMD_FLG_CALIB (1 << 17)

#define	IWM_TX_CMD_FLG_KEEP_SEQ_CTL (1 << 18)

#define	IWM_TX_CMD_FLG_AGG_START (1 << 19)

#define	IWM_TX_CMD_FLG_MH_PAD (1 << 20)

#define	IWM_TX_CMD_FLG_RESP_TO_DRV (1 << 21)

#define	IWM_TX_CMD_FLG_CCMP_AGG (1 << 22)

#define	IWM_TX_CMD_FLG_TKIP_MIC_DONE (1 << 23)

#define	IWM_TX_CMD_FLG_DUR (1 << 25)

#define	IWM_TX_CMD_FLG_FW_DROP (1 << 26)

#define	IWM_TX_CMD_FLG_EXEC_PAPD (1 << 27)

#define	IWM_TX_CMD_FLG_PAPD_TYPE (1 << 28)

#define	IWM_TX_CMD_FLG_HCCA_CHUNK (1U << 31)

#define	IWM_TX_CMD_SEC_WEP 0x01

#define	IWM_TX_CMD_SEC_CCM 0x02

#define	IWM_TX_CMD_SEC_TKIP 0x03

#define	IWM_TX_CMD_SEC_EXT 0x04

#define	IWM_TX_CMD_SEC_MSK 0x07

#define	IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6

#define	IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0

#define	IWM_TX_CMD_SEC_KEY128 0x08

#define	IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)

#define	IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)

#define	IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)

#define	IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)

#define	IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)

#define	IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)

#define	IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)

#define	IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)

#define	IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)

#define	IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF

#define	IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/

#define	IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */

#define	IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0

#define	IWM_MAX_TID_COUNT 8

#define	IWM_TID_NON_QOS 0

#define	IWM_TID_MGMT 15

#define	IWM_DEFAULT_TX_RETRY 15

#define	IWM_MGMT_DFAULT_RETRY_LIMIT 3

#define	IWM_RTS_DFAULT_RETRY_LIMIT 3

#define	IWM_BAR_DFAULT_RETRY_LIMIT 60

#define	IWM_LOW_RETRY_LIMIT 7

#define	IWM_TX_CMD_OFFLD_IP_HDR (1 << 0)

#define	IWM_TX_CMD_OFFLD_L4_EN (1 << 6)

#define	IWM_TX_CMD_OFFLD_L3_EN (1 << 7)

#define	IWM_TX_CMD_OFFLD_MH_SIZE (1 << 8)

#define	IWM_TX_CMD_OFFLD_PAD (1 << 13)

#define	IWM_TX_CMD_OFFLD_AMSDU (1 << 14)

#define	IWM_TX_STATUS_MSK 0x000000ff

#define	IWM_TX_STATUS_SUCCESS 0x01

#define	IWM_TX_STATUS_DIRECT_DONE 0x02

#define	IWM_TX_STATUS_POSTPONE_DELAY 0x40

#define	IWM_TX_STATUS_POSTPONE_FEW_BYTES 0x41

#define	IWM_TX_STATUS_POSTPONE_BT_PRIO 0x42

#define	IWM_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43

#define	IWM_TX_STATUS_POSTPONE_CALC_TTAK 0x44

#define	IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81

#define	IWM_TX_STATUS_FAIL_SHORT_LIMIT 0x82

#define	IWM_TX_STATUS_FAIL_LONG_LIMIT 0x83

#define	IWM_TX_STATUS_FAIL_UNDERRUN 0x84

#define	IWM_TX_STATUS_FAIL_DRAIN_FLOW 0x85

#define	IWM_TX_STATUS_FAIL_RFKILL_FLUSH 0x86

#define	IWM_TX_STATUS_FAIL_LIFE_EXPIRE 0x87

#define	IWM_TX_STATUS_FAIL_DEST_PS 0x88

#define	IWM_TX_STATUS_FAIL_HOST_ABORTED 0x89

#define	IWM_TX_STATUS_FAIL_BT_RETRY 0x8a

#define	IWM_TX_STATUS_FAIL_STA_INVALID 0x8b

#define	IWM_TX_STATUS_FAIL_FRAG_DROPPED 0x8c

#define	IWM_TX_STATUS_FAIL_TID_DISABLE 0x8d

#define	IWM_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e

#define	IWM_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f

#define	IWM_TX_STATUS_FAIL_FW_DROP 0x90

#define	IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91

#define	IWM_TX_STATUS_INTERNAL_ABORT 0x92

#define	IWM_TX_MODE_MSK 0x00000f00

#define	IWM_TX_MODE_NO_BURST 0x00000000

#define	IWM_TX_MODE_IN_BURST_SEQ 0x00000100

#define	IWM_TX_MODE_FIRST_IN_BURST 0x00000200

#define	IWM_TX_QUEUE_NUM_MSK 0x0001f000

#define	IWM_TX_NARROW_BW_MSK 0x00060000

#define	IWM_TX_NARROW_BW_1DIV2 0x00020000

#define	IWM_TX_NARROW_BW_1DIV4 0x00040000

#define	IWM_TX_NARROW_BW_1DIV8 0x00060000

#define	IWM_AGG_TX_STATE_STATUS_MSK 0x0fff

#define	IWM_AGG_TX_STATE_TRANSMITTED 0x0000

#define	IWM_AGG_TX_STATE_UNDERRUN 0x0001

#define	IWM_AGG_TX_STATE_BT_PRIO 0x0002

#define	IWM_AGG_TX_STATE_FEW_BYTES 0x0004

#define	IWM_AGG_TX_STATE_ABORT 0x0008

#define	IWM_AGG_TX_STATE_LAST_SENT_TTL 0x0010

#define	IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020

#define	IWM_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040

#define	IWM_AGG_TX_STATE_SCD_QUERY 0x0080

#define	IWM_AGG_TX_STATE_TEST_BAD_CRC32 0x0100

#define	IWM_AGG_TX_STATE_RESPONSE 0x01ff

#define	IWM_AGG_TX_STATE_DUMP_TX 0x0200

#define	IWM_AGG_TX_STATE_DELAY_TX 0x0400

#define	IWM_AGG_TX_STATE_TRY_CNT_POS 12

#define	IWM_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWM_AGG_TX_STATE_TRY_CNT_POS)

#define	IWM_AGG_TX_STATE_LAST_SENT_MSK

#define	IWM_AGG_TX_STAT_FRAME_NOT_SENT

#define	IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f

#define	IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70

#define	IWM_TX_RES_INV_RATE_INDEX_MSK 0x80

#define	IWM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)

#define	IWM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)

#define	IWM_DUMP_TX_FIFO_FLUSH (1 << 1)

#define	IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0)

#define	IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1)

#define	IWM_PROBE_OPTION_MAX 20

#define	IWM_SCAN_MAX_BLACKLIST_LEN 64

#define	IWM_SCAN_SHORT_BLACKLIST_LEN 16

#define	IWM_SCAN_MAX_PROFILES 11

#define	IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512

#define	IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)

#define	IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)

#define	IWM_CAN_ABORT_STATUS 1

#define	IWM_FULL_SCAN_MULTIPLIER 5

#define	IWM_FAST_SCHED_SCAN_ITERATIONS 3

#define	IWM_MAX_SCHED_SCAN_PLANS 2

#define	IWM_UNIFIED_SCAN_CHANNEL_FULL (1 << 27)

#define	IWM_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28)

#define	IWM_SCAN_CHANNEL_FLAG_EBS (1 << 0)

#define	IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1)

#define	IWM_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2)

#define	IWM_LMAC_SCAN_FLAG_PASS_ALL (1 << 0)

#define	IWM_LMAC_SCAN_FLAG_PASSIVE (1 << 1)

#define	IWM_LMAC_SCAN_FLAG_PRE_CONNECTION (1 << 2)

#define	IWM_LMAC_SCAN_FLAG_ITER_COMPLETE (1 << 3)

#define	IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS (1 << 4)

#define	IWM_LMAC_SCAN_FLAG_FRAGMENTED (1 << 5)

#define	IWM_LMAC_SCAN_FLAGS_RRM_ENABLED (1 << 6)

#define	IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL (1 << 7)

#define	IWM_LMAC_SCAN_FLAG_MATCH (1 << 9)

#define	IWM_SCAN_PRIORITY_LOW 0

#define	IWM_SCAN_PRIORITY_MEDIUM 1

#define	IWM_SCAN_PRIORITY_HIGH 2

#define	IWM_SCAN_CLIENT_SCHED_SCAN (1 << 0)

#define	IWM_SCAN_CLIENT_NETDETECT (1 << 1)

#define	IWM_SCAN_CLIENT_ASSET_TRACKING (1 << 2)

#define	IWM_NETWORK_TYPE_BSS 1

#define	IWM_NETWORK_TYPE_IBSS 2

#define	IWM_NETWORK_TYPE_ANY 3

#define	IWM_SCAN_OFFLOAD_SELECT_2_4 0x4

#define	IWM_SCAN_OFFLOAD_SELECT_5_2 0x8

#define	IWM_SCAN_OFFLOAD_SELECT_ANY 0xc

#define	IWM_MAX_UMAC_SCANS 8

#define	IWM_MAX_LMAC_SCANS 1

#define	IWM_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0)

#define	IWM_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1)

#define	IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2)

#define	IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3)

#define	IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8)

#define	IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9)

#define	IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10)

#define	IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11)

#define	IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12)

#define	IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13)

#define	IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14)

#define	IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15)

#define	IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16)

#define	IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17)

#define	IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18)

#define	IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19)

#define	IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20)

#define	IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21)

#define	IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26)

#define	IWM_SCAN_CONFIG_RATE_6M (1 << 0)

#define	IWM_SCAN_CONFIG_RATE_9M (1 << 1)

#define	IWM_SCAN_CONFIG_RATE_12M (1 << 2)

#define	IWM_SCAN_CONFIG_RATE_18M (1 << 3)

#define	IWM_SCAN_CONFIG_RATE_24M (1 << 4)

#define	IWM_SCAN_CONFIG_RATE_36M (1 << 5)

#define	IWM_SCAN_CONFIG_RATE_48M (1 << 6)

#define	IWM_SCAN_CONFIG_RATE_54M (1 << 7)

#define	IWM_SCAN_CONFIG_RATE_1M (1 << 8)

#define	IWM_SCAN_CONFIG_RATE_2M (1 << 9)

#define	IWM_SCAN_CONFIG_RATE_5M (1 << 10)

#define	IWM_SCAN_CONFIG_RATE_11M (1 << 11)

#define	IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16)

#define	IWM_CHANNEL_FLAG_EBS (1 << 0)

#define	IWM_CHANNEL_FLAG_ACCURATE_EBS (1 << 1)

#define	IWM_CHANNEL_FLAG_EBS_ADD (1 << 2)

#define	IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3)

#define	IWM_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0)

#define	IWM_UMAC_SCAN_FLAG_START_NOTIF (1 << 1)

#define	IWM_UMAC_SCAN_UID_TYPE_OFFSET 0

#define	IWM_UMAC_SCAN_UID_SEQ_OFFSET 8

#define	IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0)

#define	IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1)

#define	IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2)

#define	IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3)

#define	IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4)

#define	IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5)

#define	IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6)

#define	IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7)

#define	IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8)

#define	IWM_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9)

#define	IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10)

#define	IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP (1 << 10)

#define	IWM_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED (1 << 11)

#define	IWM_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL (1 << 13)

#define	IWM_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME (1 << 14)

#define	IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE (1 << 15)

#define	IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL (1 << 0)

#define	IWM_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER (1 << 1)

#define	IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1)

#define	IWM_SCAN_LB_LMAC_IDX 0

#define	IWM_SCAN_HB_LMAC_IDX 1

#define	IWM_SCAN_REQ_UMAC_SIZE_V8 sizeof(struct iwm_scan_req_umac)

#define	IWM_SCAN_REQ_UMAC_SIZE_V7 48

#define	IWM_SCAN_REQ_UMAC_SIZE_V6 44

#define	IWM_SCAN_REQ_UMAC_SIZE_V1 36

#define	IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5

#define	IWM_GSCAN_START_CMD 0x0

#define	IWM_GSCAN_STOP_CMD 0x1

#define	IWM_GSCAN_SET_HOTLIST_CMD 0x2

#define	IWM_GSCAN_RESET_HOTLIST_CMD 0x3

#define	IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4

#define	IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5

#define	IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD

#define	IWM_GSCAN_HOTLIST_CHANGE_EVENT 0xFE

#define	IWM_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF

#define	IWM_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3)

#define	IWM_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6)

#define	IWM_STA_FLG_DISABLE_TX (1 << 4)

#define	IWM_STA_FLG_PS (1 << 8)

#define	IWM_STA_FLG_DRAIN_FLOW (1 << 12)

#define	IWM_STA_FLG_PAN (1 << 13)

#define	IWM_STA_FLG_CLASS_AUTH (1 << 14)

#define	IWM_STA_FLG_CLASS_ASSOC (1 << 15)

#define	IWM_STA_FLG_RTS_MIMO_PROT (1 << 17)

#define	IWM_STA_FLG_MAX_AGG_SIZE_SHIFT 19

#define	IWM_STA_FLG_MAX_AGG_SIZE_8K (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

#define	IWM_STA_FLG_MAX_AGG_SIZE_16K (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

#define	IWM_STA_FLG_MAX_AGG_SIZE_32K (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

#define	IWM_STA_FLG_MAX_AGG_SIZE_64K (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

#define	IWM_STA_FLG_MAX_AGG_SIZE_128K (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

#define	IWM_STA_FLG_MAX_AGG_SIZE_256K (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

#define	IWM_STA_FLG_MAX_AGG_SIZE_512K (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

#define	IWM_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

#define	IWM_STA_FLG_MAX_AGG_SIZE_MSK (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

#define	IWM_STA_FLG_AGG_MPDU_DENS_SHIFT 23

#define	IWM_STA_FLG_AGG_MPDU_DENS_2US (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)

#define	IWM_STA_FLG_AGG_MPDU_DENS_4US (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)

#define	IWM_STA_FLG_AGG_MPDU_DENS_8US (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)

#define	IWM_STA_FLG_AGG_MPDU_DENS_16US (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)

#define	IWM_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)

#define	IWM_STA_FLG_FAT_EN_20MHZ (0 << 26)

#define	IWM_STA_FLG_FAT_EN_40MHZ (1 << 26)

#define	IWM_STA_FLG_FAT_EN_80MHZ (2 << 26)

#define	IWM_STA_FLG_FAT_EN_160MHZ (3 << 26)

#define	IWM_STA_FLG_FAT_EN_MSK (3 << 26)

#define	IWM_STA_FLG_MIMO_EN_SISO (0 << 28)

#define	IWM_STA_FLG_MIMO_EN_MIMO2 (1 << 28)

#define	IWM_STA_FLG_MIMO_EN_MIMO3 (2 << 28)

#define	IWM_STA_FLG_MIMO_EN_MSK (3 << 28)

#define	IWM_STA_KEY_FLG_NO_ENC (0 << 0)

#define	IWM_STA_KEY_FLG_WEP (1 << 0)

#define	IWM_STA_KEY_FLG_CCM (2 << 0)

#define	IWM_STA_KEY_FLG_TKIP (3 << 0)

#define	IWM_STA_KEY_FLG_EXT (4 << 0)

#define	IWM_STA_KEY_FLG_CMAC (6 << 0)

#define	IWM_STA_KEY_FLG_ENC_UNKNOWN (7 << 0)

#define	IWM_STA_KEY_FLG_EN_MSK (7 << 0)

#define	IWM_STA_KEY_FLG_WEP_KEY_MAP (1 << 3)

#define	IWM_STA_KEY_FLG_KEYID_POS 8

#define	IWM_STA_KEY_FLG_KEYID_MSK (3 << IWM_STA_KEY_FLG_KEYID_POS)

#define	IWM_STA_KEY_NOT_VALID (1 << 11)

#define	IWM_STA_KEY_FLG_WEP_13BYTES (1 << 12)

#define	IWM_STA_KEY_MULTICAST (1 << 14)

#define	IWM_STA_KEY_MFP (1 << 15)

#define	IWM_STA_MODIFY_QUEUE_REMOVAL (1 << 0)

#define	IWM_STA_MODIFY_TID_DISABLE_TX (1 << 1)

#define	IWM_STA_MODIFY_TX_RATE (1 << 2)

#define	IWM_STA_MODIFY_ADD_BA_TID (1 << 3)

#define	IWM_STA_MODIFY_REMOVE_BA_TID (1 << 4)

#define	IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5)

#define	IWM_STA_MODIFY_PROT_TH (1 << 6)

#define	IWM_STA_MODIFY_QUEUES (1 << 7)

#define	IWM_STA_MODE_MODIFY 1

#define	IWM_STA_SLEEP_STATE_AWAKE 0

#define	IWM_STA_SLEEP_STATE_PS_POLL (1 << 0)

#define	IWM_STA_SLEEP_STATE_UAPSD (1 << 1)

#define	IWM_STA_SLEEP_STATE_MOREDATA (1 << 2)

#define	IWM_STA_ID_SEED (0x0f)

#define	IWM_STA_ID_POS (0)

#define	IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)

#define	IWM_STA_COLOR_SEED (0x7)

#define	IWM_STA_COLOR_POS (4)

#define	IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)

#define	IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)

#define	IWM_STA_ID_N_COLOR_GET_ID(id_n_color) (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)

#define	IWM_STA_KEY_MAX_NUM (16)

#define	IWM_STA_KEY_IDX_INVALID (0xff)

#define	IWM_STA_KEY_MAX_DATA_KEY_NUM (4)

#define	IWM_MAX_GLOBAL_KEYS (4)

#define	IWM_STA_KEY_LEN_WEP40 (5)

#define	IWM_STA_KEY_LEN_WEP104 (13)

#define	IWM_ADD_STA_STATUS_MASK 0xFF

#define	IWM_ADD_STA_BAID_VALID_MASK 0x8000

#define	IWM_ADD_STA_BAID_MASK 0x7F00

#define	IWM_ADD_STA_BAID_SHIFT 8

#define	IWM_STA_LINK 0

#define	IWM_STA_GENERAL_PURPOSE 1

#define	IWM_STA_MULTICAST 2

#define	IWM_STA_TDLS_LINK 3

#define	IWM_STA_AUX_ACTIVITY 4

#define	IWM_ADD_STA_SUCCESS 0x1

#define	IWM_ADD_STA_STATIONS_OVERLOAD 0x2

#define	IWM_ADD_STA_IMMEDIATE_BA_FAILURE 0x4

#define	IWM_ADD_STA_MODIFY_NON_EXISTING_STA 0x8

#define	IWM_BT_COEX_DISABLE 0x0

#define	IWM_BT_COEX_NW 0x1

#define	IWM_BT_COEX_BT 0x2

#define	IWM_BT_COEX_WIFI 0x3

#define	IWM_BT_COEX_MPLUT_ENABLED (1 << 0)

#define	IWM_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1)

#define	IWM_BT_COEX_SYNC2SCO_ENABLED (1 << 2)

#define	IWM_BT_COEX_CORUN_ENABLED (1 << 3)

#define	IWM_BT_COEX_HIGH_BAND_RET (1 << 4)

#define	IWM_GEO_NO_INFO 0

#define	IWM_GEO_WMM_ETSI_5GHZ_INFO (1 << 0)

#define	IWM_MCC_RESP_NEW_CHAN_PROFILE 0

#define	IWM_MCC_RESP_SAME_CHAN_PROFILE 1

#define	IWM_MCC_RESP_INVALID 2

#define	IWM_MCC_RESP_NVM_DISABLED 3

#define	IWM_MCC_RESP_ILLEGAL 4

#define	IWM_MCC_RESP_LOW_PRIORITY 5

#define	IWM_MCC_RESP_TEST_MODE_ACTIVE 6

#define	IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE 7

#define	IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE 8

#define	IWM_MCC_SOURCE_OLD_FW 0

#define	IWM_MCC_SOURCE_ME 1

#define	IWM_MCC_SOURCE_BIOS 2

#define	IWM_MCC_SOURCE_3G_LTE_HOST 3

#define	IWM_MCC_SOURCE_3G_LTE_DEVICE 4

#define	IWM_MCC_SOURCE_WIFI 5

#define	IWM_MCC_SOURCE_RESERVED 6

#define	IWM_MCC_SOURCE_DEFAULT 7

#define	IWM_MCC_SOURCE_UNINITIALIZED 8

#define	IWM_MCC_SOURCE_MCC_API 9

#define	IWM_MCC_SOURCE_GET_CURRENT 0x10

#define	IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11

#define	IWM_FRAME_LIMIT 64

#define	IWM_WIDE_ID(grp, opcode) ((grp << 8) \| opcode)

#define	IWM_ALWAYS_LONG_GROUP 1

#define	IWM_POWER_SCHEME_CAM 1

#define	IWM_POWER_SCHEME_BPS 2

#define	IWM_POWER_SCHEME_LP 3

#define	IWM_DEF_CMD_PAYLOAD_SIZE 320

#define	IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))

#define	IWM_CMD_FAILED_MSK 0x40

#define	IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff

#define	IWM_FH_RSCSR_FRAME_INVALID 0x55550000

#define	IWM_FH_RSCSR_FRAME_ALIGN 0x40

#define	IWM_FH_RSCSR_RPA_EN (1 << 25)

#define	IWM_FH_RSCSR_RADA_EN (1 << 26)

#define	IWM_FH_RSCSR_RXQ_POS 16

#define	IWM_FH_RSCSR_RXQ_MASK 0x3F0000

#define	IWM_MIN_DBM -100

#define	IWM_MAX_DBM -33 /* realistic guess */

#define	IWM_READ(sc, reg) bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

#define	IWM_WRITE(sc, reg, val) bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

#define	IWM_WRITE_1(sc, reg, val) bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

#define	IWM_SETBITS(sc, reg, mask) IWM_WRITE(sc, reg, IWM_READ(sc, reg) \| (mask))

#define	IWM_CLRBITS(sc, reg, mask) IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))

#define	IWM_BARRIER_WRITE(sc)

#define	IWM_BARRIER_READ_WRITE(sc)

Enumerations
enum	{ IWM_SILICON_A_STEP = 0 , IWM_SILICON_B_STEP , IWM_SILICON_C_STEP }

enum	msix_fh_int_causes { IWM_MSIX_FH_INT_CAUSES_Q0 = (1 << 0) , IWM_MSIX_FH_INT_CAUSES_Q1 = (1 << 1) , IWM_MSIX_FH_INT_CAUSES_D2S_CH0_NUM = (1 << 16) , IWM_MSIX_FH_INT_CAUSES_D2S_CH1_NUM = (1 << 17) , IWM_MSIX_FH_INT_CAUSES_S2D = (1 << 19) , IWM_MSIX_FH_INT_CAUSES_FH_ERR = (1 << 21) }

enum	msix_hw_int_causes { IWM_MSIX_HW_INT_CAUSES_REG_ALIVE = (1 << 0) , IWM_MSIX_HW_INT_CAUSES_REG_WAKEUP = (1 << 1) , IWM_MSIX_HW_INT_CAUSES_REG_IPC = (1 << 1) , IWM_MSIX_HW_INT_CAUSES_REG_IML = (1 << 2) , IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = (1 << 5) , IWM_MSIX_HW_INT_CAUSES_REG_CT_KILL = (1 << 6) , IWM_MSIX_HW_INT_CAUSES_REG_RF_KILL = (1 << 7) , IWM_MSIX_HW_INT_CAUSES_REG_PERIODIC = (1 << 8) , IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR = (1 << 25) , IWM_MSIX_HW_INT_CAUSES_REG_SCD = (1 << 26) , IWM_MSIX_HW_INT_CAUSES_REG_FH_TX = (1 << 27) , IWM_MSIX_HW_INT_CAUSES_REG_HW_ERR = (1 << 29) , IWM_MSIX_HW_INT_CAUSES_REG_HAP = (1 << 30) }

enum	msix_ivar_for_cause { IWM_MSIX_IVAR_CAUSE_D2S_CH0_NUM = 0x0 , IWM_MSIX_IVAR_CAUSE_D2S_CH1_NUM = 0x1 , IWM_MSIX_IVAR_CAUSE_S2D = 0x3 , IWM_MSIX_IVAR_CAUSE_FH_ERR = 0x5 , IWM_MSIX_IVAR_CAUSE_REG_ALIVE = 0x10 , IWM_MSIX_IVAR_CAUSE_REG_WAKEUP = 0x11 , IWM_MSIX_IVAR_CAUSE_REG_IML = 0x12 , IWM_MSIX_IVAR_CAUSE_REG_CT_KILL = 0x16 , IWM_MSIX_IVAR_CAUSE_REG_RF_KILL = 0x17 , IWM_MSIX_IVAR_CAUSE_REG_PERIODIC = 0x18 , IWM_MSIX_IVAR_CAUSE_REG_SW_ERR = 0x29 , IWM_MSIX_IVAR_CAUSE_REG_SCD = 0x2a , IWM_MSIX_IVAR_CAUSE_REG_FH_TX = 0x2b , IWM_MSIX_IVAR_CAUSE_REG_HW_ERR = 0x2d , IWM_MSIX_IVAR_CAUSE_REG_HAP = 0x2e }

enum	iwm_ucode_tlv_type { IWM_UCODE_TLV_INVALID = 0 , IWM_UCODE_TLV_INST = 1 , IWM_UCODE_TLV_DATA = 2 , IWM_UCODE_TLV_INIT = 3 , IWM_UCODE_TLV_INIT_DATA = 4 , IWM_UCODE_TLV_BOOT = 5 , IWM_UCODE_TLV_PROBE_MAX_LEN = 6 , IWM_UCODE_TLV_PAN = 7 , IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8 , IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9 , IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10 , IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11 , IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12 , IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13 , IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14 , IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15 , IWM_UCODE_TLV_WOWLAN_INST = 16 , IWM_UCODE_TLV_WOWLAN_DATA = 17 , IWM_UCODE_TLV_FLAGS = 18 , IWM_UCODE_TLV_SEC_RT = 19 , IWM_UCODE_TLV_SEC_INIT = 20 , IWM_UCODE_TLV_SEC_WOWLAN = 21 , IWM_UCODE_TLV_DEF_CALIB = 22 , IWM_UCODE_TLV_PHY_SKU = 23 , IWM_UCODE_TLV_SECURE_SEC_RT = 24 , IWM_UCODE_TLV_SECURE_SEC_INIT = 25 , IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26 , IWM_UCODE_TLV_NUM_OF_CPU = 27 , IWM_UCODE_TLV_CSCHEME = 28 , IWM_UCODE_TLV_API_CHANGES_SET = 29 , IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30 , IWM_UCODE_TLV_N_SCAN_CHANNELS = 31 , IWM_UCODE_TLV_PAGING = 32 , IWM_UCODE_TLV_SEC_RT_USNIFFER = 34 , IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35 , IWM_UCODE_TLV_FW_VERSION = 36 , IWM_UCODE_TLV_FW_DBG_DEST = 38 , IWM_UCODE_TLV_FW_DBG_CONF = 39 , IWM_UCODE_TLV_FW_DBG_TRIGGER = 40 , IWM_UCODE_TLV_CMD_VERSIONS = 48 , IWM_UCODE_TLV_FW_GSCAN_CAPA = 50 , IWM_UCODE_TLV_FW_MEM_SEG = 51 , IWM_UCODE_TLV_UMAC_DEBUG_ADDRS = 54 , IWM_UCODE_TLV_LMAC_DEBUG_ADDRS = 55 , IWM_UCODE_TLV_HW_TYPE = 58 }

enum	iwm_phy_db_section_type { IWM_PHY_DB_CFG = 1 , IWM_PHY_DB_CALIB_NCH , IWM_PHY_DB_UNUSED , IWM_PHY_DB_CALIB_CHG_PAPD , IWM_PHY_DB_CALIB_CHG_TXP , IWM_PHY_DB_MAX }

enum	iwm_sf_state { IWM_SF_LONG_DELAY_ON = 0 , IWM_SF_FULL_ON , IWM_SF_UNINIT , IWM_SF_INIT_OFF , IWM_SF_HW_NUM_STATES }

enum	iwm_sf_scenario { IWM_SF_SCENARIO_SINGLE_UNICAST , IWM_SF_SCENARIO_AGG_UNICAST , IWM_SF_SCENARIO_MULTICAST , IWM_SF_SCENARIO_BA_RESP , IWM_SF_SCENARIO_TX_RESP , IWM_SF_NUM_SCENARIO }

enum	{ IWM_RATE_1M_INDEX = 0 , IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX , IWM_RATE_2M_INDEX , IWM_RATE_5M_INDEX , IWM_RATE_11M_INDEX , IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX , IWM_RATE_6M_INDEX , IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX , IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX , IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX , IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX , IWM_RATE_9M_INDEX , IWM_RATE_12M_INDEX , IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX , IWM_RATE_18M_INDEX , IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX , IWM_RATE_24M_INDEX , IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX , IWM_RATE_36M_INDEX , IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX , IWM_RATE_48M_INDEX , IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX , IWM_RATE_54M_INDEX , IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX , IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX , IWM_RATE_60M_INDEX , IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX , IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX , IWM_RATE_MCS_8_INDEX , IWM_RATE_MCS_9_INDEX , IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX , IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1 , IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1 }

enum	iwm_tx_pm_timeouts { IWM_PM_FRAME_NONE = 0 , IWM_PM_FRAME_MGMT = 2 , IWM_PM_FRAME_ASSOC = 3 }

enum	iwm_scan_offload_complete_status { IWM_SCAN_OFFLOAD_COMPLETED = 1 , IWM_SCAN_OFFLOAD_ABORTED = 2 }

enum	iwm_scan_ebs_status { IWM_SCAN_EBS_SUCCESS , IWM_SCAN_EBS_FAILED , IWM_SCAN_EBS_CHAN_NOT_FOUND , IWM_SCAN_EBS_INACTIVE }

Functions
static unsigned int	IWM_SCD_QUEUE_WRPTR (unsigned int chnl)

static unsigned int	IWM_SCD_QUEUE_RDPTR (unsigned int chnl)

static unsigned int	IWM_SCD_QUEUE_STATUS_BITS (unsigned int chnl)

static unsigned int	IWM_FH_MEM_CBBC_QUEUE (unsigned int chnl)

static uint8_t	iwm_get_dma_hi_addr (bus_addr_t addr)

static uint32_t	iwm_reciprocal (uint32_t v)

static uint32_t	iwm_get_scd_ssn (struct iwm_tx_resp *tx_resp)

static uint8_t	iwm_cmd_opcode (uint32_t cmdid)

static uint8_t	iwm_cmd_groupid (uint32_t cmdid)

static uint8_t	iwm_cmd_version (uint32_t cmdid)

static uint32_t	iwm_cmd_id (uint8_t opcode, uint8_t groupid, uint8_t version)

static uint32_t	iwm_rx_packet_len (const struct iwm_rx_packet *pkt)

static uint32_t	iwm_rx_packet_payload_len (const struct iwm_rx_packet *pkt)

Variables
struct iwm_tlv_calib_ctrl	__packed

Macro Definition Documentation

◆ IWM_AC_BE

#define IWM_AC_BE 1

Definition at line 3818 of file if_iwmreg.h.

◆ IWM_AC_BK

#define IWM_AC_BK 0

Definition at line 3817 of file if_iwmreg.h.

◆ IWM_AC_NUM

#define IWM_AC_NUM 4

Definition at line 3821 of file if_iwmreg.h.

◆ IWM_AC_VI

#define IWM_AC_VI 2

Definition at line 3819 of file if_iwmreg.h.

◆ IWM_AC_VO

#define IWM_AC_VO 3

Definition at line 3820 of file if_iwmreg.h.

◆ IWM_ADD_STA

#define IWM_ADD_STA 0x18

Definition at line 1999 of file if_iwmreg.h.

◆ IWM_ADD_STA_BAID_MASK

#define IWM_ADD_STA_BAID_MASK 0x7F00

Definition at line 6334 of file if_iwmreg.h.

◆ IWM_ADD_STA_BAID_SHIFT

#define IWM_ADD_STA_BAID_SHIFT 8

Definition at line 6335 of file if_iwmreg.h.

◆ IWM_ADD_STA_BAID_VALID_MASK

#define IWM_ADD_STA_BAID_VALID_MASK 0x8000

Definition at line 6333 of file if_iwmreg.h.

◆ IWM_ADD_STA_IMMEDIATE_BA_FAILURE

#define IWM_ADD_STA_IMMEDIATE_BA_FAILURE 0x4

Definition at line 6540 of file if_iwmreg.h.

◆ IWM_ADD_STA_KEY

#define IWM_ADD_STA_KEY 0x17

Definition at line 1998 of file if_iwmreg.h.

◆ IWM_ADD_STA_MODIFY_NON_EXISTING_STA

#define IWM_ADD_STA_MODIFY_NON_EXISTING_STA 0x8

Definition at line 6541 of file if_iwmreg.h.

◆ IWM_ADD_STA_STATIONS_OVERLOAD

#define IWM_ADD_STA_STATIONS_OVERLOAD 0x2

Definition at line 6539 of file if_iwmreg.h.

◆ IWM_ADD_STA_STATUS_MASK

#define IWM_ADD_STA_STATUS_MASK 0xFF

Definition at line 6332 of file if_iwmreg.h.

◆ IWM_ADD_STA_SUCCESS

#define IWM_ADD_STA_SUCCESS 0x1

status in the response to ADD_STA command @IWM_ADD_STA_SUCCESS: operation was executed successfully @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station that doesn't exist.

Definition at line 6538 of file if_iwmreg.h.

◆ IWM_AGG_TX_STAT_FRAME_NOT_SENT

#define IWM_AGG_TX_STAT_FRAME_NOT_SENT

Value:

                                    (IWM_AGG_TX_STATE_FEW_BYTES | \
                                    IWM_AGG_TX_STATE_ABORT | \
                                    IWM_AGG_TX_STATE_SCD_QUERY)

Definition at line 5092 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_ABORT

#define IWM_AGG_TX_STATE_ABORT 0x0008

Definition at line 5071 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_BT_PRIO

#define IWM_AGG_TX_STATE_BT_PRIO 0x0002

Definition at line 5069 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_DELAY_TX

#define IWM_AGG_TX_STATE_DELAY_TX 0x0400

Definition at line 5079 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_DUMP_TX

#define IWM_AGG_TX_STATE_DUMP_TX 0x0200

Definition at line 5078 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_FEW_BYTES

#define IWM_AGG_TX_STATE_FEW_BYTES 0x0004

Definition at line 5070 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_LAST_SENT_BT_KILL

#define IWM_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040

Definition at line 5074 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_LAST_SENT_MSK

#define IWM_AGG_TX_STATE_LAST_SENT_MSK

Value:

                                     (IWM_AGG_TX_STATE_LAST_SENT_TTL| \
                                     IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
                                     IWM_AGG_TX_STATE_LAST_SENT_BT_KILL)

Definition at line 5083 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT

#define IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020

Definition at line 5073 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_LAST_SENT_TTL

#define IWM_AGG_TX_STATE_LAST_SENT_TTL 0x0010

Definition at line 5072 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_RESPONSE

#define IWM_AGG_TX_STATE_RESPONSE 0x01ff

Definition at line 5077 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_SCD_QUERY

#define IWM_AGG_TX_STATE_SCD_QUERY 0x0080

Definition at line 5075 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_STATUS_MSK

#define IWM_AGG_TX_STATE_STATUS_MSK 0x0fff

Definition at line 5066 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_TEST_BAD_CRC32

#define IWM_AGG_TX_STATE_TEST_BAD_CRC32 0x0100

Definition at line 5076 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_TRANSMITTED

#define IWM_AGG_TX_STATE_TRANSMITTED 0x0000

Definition at line 5067 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_TRY_CNT_MSK

#define IWM_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWM_AGG_TX_STATE_TRY_CNT_POS)

Definition at line 5081 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_TRY_CNT_POS

#define IWM_AGG_TX_STATE_TRY_CNT_POS 12

Definition at line 5080 of file if_iwmreg.h.

◆ IWM_AGG_TX_STATE_UNDERRUN

#define IWM_AGG_TX_STATE_UNDERRUN 0x0001

Definition at line 5068 of file if_iwmreg.h.

◆ IWM_ALIVE

#define IWM_ALIVE 0x1

Definition at line 1982 of file if_iwmreg.h.

◆ IWM_ALIVE_FLG_RFKILL

#define IWM_ALIVE_FLG_RFKILL (1 << 0)

Definition at line 2526 of file if_iwmreg.h.

◆ IWM_ALIVE_RESP_RFKILL

#define IWM_ALIVE_RESP_RFKILL (1 << 1)

Definition at line 2503 of file if_iwmreg.h.

◆ IWM_ALIVE_RESP_UCODE_OK

#define IWM_ALIVE_RESP_UCODE_OK (1 << 0)

Definition at line 2502 of file if_iwmreg.h.

◆ IWM_ALIVE_STATUS_ERR

#define IWM_ALIVE_STATUS_ERR 0xDEAD

Definition at line 2523 of file if_iwmreg.h.

◆ IWM_ALIVE_STATUS_OK

#define IWM_ALIVE_STATUS_OK 0xCAFE

Definition at line 2524 of file if_iwmreg.h.

◆ IWM_ALWAYS_LONG_GROUP

#define IWM_ALWAYS_LONG_GROUP 1

Definition at line 6857 of file if_iwmreg.h.

◆ IWM_ANT_A

#define IWM_ANT_A (1 << 0)

Definition at line 4728 of file if_iwmreg.h.

◆ IWM_ANT_AB

#define IWM_ANT_AB (IWM_ANT_A | IWM_ANT_B)

Definition at line 4732 of file if_iwmreg.h.

◆ IWM_ANT_ABC

#define IWM_ANT_ABC (IWM_ANT_A | IWM_ANT_B | IWM_ANT_C)

Definition at line 4734 of file if_iwmreg.h.

◆ IWM_ANT_B

#define IWM_ANT_B (1 << 1)

Definition at line 4729 of file if_iwmreg.h.

◆ IWM_ANT_BC

#define IWM_ANT_BC (IWM_ANT_B | IWM_ANT_C)

Definition at line 4733 of file if_iwmreg.h.

◆ IWM_ANT_C

#define IWM_ANT_C (1 << 2)

Definition at line 4730 of file if_iwmreg.h.

◆ IWM_APMG_ANALOG_SVR_REG

#define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)

Definition at line 1216 of file if_iwmreg.h.

◆ IWM_APMG_BASE

#define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)

Definition at line 1206 of file if_iwmreg.h.

◆ IWM_APMG_CLK_CTRL_REG

#define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)

Definition at line 1207 of file if_iwmreg.h.

◆ IWM_APMG_CLK_DIS_REG

#define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)

Definition at line 1209 of file if_iwmreg.h.

◆ IWM_APMG_CLK_EN_REG

#define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)

Definition at line 1208 of file if_iwmreg.h.

◆ IWM_APMG_CLK_VAL_BSM_CLK_RQT

#define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)

Definition at line 1220 of file if_iwmreg.h.

◆ IWM_APMG_CLK_VAL_DMA_CLK_RQT

#define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)

Definition at line 1219 of file if_iwmreg.h.

◆ IWM_APMG_DIGITAL_SVR_REG

#define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)

Definition at line 1215 of file if_iwmreg.h.

◆ IWM_APMG_PCIDEV_STT_REG

#define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)

Definition at line 1211 of file if_iwmreg.h.

◆ IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS

#define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)

Definition at line 1230 of file if_iwmreg.h.

◆ IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS

#define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)

Definition at line 1222 of file if_iwmreg.h.

◆ IWM_APMG_PS_CTRL_MSK_PWR_SRC

#define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)

Definition at line 1224 of file if_iwmreg.h.

◆ IWM_APMG_PS_CTRL_REG

#define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)

Definition at line 1210 of file if_iwmreg.h.

◆ IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX

#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)

Definition at line 1226 of file if_iwmreg.h.

◆ IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN

#define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)

Definition at line 1225 of file if_iwmreg.h.

◆ IWM_APMG_PS_CTRL_VAL_RESET_REQ

#define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)

Definition at line 1223 of file if_iwmreg.h.

◆ IWM_APMG_RFKILL_REG

#define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)

Definition at line 1212 of file if_iwmreg.h.

◆ IWM_APMG_RTC_INT_MSK_REG

#define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)

Definition at line 1214 of file if_iwmreg.h.

◆ IWM_APMG_RTC_INT_STT_REG

#define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)

Definition at line 1213 of file if_iwmreg.h.

◆ IWM_APMG_RTC_INT_STT_RFKILL

#define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)

Definition at line 1232 of file if_iwmreg.h.

◆ IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32

#define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)

Definition at line 1228 of file if_iwmreg.h.

◆ IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK

#define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */

Definition at line 1227 of file if_iwmreg.h.

◆ IWM_APMS_CLK_VAL_MRB_FUNC_MODE

#define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)

Definition at line 1218 of file if_iwmreg.h.

◆ IWM_AUX_BINDING_INDEX

#define IWM_AUX_BINDING_INDEX (3)

Definition at line 2647 of file if_iwmreg.h.

◆ IWM_AUX_MISC_MASTER1_EN

#define IWM_AUX_MISC_MASTER1_EN 0xa20818

Definition at line 624 of file if_iwmreg.h.

◆ IWM_AUX_MISC_MASTER1_EN_SBE_MSK

#define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1

Definition at line 625 of file if_iwmreg.h.

◆ IWM_AUX_MISC_MASTER1_SMPHR_STATUS

#define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800

Definition at line 626 of file if_iwmreg.h.

◆ IWM_AUX_MISC_REG

#define IWM_AUX_MISC_REG 0xa200b0

Definition at line 621 of file if_iwmreg.h.

◆ IWM_AUX_QUEUE

#define IWM_AUX_QUEUE 15

Definition at line 1968 of file if_iwmreg.h.

◆ IWM_BA_ENABLE_BEACON_ABORT_DEFAULT

#define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1

Definition at line 4416 of file if_iwmreg.h.

◆ IWM_BA_ESCAPE_TIMER_D3

#define IWM_BA_ESCAPE_TIMER_D3 9

Definition at line 4412 of file if_iwmreg.h.

◆ IWM_BA_ESCAPE_TIMER_DEFAULT

#define IWM_BA_ESCAPE_TIMER_DEFAULT 6

Definition at line 4411 of file if_iwmreg.h.

◆ IWM_BA_ESCAPE_TIMER_MAX

#define IWM_BA_ESCAPE_TIMER_MAX 1024

Definition at line 4413 of file if_iwmreg.h.

◆ IWM_BA_ESCAPE_TIMER_MIN

#define IWM_BA_ESCAPE_TIMER_MIN 0

Definition at line 4414 of file if_iwmreg.h.

◆ IWM_BA_NOTIF

#define IWM_BA_NOTIF 0xc5

Definition at line 2081 of file if_iwmreg.h.

◆ IWM_BAR_DFAULT_RETRY_LIMIT

#define IWM_BAR_DFAULT_RETRY_LIMIT 60

Definition at line 4917 of file if_iwmreg.h.

◆ IWM_BARRIER_READ_WRITE

#define IWM_BARRIER_READ_WRITE ( sc )

Value:

bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \

BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)

Definition at line 6973 of file if_iwmreg.h.

◆ IWM_BARRIER_WRITE

#define IWM_BARRIER_WRITE ( sc )

Value:

bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \

BUS_SPACE_BARRIER_WRITE)

Definition at line 6969 of file if_iwmreg.h.

◆ IWM_BEACON_NOTIFICATION

#define IWM_BEACON_NOTIFICATION 0x90

Definition at line 2061 of file if_iwmreg.h.

◆ IWM_BEACON_TEMPLATE_CMD

#define IWM_BEACON_TEMPLATE_CMD 0x91

Definition at line 2062 of file if_iwmreg.h.

◆ IWM_BF_CMD_CONFIG_DEFAULTS

#define IWM_BF_CMD_CONFIG_DEFAULTS

Value:

        .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT),             \
        .bf_roaming_energy_delta =                                           \
                htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT),        \
        .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT),           \
        .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT),     \
        .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
        .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
        .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT),         \
        .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT),             \
        .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)

Definition at line 4418 of file if_iwmreg.h.

◆ IWM_BF_DEBUG_FLAG_DEFAULT

#define IWM_BF_DEBUG_FLAG_DEFAULT 0

Definition at line 4405 of file if_iwmreg.h.

◆ IWM_BF_ENABLE_BEACON_FILTER_DEFAULT

#define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1

Definition at line 4403 of file if_iwmreg.h.

◆ IWM_BF_ENERGY_DELTA_DEFAULT

#define IWM_BF_ENERGY_DELTA_DEFAULT 5

Definition at line 4379 of file if_iwmreg.h.

◆ IWM_BF_ENERGY_DELTA_MAX

#define IWM_BF_ENERGY_DELTA_MAX 255

Definition at line 4380 of file if_iwmreg.h.

◆ IWM_BF_ENERGY_DELTA_MIN

#define IWM_BF_ENERGY_DELTA_MIN 0

Definition at line 4381 of file if_iwmreg.h.

◆ IWM_BF_ESCAPE_TIMER_DEFAULT

#define IWM_BF_ESCAPE_TIMER_DEFAULT 50

Definition at line 4407 of file if_iwmreg.h.

◆ IWM_BF_ESCAPE_TIMER_MAX

#define IWM_BF_ESCAPE_TIMER_MAX 1024

Definition at line 4408 of file if_iwmreg.h.

◆ IWM_BF_ESCAPE_TIMER_MIN

#define IWM_BF_ESCAPE_TIMER_MIN 0

Definition at line 4409 of file if_iwmreg.h.

◆ IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT

#define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1

Definition at line 4383 of file if_iwmreg.h.

◆ IWM_BF_ROAMING_ENERGY_DELTA_MAX

#define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255

Definition at line 4384 of file if_iwmreg.h.

◆ IWM_BF_ROAMING_ENERGY_DELTA_MIN

#define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0

Definition at line 4385 of file if_iwmreg.h.

◆ IWM_BF_ROAMING_STATE_DEFAULT

#define IWM_BF_ROAMING_STATE_DEFAULT 72

Definition at line 4387 of file if_iwmreg.h.

◆ IWM_BF_ROAMING_STATE_MAX

#define IWM_BF_ROAMING_STATE_MAX 255

Definition at line 4388 of file if_iwmreg.h.

◆ IWM_BF_ROAMING_STATE_MIN

#define IWM_BF_ROAMING_STATE_MIN 0

Definition at line 4389 of file if_iwmreg.h.

◆ IWM_BF_TEMP_FAST_FILTER_DEFAULT

#define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1

Definition at line 4395 of file if_iwmreg.h.

◆ IWM_BF_TEMP_FAST_FILTER_MAX

#define IWM_BF_TEMP_FAST_FILTER_MAX 255

Definition at line 4396 of file if_iwmreg.h.

◆ IWM_BF_TEMP_FAST_FILTER_MIN

#define IWM_BF_TEMP_FAST_FILTER_MIN 0

Definition at line 4397 of file if_iwmreg.h.

◆ IWM_BF_TEMP_SLOW_FILTER_DEFAULT

#define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5

Definition at line 4399 of file if_iwmreg.h.

◆ IWM_BF_TEMP_SLOW_FILTER_MAX

#define IWM_BF_TEMP_SLOW_FILTER_MAX 255

Definition at line 4400 of file if_iwmreg.h.

◆ IWM_BF_TEMP_SLOW_FILTER_MIN

#define IWM_BF_TEMP_SLOW_FILTER_MIN 0

Definition at line 4401 of file if_iwmreg.h.

◆ IWM_BF_TEMP_THRESHOLD_DEFAULT

#define IWM_BF_TEMP_THRESHOLD_DEFAULT 112

Definition at line 4391 of file if_iwmreg.h.

◆ IWM_BF_TEMP_THRESHOLD_MAX

#define IWM_BF_TEMP_THRESHOLD_MAX 255

Definition at line 4392 of file if_iwmreg.h.

◆ IWM_BF_TEMP_THRESHOLD_MIN

#define IWM_BF_TEMP_THRESHOLD_MIN 0

Definition at line 4393 of file if_iwmreg.h.

◆ IWM_BINDING_CONTEXT_CMD

#define IWM_BINDING_CONTEXT_CMD 0x2b

Definition at line 2017 of file if_iwmreg.h.

◆ IWM_BLOCK_2_EXP_SIZE

#define IWM_BLOCK_2_EXP_SIZE (IWM_PAGE_2_EXP_SIZE + IWM_PAGE_PER_GROUP_2_EXP_SIZE)

Definition at line 2443 of file if_iwmreg.h.

◆ IWM_BLOCK_PER_IMAGE_2_EXP_SIZE

#define IWM_BLOCK_PER_IMAGE_2_EXP_SIZE 5

Definition at line 2448 of file if_iwmreg.h.

◆ IWM_BT_COEX_BT

#define IWM_BT_COEX_BT 0x2

Definition at line 6598 of file if_iwmreg.h.

◆ IWM_BT_COEX_CI

#define IWM_BT_COEX_CI 0x5d

Definition at line 2091 of file if_iwmreg.h.

◆ IWM_BT_COEX_CORUN_ENABLED

#define IWM_BT_COEX_CORUN_ENABLED (1 << 3)

Definition at line 6605 of file if_iwmreg.h.

◆ IWM_BT_COEX_DISABLE

#define IWM_BT_COEX_DISABLE 0x0

Definition at line 6596 of file if_iwmreg.h.

◆ IWM_BT_COEX_HIGH_BAND_RET

#define IWM_BT_COEX_HIGH_BAND_RET (1 << 4)

Definition at line 6606 of file if_iwmreg.h.

◆ IWM_BT_COEX_MPLUT_BOOST_ENABLED

#define IWM_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1)

Definition at line 6603 of file if_iwmreg.h.

◆ IWM_BT_COEX_MPLUT_ENABLED

#define IWM_BT_COEX_MPLUT_ENABLED (1 << 0)

Definition at line 6602 of file if_iwmreg.h.

◆ IWM_BT_COEX_NW

#define IWM_BT_COEX_NW 0x1

Definition at line 6597 of file if_iwmreg.h.

◆ IWM_BT_COEX_PRIO_TABLE

#define IWM_BT_COEX_PRIO_TABLE 0xcc

Definition at line 2088 of file if_iwmreg.h.

◆ IWM_BT_COEX_PROT_ENV

#define IWM_BT_COEX_PROT_ENV 0xcd

Definition at line 2089 of file if_iwmreg.h.

◆ IWM_BT_COEX_SYNC2SCO_ENABLED

#define IWM_BT_COEX_SYNC2SCO_ENABLED (1 << 2)

Definition at line 6604 of file if_iwmreg.h.

◆ IWM_BT_COEX_WIFI

#define IWM_BT_COEX_WIFI 0x3

Definition at line 6599 of file if_iwmreg.h.

◆ IWM_BT_CONFIG

#define IWM_BT_CONFIG 0x9b

Definition at line 2064 of file if_iwmreg.h.

◆ IWM_BT_PROFILE_NOTIFICATION

#define IWM_BT_PROFILE_NOTIFICATION 0xce

Definition at line 2090 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_ABS_IDX

#define IWM_CALIB_CFG_ABS_IDX (1 << 17)

Definition at line 2228 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_AGC_IDX

#define IWM_CALIB_CFG_AGC_IDX (1 << 18)

Definition at line 2229 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_ANT_COUPLING_IDX

#define IWM_CALIB_CFG_ANT_COUPLING_IDX (1 << 15)

Definition at line 2226 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_BB_FILTER_IDX

#define IWM_CALIB_CFG_BB_FILTER_IDX (1 << 6)

Definition at line 2217 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_CHAIN_NOISE_IDX

#define IWM_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13)

Definition at line 2224 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_DAC_IDX

#define IWM_CALIB_CFG_DAC_IDX (1 << 16)

Definition at line 2227 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_DC_IDX

#define IWM_CALIB_CFG_DC_IDX (1 << 5)

Definition at line 2216 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_DISCONNECTED_ANT_IDX

#define IWM_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14)

Definition at line 2225 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_LO_LEAKAGE_IDX

#define IWM_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7)

Definition at line 2218 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_PAPD_IDX

#define IWM_CALIB_CFG_PAPD_IDX (1 << 3)

Definition at line 2214 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_RX_IQ_IDX

#define IWM_CALIB_CFG_RX_IQ_IDX (1 << 10)

Definition at line 2221 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_RX_IQ_SKEW_IDX

#define IWM_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11)

Definition at line 2222 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_SENSITIVITY_IDX

#define IWM_CALIB_CFG_SENSITIVITY_IDX (1 << 12)

Definition at line 2223 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_TEMPERATURE_IDX

#define IWM_CALIB_CFG_TEMPERATURE_IDX (1 << 1)

Definition at line 2212 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_TX_IQ_IDX

#define IWM_CALIB_CFG_TX_IQ_IDX (1 << 8)

Definition at line 2219 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_TX_IQ_SKEW_IDX

#define IWM_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9)

Definition at line 2220 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_TX_PWR_IDX

#define IWM_CALIB_CFG_TX_PWR_IDX (1 << 4)

Definition at line 2215 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_VOLTAGE_READ_IDX

#define IWM_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2)

Definition at line 2213 of file if_iwmreg.h.

◆ IWM_CALIB_CFG_XTAL_IDX

#define IWM_CALIB_CFG_XTAL_IDX (1 << 0)

Definition at line 2211 of file if_iwmreg.h.

◆ IWM_CALIB_RES_NOTIF_PHY_DB

#define IWM_CALIB_RES_NOTIF_PHY_DB 0x6b

Definition at line 2045 of file if_iwmreg.h.

◆ IWM_CALIBRATION_CFG_CMD

#define IWM_CALIBRATION_CFG_CMD 0x65

Definition at line 2025 of file if_iwmreg.h.

◆ IWM_CALIBRATION_COMPLETE_NOTIFICATION

#define IWM_CALIBRATION_COMPLETE_NOTIFICATION 0x67

Definition at line 2027 of file if_iwmreg.h.

◆ IWM_CALIBRATION_RES_NOTIFICATION

#define IWM_CALIBRATION_RES_NOTIFICATION 0x66

Definition at line 2026 of file if_iwmreg.h.

◆ IWM_CAN_ABORT_STATUS

#define IWM_CAN_ABORT_STATUS 1

Definition at line 5392 of file if_iwmreg.h.

◆ IWM_CARD_DISABLED_MSK

#define IWM_CARD_DISABLED_MSK 0x0f

Definition at line 3435 of file if_iwmreg.h.

◆ IWM_CARD_ENABLED

#define IWM_CARD_ENABLED 0x00

Definition at line 3430 of file if_iwmreg.h.

◆ IWM_CARD_IS_RX_ON

#define IWM_CARD_IS_RX_ON 0x10

Definition at line 3436 of file if_iwmreg.h.

◆ IWM_CARD_STATE_CMD

#define IWM_CARD_STATE_CMD 0xa0

Definition at line 2069 of file if_iwmreg.h.

◆ IWM_CARD_STATE_NOTIFICATION

#define IWM_CARD_STATE_NOTIFICATION 0xa1

Definition at line 2070 of file if_iwmreg.h.

◆ IWM_CHANNEL_FLAG_ACCURATE_EBS

#define IWM_CHANNEL_FLAG_ACCURATE_EBS (1 << 1)

Definition at line 5759 of file if_iwmreg.h.

◆ IWM_CHANNEL_FLAG_EBS

#define IWM_CHANNEL_FLAG_EBS (1 << 0)

Definition at line 5758 of file if_iwmreg.h.

◆ IWM_CHANNEL_FLAG_EBS_ADD

#define IWM_CHANNEL_FLAG_EBS_ADD (1 << 2)

Definition at line 5760 of file if_iwmreg.h.

◆ IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE

#define IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3)

Definition at line 5761 of file if_iwmreg.h.

◆ IWM_CLRBITS

#define IWM_CLRBITS	(	sc,
		reg,
		mask
	)	IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))

Definition at line 6966 of file if_iwmreg.h.

◆ IWM_CMD_DTS_MEASUREMENT_TRIGGER

#define IWM_CMD_DTS_MEASUREMENT_TRIGGER 0xdc

Definition at line 2097 of file if_iwmreg.h.

◆ IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE

#define IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE 0x0

Definition at line 2133 of file if_iwmreg.h.

◆ IWM_CMD_FAILED_MSK

#define IWM_CMD_FAILED_MSK 0x40

Definition at line 6882 of file if_iwmreg.h.

◆ IWM_CMD_QUEUE

#define IWM_CMD_QUEUE 9

Definition at line 1967 of file if_iwmreg.h.

◆ IWM_CPU1_CPU2_SEPARATOR_SECTION

#define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC

Definition at line 980 of file if_iwmreg.h.

◆ IWM_CSR50_ANA_PLL_CFG_VAL

#define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)

Definition at line 413 of file if_iwmreg.h.

◆ IWM_CSR_ANA_PLL_CFG

#define IWM_CSR_ANA_PLL_CFG (0x20c)

Definition at line 151 of file if_iwmreg.h.

◆ IWM_CSR_DBG_HPET_MEM_REG

#define IWM_CSR_DBG_HPET_MEM_REG (0x240)

Definition at line 163 of file if_iwmreg.h.

◆ IWM_CSR_DBG_HPET_MEM_REG_VAL

#define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)

Definition at line 416 of file if_iwmreg.h.

◆ IWM_CSR_DBG_LINK_PWR_MGMT_REG

#define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)

Definition at line 164 of file if_iwmreg.h.

◆ IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK

#define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)

Definition at line 421 of file if_iwmreg.h.

◆ IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER

#define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)

Definition at line 420 of file if_iwmreg.h.

◆ IWM_CSR_DRAM_INT_TBL_ENABLE

#define IWM_CSR_DRAM_INT_TBL_ENABLE (1U << 31)

Definition at line 419 of file if_iwmreg.h.

◆ IWM_CSR_DRAM_INT_TBL_REG

#define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)

Definition at line 143 of file if_iwmreg.h.

◆ IWM_CSR_EEPROM_GP

#define IWM_CSR_EEPROM_GP (0x030)

Definition at line 123 of file if_iwmreg.h.

◆ IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP

#define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)

Definition at line 338 of file if_iwmreg.h.

◆ IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP

#define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)

Definition at line 337 of file if_iwmreg.h.

◆ IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K

#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)

Definition at line 339 of file if_iwmreg.h.

◆ IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K

#define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)

Definition at line 340 of file if_iwmreg.h.

◆ IWM_CSR_EEPROM_GP_IF_OWNER_MSK

#define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)

Definition at line 336 of file if_iwmreg.h.

◆ IWM_CSR_EEPROM_GP_VALID_MSK

#define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */

Definition at line 335 of file if_iwmreg.h.

◆ IWM_CSR_EEPROM_REG

#define IWM_CSR_EEPROM_REG (0x02c)

Definition at line 122 of file if_iwmreg.h.

◆ IWM_CSR_EEPROM_REG_BIT_CMD

#define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)

Definition at line 330 of file if_iwmreg.h.

◆ IWM_CSR_EEPROM_REG_MSK_ADDR

#define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)

Definition at line 331 of file if_iwmreg.h.

◆ IWM_CSR_EEPROM_REG_MSK_DATA

#define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)

Definition at line 332 of file if_iwmreg.h.

◆ IWM_CSR_EEPROM_REG_READ_VALID_MSK

#define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)

Definition at line 329 of file if_iwmreg.h.

◆ IWM_CSR_FH_INT_BIT_ERR

#define IWM_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */

Definition at line 219 of file if_iwmreg.h.

◆ IWM_CSR_FH_INT_BIT_HI_PRIOR

#define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */

Definition at line 220 of file if_iwmreg.h.

◆ IWM_CSR_FH_INT_BIT_RX_CHNL0

#define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */

Definition at line 222 of file if_iwmreg.h.

◆ IWM_CSR_FH_INT_BIT_RX_CHNL1

#define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */

Definition at line 221 of file if_iwmreg.h.

◆ IWM_CSR_FH_INT_BIT_TX_CHNL0

#define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */

Definition at line 224 of file if_iwmreg.h.

◆ IWM_CSR_FH_INT_BIT_TX_CHNL1

#define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */

Definition at line 223 of file if_iwmreg.h.

◆ IWM_CSR_FH_INT_RX_MASK

#define IWM_CSR_FH_INT_RX_MASK

Value:

                                (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
                                IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
                                IWM_CSR_FH_INT_BIT_RX_CHNL0)

Definition at line 226 of file if_iwmreg.h.

◆ IWM_CSR_FH_INT_STATUS

#define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/

Definition at line 98 of file if_iwmreg.h.

◆ IWM_CSR_FH_INT_TX_MASK

#define IWM_CSR_FH_INT_TX_MASK

Value:

(IWM_CSR_FH_INT_BIT_TX_CHNL1 | \

IWM_CSR_FH_INT_BIT_TX_CHNL0)

IWM_CSR_FH_INT_BIT_TX_CHNL1

#define IWM_CSR_FH_INT_BIT_TX_CHNL1

Definition: if_iwmreg.h:223

Definition at line 230 of file if_iwmreg.h.

◆ IWM_CSR_GIO_CHICKEN_BITS

#define IWM_CSR_GIO_CHICKEN_BITS (0x100)

Definition at line 148 of file if_iwmreg.h.

◆ IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER

#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)

Definition at line 405 of file if_iwmreg.h.

◆ IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX

#define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)

Definition at line 404 of file if_iwmreg.h.

◆ IWM_CSR_GIO_REG

#define IWM_CSR_GIO_REG (0x03C)

Definition at line 126 of file if_iwmreg.h.

◆ IWM_CSR_GIO_REG_VAL_L0S_ENABLED

#define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)

Definition at line 357 of file if_iwmreg.h.

◆ IWM_CSR_GP_CNTRL

#define IWM_CSR_GP_CNTRL (0x024)

Definition at line 101 of file if_iwmreg.h.

◆ IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP

#define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)

Definition at line 287 of file if_iwmreg.h.

◆ IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW

#define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)

Definition at line 293 of file if_iwmreg.h.

◆ IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE

#define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)

Definition at line 285 of file if_iwmreg.h.

◆ IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ

#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)

Definition at line 286 of file if_iwmreg.h.

◆ IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY

#define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)

Definition at line 284 of file if_iwmreg.h.

◆ IWM_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN

#define IWM_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)

Definition at line 292 of file if_iwmreg.h.

◆ IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE

#define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)

Definition at line 291 of file if_iwmreg.h.

◆ IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN

#define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)

Definition at line 289 of file if_iwmreg.h.

◆ IWM_CSR_GP_DRIVER_REG

#define IWM_CSR_GP_DRIVER_REG (0x050)

Definition at line 128 of file if_iwmreg.h.

◆ IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2

#define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)

Definition at line 399 of file if_iwmreg.h.

◆ IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6

#define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)

Definition at line 398 of file if_iwmreg.h.

◆ IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER

#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)

Definition at line 401 of file if_iwmreg.h.

◆ IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB

#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)

Definition at line 396 of file if_iwmreg.h.

◆ IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA

#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)

Definition at line 397 of file if_iwmreg.h.

◆ IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB

#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)

Definition at line 395 of file if_iwmreg.h.

◆ IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK

#define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)

Definition at line 394 of file if_iwmreg.h.

◆ IWM_CSR_GP_REG_MAC_POWER_SAVE

#define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)

Definition at line 351 of file if_iwmreg.h.

◆ IWM_CSR_GP_REG_NO_POWER_SAVE

#define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)

Definition at line 350 of file if_iwmreg.h.

◆ IWM_CSR_GP_REG_PHY_POWER_SAVE

#define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)

Definition at line 352 of file if_iwmreg.h.

◆ IWM_CSR_GP_REG_POWER_SAVE_ERROR

#define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)

Definition at line 353 of file if_iwmreg.h.

◆ IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK

#define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */

Definition at line 349 of file if_iwmreg.h.

◆ IWM_CSR_GP_UCODE_REG

#define IWM_CSR_GP_UCODE_REG (0x048)

Definition at line 127 of file if_iwmreg.h.

◆ IWM_CSR_GPIO_IN

#define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */

Definition at line 99 of file if_iwmreg.h.

◆ IWM_CSR_GPIO_IN_BIT_AUX_POWER

#define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)

Definition at line 234 of file if_iwmreg.h.

◆ IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC

#define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)

Definition at line 235 of file if_iwmreg.h.

◆ IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC

#define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)

Definition at line 236 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG

#define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */

Definition at line 94 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM

#define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)

Definition at line 184 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A

#define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)

Definition at line 183 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI

#define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)

Definition at line 170 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE

#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */

Definition at line 186 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY

#define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */

Definition at line 185 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI

#define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)

Definition at line 171 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME

#define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)

Definition at line 188 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER

#define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)

Definition at line 169 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH

#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)

Definition at line 167 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP

#define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)

Definition at line 168 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH

#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)

Definition at line 173 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP

#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)

Definition at line 174 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE

#define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)

Definition at line 172 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE

#define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */

Definition at line 189 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER

#define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)

Definition at line 178 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH

#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)

Definition at line 176 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP

#define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)

Definition at line 177 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH

#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)

Definition at line 180 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP

#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)

Definition at line 181 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE

#define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)

Definition at line 179 of file if_iwmreg.h.

◆ IWM_CSR_HW_IF_CONFIG_REG_PREPARE

#define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */

Definition at line 187 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV

#define IWM_CSR_HW_REV (0x028)

Definition at line 114 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_DASH

#define IWM_CSR_HW_REV_DASH ( _val ) (((_val) & 0x0000003) >> 0)

Definition at line 297 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_STEP

#define IWM_CSR_HW_REV_STEP ( _val ) (((_val) & 0x000000C) >> 2)

Definition at line 298 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_1000

#define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)

Definition at line 314 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_105

#define IWM_CSR_HW_REV_TYPE_105 (0x0000110)

Definition at line 323 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_135

#define IWM_CSR_HW_REV_TYPE_135 (0x0000120)

Definition at line 324 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_2x00

#define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)

Definition at line 322 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_2x30

#define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)

Definition at line 321 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_5100

#define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)

Definition at line 312 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_5150

#define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)

Definition at line 313 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_5300

#define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)

Definition at line 310 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_5350

#define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)

Definition at line 311 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_6150

#define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)

Definition at line 317 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_6x00

#define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)

Definition at line 315 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_6x05

#define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)

Definition at line 318 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_6x30

#define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05

Definition at line 319 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_6x35

#define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05

Definition at line 320 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_6x50

#define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)

Definition at line 316 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_7265D

#define IWM_CSR_HW_REV_TYPE_7265D (0x0000210)

Definition at line 325 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_MSK

#define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)

Definition at line 309 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_TYPE_NONE

#define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)

Definition at line 326 of file if_iwmreg.h.

◆ IWM_CSR_HW_REV_WA_REG

#define IWM_CSR_HW_REV_WA_REG (0x22C)

Definition at line 161 of file if_iwmreg.h.

◆ IWM_CSR_INI_SET_MASK

#define IWM_CSR_INI_SET_MASK

Value:

                                 (IWM_CSR_INT_BIT_FH_RX   | \
                                 IWM_CSR_INT_BIT_HW_ERR  | \
                                 IWM_CSR_INT_BIT_FH_TX   | \
                                 IWM_CSR_INT_BIT_SW_ERR  | \
                                 IWM_CSR_INT_BIT_RF_KILL | \
                                 IWM_CSR_INT_BIT_SW_RX   | \
                                 IWM_CSR_INT_BIT_WAKEUP  | \
                                 IWM_CSR_INT_BIT_ALIVE   | \
                                 IWM_CSR_INT_BIT_RX_PERIODIC)

Definition at line 208 of file if_iwmreg.h.

◆ IWM_CSR_INT

#define IWM_CSR_INT (0x008) /* host interrupt status/ack */

Definition at line 96 of file if_iwmreg.h.

◆ IWM_CSR_INT_BIT_ALIVE

#define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */

Definition at line 206 of file if_iwmreg.h.

◆ IWM_CSR_INT_BIT_CT_KILL

#define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */

Definition at line 203 of file if_iwmreg.h.

◆ IWM_CSR_INT_BIT_FH_RX

#define IWM_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */

Definition at line 196 of file if_iwmreg.h.

◆ IWM_CSR_INT_BIT_FH_TX

#define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */

Definition at line 199 of file if_iwmreg.h.

◆ IWM_CSR_INT_BIT_HW_ERR

#define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */

Definition at line 197 of file if_iwmreg.h.

◆ IWM_CSR_INT_BIT_RF_KILL

#define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */

Definition at line 202 of file if_iwmreg.h.

◆ IWM_CSR_INT_BIT_RX_PERIODIC

#define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */

Definition at line 198 of file if_iwmreg.h.

◆ IWM_CSR_INT_BIT_SCD

#define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */

Definition at line 200 of file if_iwmreg.h.

◆ IWM_CSR_INT_BIT_SW_ERR

#define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */

Definition at line 201 of file if_iwmreg.h.

◆ IWM_CSR_INT_BIT_SW_RX

#define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */

Definition at line 204 of file if_iwmreg.h.

◆ IWM_CSR_INT_BIT_WAKEUP

#define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */

Definition at line 205 of file if_iwmreg.h.

◆ IWM_CSR_INT_COALESCING

#define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */

Definition at line 95 of file if_iwmreg.h.

◆ IWM_CSR_INT_MASK

#define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */

Definition at line 97 of file if_iwmreg.h.

◆ IWM_CSR_INT_PERIODIC_DIS

#define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/

Definition at line 191 of file if_iwmreg.h.

◆ IWM_CSR_INT_PERIODIC_ENA

#define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/

Definition at line 192 of file if_iwmreg.h.

◆ IWM_CSR_INT_PERIODIC_REG

#define IWM_CSR_INT_PERIODIC_REG (0x005)

Definition at line 104 of file if_iwmreg.h.

◆ IWM_CSR_LED_BSM_CTRL_MSK

#define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)

Definition at line 408 of file if_iwmreg.h.

◆ IWM_CSR_LED_REG

#define IWM_CSR_LED_REG (0x094)

Definition at line 142 of file if_iwmreg.h.

◆ IWM_CSR_LED_REG_TURN_OFF

#define IWM_CSR_LED_REG_TURN_OFF (0x20)

Definition at line 410 of file if_iwmreg.h.

◆ IWM_CSR_LED_REG_TURN_ON

#define IWM_CSR_LED_REG_TURN_ON (0x60)

Definition at line 409 of file if_iwmreg.h.

◆ IWM_CSR_MAC_SHADOW_REG_CTRL

#define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */

Definition at line 144 of file if_iwmreg.h.

◆ IWM_CSR_MBOX_SET_REG

#define IWM_CSR_MBOX_SET_REG (0x088)

Definition at line 139 of file if_iwmreg.h.

◆ IWM_CSR_MBOX_SET_REG_OS_ALIVE

#define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20

Definition at line 140 of file if_iwmreg.h.

◆ IWM_CSR_MSIX_AUTOMASK_ST_AD

#define IWM_CSR_MSIX_AUTOMASK_ST_AD (IWM_CSR_MSIX_BASE + 0x810)

Definition at line 699 of file if_iwmreg.h.

◆ IWM_CSR_MSIX_BASE

#define IWM_CSR_MSIX_BASE (0x2000)

Definition at line 694 of file if_iwmreg.h.

◆ IWM_CSR_MSIX_FH_INT_CAUSES_AD

#define IWM_CSR_MSIX_FH_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x800)

Definition at line 695 of file if_iwmreg.h.

◆ IWM_CSR_MSIX_FH_INT_MASK_AD

#define IWM_CSR_MSIX_FH_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x804)

Definition at line 696 of file if_iwmreg.h.

◆ IWM_CSR_MSIX_HW_INT_CAUSES_AD

#define IWM_CSR_MSIX_HW_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x808)

Definition at line 697 of file if_iwmreg.h.

◆ IWM_CSR_MSIX_HW_INT_MASK_AD

#define IWM_CSR_MSIX_HW_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x80C)

Definition at line 698 of file if_iwmreg.h.

◆ IWM_CSR_MSIX_IVAR

#define IWM_CSR_MSIX_IVAR ( cause ) (IWM_CSR_MSIX_IVAR_AD_REG + (cause))

Definition at line 704 of file if_iwmreg.h.

◆ IWM_CSR_MSIX_IVAR_AD_REG

#define IWM_CSR_MSIX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x890)

Definition at line 701 of file if_iwmreg.h.

◆ IWM_CSR_MSIX_PENDING_PBA_AD

#define IWM_CSR_MSIX_PENDING_PBA_AD (IWM_CSR_MSIX_BASE + 0x1000)

Definition at line 702 of file if_iwmreg.h.

◆ IWM_CSR_MSIX_RX_IVAR

#define IWM_CSR_MSIX_RX_IVAR ( cause ) (IWM_CSR_MSIX_RX_IVAR_AD_REG + (cause))

Definition at line 703 of file if_iwmreg.h.

◆ IWM_CSR_MSIX_RX_IVAR_AD_REG

#define IWM_CSR_MSIX_RX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x880)

Definition at line 700 of file if_iwmreg.h.

◆ IWM_CSR_OTP_GP_REG

#define IWM_CSR_OTP_GP_REG (0x034)

Definition at line 124 of file if_iwmreg.h.

◆ IWM_CSR_OTP_GP_REG_DEVICE_SELECT

#define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */

Definition at line 343 of file if_iwmreg.h.

◆ IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK

#define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */

Definition at line 345 of file if_iwmreg.h.

◆ IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK

#define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */

Definition at line 346 of file if_iwmreg.h.

◆ IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE

#define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */

Definition at line 344 of file if_iwmreg.h.

◆ IWM_CSR_RESET

#define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/

Definition at line 100 of file if_iwmreg.h.

◆ IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED

#define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)

Definition at line 244 of file if_iwmreg.h.

◆ IWM_CSR_RESET_REG_FLAG_FORCE_NMI

#define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)

Definition at line 240 of file if_iwmreg.h.

◆ IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED

#define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)

Definition at line 242 of file if_iwmreg.h.

◆ IWM_CSR_RESET_REG_FLAG_NEVO_RESET

#define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)

Definition at line 239 of file if_iwmreg.h.

◆ IWM_CSR_RESET_REG_FLAG_STOP_MASTER

#define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)

Definition at line 243 of file if_iwmreg.h.

◆ IWM_CSR_RESET_REG_FLAG_SW_RESET

#define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)

Definition at line 241 of file if_iwmreg.h.

◆ IWM_CSR_SECURE_BOOT_CONFIG_ADDR

#define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)

Definition at line 424 of file if_iwmreg.h.

◆ IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP

#define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP 0x00000001

Definition at line 425 of file if_iwmreg.h.

◆ IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ

#define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ 0x00000002

Definition at line 426 of file if_iwmreg.h.

◆ IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR

#define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)

Definition at line 427 of file if_iwmreg.h.

◆ IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR

#define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)

Definition at line 428 of file if_iwmreg.h.

◆ IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL

#define IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL 0x00000010

Definition at line 433 of file if_iwmreg.h.

◆ IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED

#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED 0x00000002

Definition at line 430 of file if_iwmreg.h.

◆ IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL

#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL 0x00000008

Definition at line 432 of file if_iwmreg.h.

◆ IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS

#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS 0x00000003

Definition at line 429 of file if_iwmreg.h.

◆ IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS

#define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS 0x00000004

Definition at line 431 of file if_iwmreg.h.

◆ IWM_CSR_SECURE_TIME_OUT

#define IWM_CSR_SECURE_TIME_OUT (100)

Definition at line 550 of file if_iwmreg.h.

◆ IWM_CSR_UCODE_DRV_GP1

#define IWM_CSR_UCODE_DRV_GP1 (0x054)

Definition at line 134 of file if_iwmreg.h.

◆ IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED

#define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)

Definition at line 389 of file if_iwmreg.h.

◆ IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE

#define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)

Definition at line 391 of file if_iwmreg.h.

◆ IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP

#define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)

Definition at line 387 of file if_iwmreg.h.

◆ IWM_CSR_UCODE_DRV_GP1_CLR

#define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)

Definition at line 136 of file if_iwmreg.h.

◆ IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT

#define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)

Definition at line 390 of file if_iwmreg.h.

◆ IWM_CSR_UCODE_DRV_GP1_SET

#define IWM_CSR_UCODE_DRV_GP1_SET (0x058)

Definition at line 135 of file if_iwmreg.h.

◆ IWM_CSR_UCODE_DRV_GP2

#define IWM_CSR_UCODE_DRV_GP2 (0x060)

Definition at line 137 of file if_iwmreg.h.

◆ IWM_CSR_UCODE_SW_BIT_RFKILL

#define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)

Definition at line 388 of file if_iwmreg.h.

◆ IWM_CT_KILL_CARD_DISABLED

#define IWM_CT_KILL_CARD_DISABLED 0x04

Definition at line 3433 of file if_iwmreg.h.

◆ IWM_CT_KILL_NOTIFICATION

#define IWM_CT_KILL_NOTIFICATION 0xFE

Definition at line 2136 of file if_iwmreg.h.

◆ IWM_CTDP_CONFIG_CMD

#define IWM_CTDP_CONFIG_CMD 0x03

Definition at line 2134 of file if_iwmreg.h.

◆ IWM_D3_CONFIG_CMD

#define IWM_D3_CONFIG_CMD 0xd3

Definition at line 2106 of file if_iwmreg.h.

◆ IWM_DATA_PATH_GROUP

#define IWM_DATA_PATH_GROUP 0x5

Definition at line 2145 of file if_iwmreg.h.

◆ IWM_DBG_CFG

#define IWM_DBG_CFG 0x9

Definition at line 1988 of file if_iwmreg.h.

◆ IWM_DEBUG_LOG_MSG

#define IWM_DEBUG_LOG_MSG 0xf7

Definition at line 2101 of file if_iwmreg.h.

◆ IWM_DEF_CMD_PAYLOAD_SIZE

#define IWM_DEF_CMD_PAYLOAD_SIZE 320

Definition at line 6880 of file if_iwmreg.h.

◆ IWM_DEFAULT_MAX_PROBE_LENGTH

#define IWM_DEFAULT_MAX_PROBE_LENGTH 200

Definition at line 974 of file if_iwmreg.h.

◆ IWM_DEFAULT_PS_RX_DATA_TIMEOUT

#define IWM_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000)

Definition at line 4308 of file if_iwmreg.h.

◆ IWM_DEFAULT_PS_TX_DATA_TIMEOUT

#define IWM_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000)

Definition at line 4307 of file if_iwmreg.h.

◆ IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE

#define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18

Definition at line 969 of file if_iwmreg.h.

◆ IWM_DEFAULT_TX_RETRY

#define IWM_DEFAULT_TX_RETRY 15

Definition at line 4914 of file if_iwmreg.h.

◆ IWM_DEVICE_POWER_FLAGS_CAM_MSK

#define IWM_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13)

Definition at line 4223 of file if_iwmreg.h.

◆ IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK

#define IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)

Masks for device power command flags @IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off receiver and transmitter. '0' Do not allow. This flag should be always set to '1' unless one needs to disable actual power down for debug purposes. @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, power management is disabled. '0' Power management is enabled, one of the power schemes is applied.

Definition at line 4222 of file if_iwmreg.h.

◆ IWM_DEVICE_SET_NMI_8000_REG

#define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24

Definition at line 1241 of file if_iwmreg.h.

◆ IWM_DEVICE_SET_NMI_8000_VAL

#define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000

Definition at line 1242 of file if_iwmreg.h.

◆ IWM_DEVICE_SET_NMI_REG

#define IWM_DEVICE_SET_NMI_REG 0x00a01c30

Definition at line 1238 of file if_iwmreg.h.

◆ IWM_DEVICE_SET_NMI_VAL_DRV

#define IWM_DEVICE_SET_NMI_VAL_DRV 0x80

Definition at line 1240 of file if_iwmreg.h.

◆ IWM_DEVICE_SET_NMI_VAL_HW

#define IWM_DEVICE_SET_NMI_VAL_HW 0x01

Definition at line 1239 of file if_iwmreg.h.

◆ IWM_DEVICE_SYSTEM_TIME_REG

#define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C

Definition at line 1235 of file if_iwmreg.h.

◆ IWM_DQA_AP_PROBE_RESP_QUEUE

#define IWM_DQA_AP_PROBE_RESP_QUEUE 9

Definition at line 1956 of file if_iwmreg.h.

◆ IWM_DQA_AUX_QUEUE

#define IWM_DQA_AUX_QUEUE 1

Definition at line 1949 of file if_iwmreg.h.

◆ IWM_DQA_BSS_CLIENT_QUEUE

#define IWM_DQA_BSS_CLIENT_QUEUE 4

Definition at line 1953 of file if_iwmreg.h.

◆ IWM_DQA_CMD_QUEUE

#define IWM_DQA_CMD_QUEUE 0

DQA - Dynamic Queue Allocation -introduction

Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi to allow dynamic allocation of queues on-demand, rather than allocate them statically ahead of time. Ideally, we would like to allocate one queue per RA/TID, thus allowing an AP - for example - to send BE traffic to STA2 even if it also needs to send traffic to a sleeping STA1, without being blocked by the sleeping station.

Although the queues in DQA mode are dynamically allocated, there are still some queues that are statically allocated: TXQ #0 - command queue TXQ #1 - aux frames TXQ #2 - P2P device frames TXQ #3 - P2P GO/SoftAP GCAST/BCAST frames TXQ #4 - BSS DATA frames queue TXQ #5-8 - non-QoS data, QoS no-data, and MGMT frames queue pool TXQ #9 - P2P GO/SoftAP probe responses TXQ #10-31 - QoS DATA frames queue pool (for Tx aggregation)

Definition at line 1948 of file if_iwmreg.h.

◆ IWM_DQA_ENABLE_CMD

#define IWM_DQA_ENABLE_CMD 0x00

Definition at line 2156 of file if_iwmreg.h.

◆ IWM_DQA_GCAST_QUEUE

#define IWM_DQA_GCAST_QUEUE 3

Definition at line 1952 of file if_iwmreg.h.

◆ IWM_DQA_INJECT_MONITOR_QUEUE

#define IWM_DQA_INJECT_MONITOR_QUEUE 2

Definition at line 1951 of file if_iwmreg.h.

◆ IWM_DQA_MAX_DATA_QUEUE

#define IWM_DQA_MAX_DATA_QUEUE 31

Definition at line 1958 of file if_iwmreg.h.

◆ IWM_DQA_MAX_MGMT_QUEUE

#define IWM_DQA_MAX_MGMT_QUEUE 8

Definition at line 1955 of file if_iwmreg.h.

◆ IWM_DQA_MIN_DATA_QUEUE

#define IWM_DQA_MIN_DATA_QUEUE 10

Definition at line 1957 of file if_iwmreg.h.

◆ IWM_DQA_MIN_MGMT_QUEUE

#define IWM_DQA_MIN_MGMT_QUEUE 5

Definition at line 1954 of file if_iwmreg.h.

◆ IWM_DQA_P2P_DEVICE_QUEUE

#define IWM_DQA_P2P_DEVICE_QUEUE 2

Definition at line 1950 of file if_iwmreg.h.

◆ IWM_DTS_DIODE_REG_DIG_VAL

#define IWM_DTS_DIODE_REG_DIG_VAL 0x000000FF /* bits [7:0] */

Definition at line 678 of file if_iwmreg.h.

◆ IWM_DTS_DIODE_REG_FLAGS_MSK

#define IWM_DTS_DIODE_REG_FLAGS_MSK 0xFF000000 /* bits [31:24] */

Definition at line 683 of file if_iwmreg.h.

◆ IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE

#define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE 0x00000080 /* bits [7:7] */

Definition at line 688 of file if_iwmreg.h.

◆ IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS

#define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS 7

Definition at line 687 of file if_iwmreg.h.

◆ IWM_DTS_DIODE_REG_FLAGS_VREFS_ID

#define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID 0x00000003 /* bits [1:0] */

Definition at line 686 of file if_iwmreg.h.

◆ IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS

#define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS 0

Definition at line 685 of file if_iwmreg.h.

◆ IWM_DTS_DIODE_REG_PASS_ONCE

#define IWM_DTS_DIODE_REG_PASS_ONCE 0x80000000 /* bits [31:31] */

Definition at line 682 of file if_iwmreg.h.

◆ IWM_DTS_DIODE_REG_VREF_HIGH

#define IWM_DTS_DIODE_REG_VREF_HIGH 0x00FF0000 /* bits [23:16] */

Definition at line 680 of file if_iwmreg.h.

◆ IWM_DTS_DIODE_REG_VREF_ID

#define IWM_DTS_DIODE_REG_VREF_ID 0x03000000 /* bits [25:24] */

Definition at line 681 of file if_iwmreg.h.

◆ IWM_DTS_DIODE_REG_VREF_LOW

#define IWM_DTS_DIODE_REG_VREF_LOW 0x0000FF00 /* bits [15:8] */

Definition at line 679 of file if_iwmreg.h.

◆ IWM_DTS_MEASUREMENT_NOTIF_WIDE

#define IWM_DTS_MEASUREMENT_NOTIF_WIDE 0xFF

Definition at line 2137 of file if_iwmreg.h.

◆ IWM_DTS_MEASUREMENT_NOTIFICATION

#define IWM_DTS_MEASUREMENT_NOTIFICATION 0xdd

Definition at line 2098 of file if_iwmreg.h.

◆ IWM_DTSC_CFG_MODE

#define IWM_DTSC_CFG_MODE (0x00a10604)

Definition at line 1257 of file if_iwmreg.h.

◆ IWM_DTSC_CFG_MODE_PERIODIC

#define IWM_DTSC_CFG_MODE_PERIODIC (0x2)

Definition at line 1260 of file if_iwmreg.h.

◆ IWM_DTSC_PTAT_AVG

#define IWM_DTSC_PTAT_AVG (0x00a10650)

Definition at line 1261 of file if_iwmreg.h.

◆ IWM_DTSC_VREF5_AVG

#define IWM_DTSC_VREF5_AVG (0x00a1064c)

Definition at line 1259 of file if_iwmreg.h.

◆ IWM_DTSC_VREF_AVG

#define IWM_DTSC_VREF_AVG (0x00a10648)

Definition at line 1258 of file if_iwmreg.h.

◆ IWM_DUMP_TX_FIFO_FLUSH

#define IWM_DUMP_TX_FIFO_FLUSH (1 << 1)

dump (flush) control flags @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty and the TFD queues are empty.

Definition at line 5266 of file if_iwmreg.h.

◆ IWM_ENABLE_WFPM

#define IWM_ENABLE_WFPM 0x80000000

Definition at line 619 of file if_iwmreg.h.

◆ IWM_FAST_SCHED_SCAN_ITERATIONS

#define IWM_FAST_SCHED_SCAN_ITERATIONS 3

Definition at line 5395 of file if_iwmreg.h.

◆ IWM_FH_KW_MEM_ADDR_REG

#define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)

Keep-Warm (KW) buffer base address.

Driver must allocate a 4KByte buffer that is for keeping the host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency DRAM access when doing Txing or Rxing. The dummy accesses prevent host from going into a power-savings mode that would cause higher DRAM latency, and possible data over/under-runs, before all Tx/Rx is complete.

Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) of the buffer, which must be 4K aligned. Once this is set up, the device automatically invokes keep-warm accesses when normal accesses might not be sufficient to maintain fast DRAM response.

Bit fields: 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned

Definition at line 1465 of file if_iwmreg.h.

◆ IWM_FH_MEM_CBBC_0_15_LOWER_BOUND

#define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)

TFD Circular Buffers Base (CBBC) addresses

Device has 16 base pointer registers, one for each of 16 host-DRAM-resident circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04 bytes from one another. Each TFD circular buffer in DRAM must be 256-byte aligned (address bits 0-7 must be 0). Later devices have 20 (5000 series) or 30 (higher) queues, but the registers for them are in different places.

Bit fields in each pointer register: 27-0: TFD CB physical base address [35:8], must be 256-byte aligned

Definition at line 1482 of file if_iwmreg.h.

◆ IWM_FH_MEM_CBBC_0_15_UPPER_BOUN

#define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)

Definition at line 1483 of file if_iwmreg.h.

◆ IWM_FH_MEM_CBBC_16_19_LOWER_BOUND

#define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)

Definition at line 1484 of file if_iwmreg.h.

◆ IWM_FH_MEM_CBBC_16_19_UPPER_BOUND

#define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)

Definition at line 1485 of file if_iwmreg.h.

◆ IWM_FH_MEM_CBBC_20_31_LOWER_BOUND

#define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)

Definition at line 1486 of file if_iwmreg.h.

◆ IWM_FH_MEM_CBBC_20_31_UPPER_BOUND

#define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)

Definition at line 1487 of file if_iwmreg.h.

◆ IWM_FH_MEM_LOWER_BOUND

#define IWM_FH_MEM_LOWER_BOUND (0x1000)

This I/O area is directly read/writable by driver (e.g. Linux uses writel()) Addresses are offsets from device's PCI hardware base address.

Definition at line 1445 of file if_iwmreg.h.

◆ IWM_FH_MEM_RCSR_CHNL0

#define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)

Definition at line 1627 of file if_iwmreg.h.

◆ IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG

#define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)

Definition at line 1629 of file if_iwmreg.h.

◆ IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ

#define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)

Definition at line 1631 of file if_iwmreg.h.

◆ IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR

#define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)

Definition at line 1630 of file if_iwmreg.h.

◆ IWM_FH_MEM_RCSR_LOWER_BOUND

#define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)

Rx Config/Status Registers (RCSR) Rx Config Reg for channel 0 (only channel used)

Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for normal operation (see bit fields).

Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.

Bit fields: 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, '10' operate normally 29-24: reserved 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), min "5" for 32 RBDs, max "12" for 4096 RBDs. 19-18: reserved 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, '10' 12K, '11' 16K. 15-14: reserved 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) typical value 0x10 (about 1/2 msec) 3- 0: reserved

Definition at line 1625 of file if_iwmreg.h.

◆ IWM_FH_MEM_RCSR_UPPER_BOUND

#define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)

Definition at line 1626 of file if_iwmreg.h.

◆ IWM_FH_MEM_RSCSR_CHNL0

#define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)

Definition at line 1571 of file if_iwmreg.h.

◆ IWM_FH_MEM_RSCSR_LOWER_BOUND

#define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)

Rx SRAM Control and Status Registers (RSCSR)

These registers provide handshake between driver and device for the Rx queue (this queue handles all command responses, notifications, Rx data, etc. sent from uCode to host driver). Unlike Tx, there is only one Rx queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 mapping between RBDs and RBs.

Driver must allocate host DRAM memory for the following, and set the physical address of each into device registers:

1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 entries (although any power of 2, up to 4096, is selectable by driver). Each entry (1 dword) points to a receive buffer (RB) of consistent size (typically 4K, although 8K or 16K are also selectable by driver). Driver sets up RB size and number of RBDs in the CB via Rx config register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.

Bit fields within one RBD: 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned

Driver sets physical address [35:8] of base of RBD circular buffer into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].

2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers (RBs) have been filled, via a "write pointer", actually the index of the RB's corresponding RBD within the circular buffer. Driver sets physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].

Bit fields in lower dword of Rx status buffer (upper dword not used by driver: 31-12: Not used by driver 11- 0: Index of last filled Rx buffer descriptor (device writes, driver reads this value)

As the driver prepares Receive Buffers (RBs) for device to fill, driver must enter pointers to these RBs into contiguous RBD circular buffer entries, and update the device's "write" index register, IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.

This "write" index corresponds to the next RBD that the driver will make available, i.e. one RBD past the tail of the ready-to-fill RBDs within the circular buffer. This value should initially be 0 (before preparing any RBs), should be 8 after preparing the first 8 RBs (for example), and must wrap back to 0 at the end of the circular buffer (but don't wrap before "read" index has advanced past 1! See below). NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.

As the device fills RBs (referenced from contiguous RBDs within the circular buffer), it updates the Rx status buffer in host DRAM, 2) described above, to tell the driver the index of the latest filled RBD. The driver must read this "read" index from DRAM after receiving an Rx interrupt from device

The driver must also internally keep track of a third index, which is the next RBD to process. When receiving an Rx interrupt, driver should process all filled but unprocessed RBs up to, but not including, the RB corresponding to the "read" index. For example, if "read" index becomes "1", driver may process the RB pointed to by RBD 0. Depending on volume of traffic, there may be many RBs to process.

If read index == write index, device thinks there is no room to put new data. Due to this, the maximum number of filled RBs is 255, instead of 256. To be safe, make sure that there is a gap of at least 2 RBDs between "write" and "read" indexes; that is, make sure that there are no more than 254 buffers waiting to be filled.

Definition at line 1569 of file if_iwmreg.h.

◆ IWM_FH_MEM_RSCSR_UPPER_BOUND

#define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)

Definition at line 1570 of file if_iwmreg.h.

◆ IWM_FH_MEM_RSSR_LOWER_BOUND

#define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)

Rx Shared Status Registers (RSSR)

After stopping Rx DMA channel (writing 0 to IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.

Bit fields: 24: 1 = Channel 0 is idle

IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV contain default values that should not be altered by the driver.

Definition at line 1670 of file if_iwmreg.h.

◆ IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV

#define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)

Definition at line 1675 of file if_iwmreg.h.

◆ IWM_FH_MEM_RSSR_RX_STATUS_REG

#define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)

Definition at line 1674 of file if_iwmreg.h.

◆ IWM_FH_MEM_RSSR_SHARED_CTRL_REG

#define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)

Definition at line 1673 of file if_iwmreg.h.

◆ IWM_FH_MEM_RSSR_UPPER_BOUND

#define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)

Definition at line 1671 of file if_iwmreg.h.

◆ IWM_FH_MEM_TB_MAX_LENGTH

#define IWM_FH_MEM_TB_MAX_LENGTH 0x20000

Definition at line 437 of file if_iwmreg.h.

◆ IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK

#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)

Definition at line 1683 of file if_iwmreg.h.

◆ IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT

#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28

Definition at line 1680 of file if_iwmreg.h.

◆ IWM_FH_MEM_UPPER_BOUND

#define IWM_FH_MEM_UPPER_BOUND (0x2000)

Definition at line 1446 of file if_iwmreg.h.

◆ IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK

#define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/

Definition at line 1638 of file if_iwmreg.h.

◆ IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL

#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)

Definition at line 1655 of file if_iwmreg.h.

◆ IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK

#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */

Definition at line 1634 of file if_iwmreg.h.

◆ IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL

#define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)

Definition at line 1654 of file if_iwmreg.h.

◆ IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK

#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */

Definition at line 1636 of file if_iwmreg.h.

◆ IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK

#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */

Definition at line 1633 of file if_iwmreg.h.

◆ IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK

#define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */

Definition at line 1637 of file if_iwmreg.h.

◆ IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK

#define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */

Definition at line 1635 of file if_iwmreg.h.

◆ IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY

#define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)

Definition at line 1653 of file if_iwmreg.h.

◆ IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL

#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)

Definition at line 1646 of file if_iwmreg.h.

◆ IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL

#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)

Definition at line 1645 of file if_iwmreg.h.

◆ IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL

#define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)

Definition at line 1644 of file if_iwmreg.h.

◆ IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS

#define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)

Definition at line 1640 of file if_iwmreg.h.

◆ IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS

#define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)

Definition at line 1641 of file if_iwmreg.h.

◆ IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K

#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)

Definition at line 1650 of file if_iwmreg.h.

◆ IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K

#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)

Definition at line 1651 of file if_iwmreg.h.

◆ IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K

#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)

Definition at line 1648 of file if_iwmreg.h.

◆ IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K

#define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)

Definition at line 1649 of file if_iwmreg.h.

◆ IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG

#define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)

Physical base address of Rx Buffer Descriptor Circular Buffer. Bit fields: 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.

Definition at line 1585 of file if_iwmreg.h.

◆ IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG

#define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)

Rx write pointer (index, really!). Bit fields: 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. NOTE: For 256-entry circular buffer, use only bits [7:0].

Definition at line 1593 of file if_iwmreg.h.

◆ IWM_FH_RSCSR_CHNL0_RDPTR

#define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG

Definition at line 1597 of file if_iwmreg.h.

◆ IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG

#define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)

Physical base address of 8-byte Rx Status buffer. Bit fields: 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.

Definition at line 1578 of file if_iwmreg.h.

◆ IWM_FH_RSCSR_CHNL0_WPTR

#define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)

Definition at line 1594 of file if_iwmreg.h.

◆ IWM_FH_RSCSR_FRAME_ALIGN

#define IWM_FH_RSCSR_FRAME_ALIGN 0x40

Definition at line 6930 of file if_iwmreg.h.

◆ IWM_FH_RSCSR_FRAME_INVALID

#define IWM_FH_RSCSR_FRAME_INVALID 0x55550000

Definition at line 6929 of file if_iwmreg.h.

◆ IWM_FH_RSCSR_FRAME_SIZE_MSK

#define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff

Definition at line 6928 of file if_iwmreg.h.

◆ IWM_FH_RSCSR_RADA_EN

#define IWM_FH_RSCSR_RADA_EN (1 << 26)

Definition at line 6932 of file if_iwmreg.h.

◆ IWM_FH_RSCSR_RPA_EN

#define IWM_FH_RSCSR_RPA_EN (1 << 25)

Definition at line 6931 of file if_iwmreg.h.

◆ IWM_FH_RSCSR_RXQ_MASK

#define IWM_FH_RSCSR_RXQ_MASK 0x3F0000

Definition at line 6934 of file if_iwmreg.h.

◆ IWM_FH_RSCSR_RXQ_POS

#define IWM_FH_RSCSR_RXQ_POS 16

Definition at line 6933 of file if_iwmreg.h.

◆ IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE

#define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)

Definition at line 1678 of file if_iwmreg.h.

◆ IWM_FH_SRVC_CHNL

#define IWM_FH_SRVC_CHNL (9)

Definition at line 1790 of file if_iwmreg.h.

◆ IWM_FH_SRVC_CHNL_SRAM_ADDR_REG

#define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG ( _chnl ) (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)

Definition at line 1793 of file if_iwmreg.h.

◆ IWM_FH_SRVC_LOWER_BOUND

#define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)

Definition at line 1791 of file if_iwmreg.h.

◆ IWM_FH_SRVC_UPPER_BOUND

#define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)

Definition at line 1792 of file if_iwmreg.h.

◆ IWM_FH_TCSR_0_REG0

#define IWM_FH_TCSR_0_REG0 (0x1D00)

Definition at line 560 of file if_iwmreg.h.

◆ IWM_FH_TCSR_CHNL_NUM

#define IWM_FH_TCSR_CHNL_NUM (8)

Definition at line 1715 of file if_iwmreg.h.

◆ IWM_FH_TCSR_CHNL_TX_BUF_STS_REG

#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG ( _chnl ) (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)

Definition at line 1722 of file if_iwmreg.h.

◆ IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX

#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)

Definition at line 1748 of file if_iwmreg.h.

◆ IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM

#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)

Definition at line 1747 of file if_iwmreg.h.

◆ IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY

#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)

Definition at line 1743 of file if_iwmreg.h.

◆ IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID

#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)

Definition at line 1745 of file if_iwmreg.h.

◆ IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT

#define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)

Definition at line 1744 of file if_iwmreg.h.

◆ IWM_FH_TCSR_CHNL_TX_CONFIG_REG

#define IWM_FH_TCSR_CHNL_TX_CONFIG_REG ( _chnl ) (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))

Definition at line 1718 of file if_iwmreg.h.

◆ IWM_FH_TCSR_CHNL_TX_CREDIT_REG

#define IWM_FH_TCSR_CHNL_TX_CREDIT_REG ( _chnl ) (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)

Definition at line 1720 of file if_iwmreg.h.

◆ IWM_FH_TCSR_LOWER_BOUND

#define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)

Transmit DMA Channel Control/Status Registers (TCSR)

Device has one configuration register for each of 8 Tx DMA/FIFO channels supported in hardware (don't confuse these with the 16 Tx queues in DRAM, which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.

To use a Tx DMA channel, driver must initialize its IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:

IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL

All other bits should be 0.

Bit fields: 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, '10' operate normally 29- 4: Reserved, set to "0" 3: Enable internal DMA requests (1, normal operation), disable (0) 2- 0: Reserved, set to "0"

Definition at line 1711 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)

Definition at line 1732 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)

Definition at line 1733 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)

Definition at line 1731 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)

Definition at line 1736 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)

Definition at line 1737 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)

Definition at line 1735 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)

Definition at line 1741 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)

Definition at line 1739 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)

Definition at line 1740 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)

Definition at line 1728 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)

Definition at line 1729 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)

Definition at line 1726 of file if_iwmreg.h.

◆ IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF

#define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)

Definition at line 1725 of file if_iwmreg.h.

◆ IWM_FH_TCSR_UPPER_BOUND

#define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)

Definition at line 1712 of file if_iwmreg.h.

◆ IWM_FH_TFDIB_CTRL0_REG

#define IWM_FH_TFDIB_CTRL0_REG ( _chnl ) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))

Definition at line 1686 of file if_iwmreg.h.

◆ IWM_FH_TFDIB_CTRL1_REG

#define IWM_FH_TFDIB_CTRL1_REG ( _chnl ) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)

Definition at line 1687 of file if_iwmreg.h.

◆ IWM_FH_TFDIB_LOWER_BOUND

#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)

Definition at line 1684 of file if_iwmreg.h.

◆ IWM_FH_TFDIB_UPPER_BOUND

#define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)

Definition at line 1685 of file if_iwmreg.h.

◆ IWM_FH_TSSR_LOWER_BOUND

#define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)

Tx Shared Status Registers (TSSR)

After stopping Tx DMA channel (writing 0 to IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle (channel's buffers empty | no pending requests).

Bit fields: 31-24: 1 = Channel buffers empty (channel 7:0) 23-16: 1 = No pending requests (channel 7:0)

Definition at line 1762 of file if_iwmreg.h.

◆ IWM_FH_TSSR_TX_ERROR_REG

#define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)

Bit fields for TSSR(Tx Shared Status & Control) error status register: 31: Indicates an address error when accessed to internal memory uCode/driver must write "1" in order to clear this flag 30: Indicates that Host did not send the expected number of dwords to FH uCode/driver must write "1" in order to clear this flag 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA command was received from the scheduler while the TRB was already full with previous command uCode/driver must write "1" in order to clear this flag 7-0: Each status bit indicates a channel's TxCredit error. When an error bit is set, it indicates that the FH has received a full indication from the RTC TxFIFO and the current value of the TxCredit counter was not equal to zero. This mean that the credit mechanism was not synchronized to the TxFIFO status uCode/driver must write "1" in order to clear this flag

Definition at line 1784 of file if_iwmreg.h.

◆ IWM_FH_TSSR_TX_MSG_CONFIG_REG

#define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)

Definition at line 1785 of file if_iwmreg.h.

◆ IWM_FH_TSSR_TX_STATUS_REG

#define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)

Definition at line 1765 of file if_iwmreg.h.

◆ IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE

#define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE ( _chnl ) ((1 << (_chnl)) << 16)

Definition at line 1787 of file if_iwmreg.h.

◆ IWM_FH_TSSR_UPPER_BOUND

#define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)

Definition at line 1763 of file if_iwmreg.h.

◆ IWM_FH_TX_CHICKEN_BITS_REG

#define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)

Definition at line 1796 of file if_iwmreg.h.

◆ IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN

#define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)

Definition at line 1803 of file if_iwmreg.h.

◆ IWM_FH_TX_TRB_REG

#define IWM_FH_TX_TRB_REG ( _chan )

Value:

(IWM_FH_MEM_LOWER_BOUND + 0x958 + \

(_chan) * 4)

IWM_FH_MEM_LOWER_BOUND

#define IWM_FH_MEM_LOWER_BOUND

Definition: if_iwmreg.h:1445

Definition at line 1797 of file if_iwmreg.h.

◆ IWM_FH_UCODE_LOAD_STATUS

#define IWM_FH_UCODE_LOAD_STATUS 0x1af0

Definition at line 435 of file if_iwmreg.h.

◆ IWM_FIRST_AGG_TX_QUEUE

#define IWM_FIRST_AGG_TX_QUEUE IWM_DQA_MIN_DATA_QUEUE

Definition at line 1962 of file if_iwmreg.h.

◆ IWM_FRAME_LIMIT

#define IWM_FRAME_LIMIT 64

Definition at line 6815 of file if_iwmreg.h.

◆ IWM_FSEQ_VER_MISMATCH_NOTIFICATION

#define IWM_FSEQ_VER_MISMATCH_NOTIFICATION 0xff

Definition at line 2128 of file if_iwmreg.h.

◆ IWM_FULL_SCAN_MULTIPLIER

#define IWM_FULL_SCAN_MULTIPLIER 5

Definition at line 5394 of file if_iwmreg.h.

◆ IWM_FW_CMD_ID_AND_COLOR

#define IWM_FW_CMD_ID_AND_COLOR	(	_id,
		_color
	)

Value:

((_id << IWM_FW_CTXT_ID_POS) |\

(_color << IWM_FW_CTXT_COLOR_POS))

IWM_FW_CTXT_COLOR_POS

#define IWM_FW_CTXT_COLOR_POS

Definition: if_iwmreg.h:2653

IWM_FW_CTXT_ID_POS

#define IWM_FW_CTXT_ID_POS

Definition: if_iwmreg.h:2651

Definition at line 2657 of file if_iwmreg.h.

◆ IWM_FW_CMD_VER_UNKNOWN

#define IWM_FW_CMD_VER_UNKNOWN 99

Definition at line 2626 of file if_iwmreg.h.

◆ IWM_FW_CTXT_ACTION_ADD

#define IWM_FW_CTXT_ACTION_ADD 1

Definition at line 2662 of file if_iwmreg.h.

◆ IWM_FW_CTXT_ACTION_MODIFY

#define IWM_FW_CTXT_ACTION_MODIFY 2

Definition at line 2663 of file if_iwmreg.h.

◆ IWM_FW_CTXT_ACTION_NUM

#define IWM_FW_CTXT_ACTION_NUM 4

Definition at line 2665 of file if_iwmreg.h.

◆ IWM_FW_CTXT_ACTION_REMOVE

#define IWM_FW_CTXT_ACTION_REMOVE 3

Definition at line 2664 of file if_iwmreg.h.

◆ IWM_FW_CTXT_ACTION_STUB

#define IWM_FW_CTXT_ACTION_STUB 0

Definition at line 2661 of file if_iwmreg.h.

◆ IWM_FW_CTXT_COLOR_MSK

#define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)

Definition at line 2654 of file if_iwmreg.h.

◆ IWM_FW_CTXT_COLOR_POS

#define IWM_FW_CTXT_COLOR_POS (8)

Definition at line 2653 of file if_iwmreg.h.

◆ IWM_FW_CTXT_ID_MSK

#define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)

Definition at line 2652 of file if_iwmreg.h.

◆ IWM_FW_CTXT_ID_POS

#define IWM_FW_CTXT_ID_POS (0)

Definition at line 2651 of file if_iwmreg.h.

◆ IWM_FW_CTXT_INVALID

#define IWM_FW_CTXT_INVALID (0xffffffff)

Definition at line 2655 of file if_iwmreg.h.

◆ IWM_FW_ERR_ARC_CODE

#define IWM_FW_ERR_ARC_CODE 0x4

Definition at line 2599 of file if_iwmreg.h.

◆ IWM_FW_ERR_ARC_MEMORY

#define IWM_FW_ERR_ARC_MEMORY 0x3

Definition at line 2598 of file if_iwmreg.h.

◆ IWM_FW_ERR_FATAL

#define IWM_FW_ERR_FATAL 0xFF

Definition at line 2605 of file if_iwmreg.h.

◆ IWM_FW_ERR_INVALID_CMD_PARAM

#define IWM_FW_ERR_INVALID_CMD_PARAM 0x1

Definition at line 2596 of file if_iwmreg.h.

◆ IWM_FW_ERR_OBSOLETE_FUNC

#define IWM_FW_ERR_OBSOLETE_FUNC 0x12

Definition at line 2603 of file if_iwmreg.h.

◆ IWM_FW_ERR_SERVICE

#define IWM_FW_ERR_SERVICE 0x2

Definition at line 2597 of file if_iwmreg.h.

◆ IWM_FW_ERR_UNEXPECTED

#define IWM_FW_ERR_UNEXPECTED 0xFE

Definition at line 2604 of file if_iwmreg.h.

◆ IWM_FW_ERR_UNKNOWN_CMD

#define IWM_FW_ERR_UNKNOWN_CMD 0x0

Definition at line 2595 of file if_iwmreg.h.

◆ IWM_FW_ERR_WATCH_DOG

#define IWM_FW_ERR_WATCH_DOG 0x5

Definition at line 2600 of file if_iwmreg.h.

◆ IWM_FW_ERR_WEP_GRP_KEY_INDX

#define IWM_FW_ERR_WEP_GRP_KEY_INDX 0x10

Definition at line 2601 of file if_iwmreg.h.

◆ IWM_FW_ERR_WEP_KEY_SIZE

#define IWM_FW_ERR_WEP_KEY_SIZE 0x11

Definition at line 2602 of file if_iwmreg.h.

◆ IWM_FW_ERROR_RECOVERY_CMD

#define IWM_FW_ERROR_RECOVERY_CMD 0x07

Definition at line 2153 of file if_iwmreg.h.

◆ IWM_FW_MAC_TYPE_AUX

#define IWM_FW_MAC_TYPE_AUX IWM_FW_MAC_TYPE_FIRST

Definition at line 3855 of file if_iwmreg.h.

◆ IWM_FW_MAC_TYPE_BSS_STA

#define IWM_FW_MAC_TYPE_BSS_STA 5

Definition at line 3859 of file if_iwmreg.h.

◆ IWM_FW_MAC_TYPE_FIRST

#define IWM_FW_MAC_TYPE_FIRST 1

Supported MAC types @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal) @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?) @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS @IWM_FW_MAC_TYPE_IBSS: IBSS @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device @IWM_FW_MAC_TYPE_P2P_STA: P2P client @IWM_FW_MAC_TYPE_GO: P2P GO @IWM_FW_MAC_TYPE_TEST: ? @IWM_FW_MAC_TYPE_MAX: highest support MAC type

Definition at line 3854 of file if_iwmreg.h.

◆ IWM_FW_MAC_TYPE_GO

#define IWM_FW_MAC_TYPE_GO 8

Definition at line 3862 of file if_iwmreg.h.

◆ IWM_FW_MAC_TYPE_IBSS

#define IWM_FW_MAC_TYPE_IBSS 4

Definition at line 3858 of file if_iwmreg.h.

◆ IWM_FW_MAC_TYPE_LISTENER

#define IWM_FW_MAC_TYPE_LISTENER 2

Definition at line 3856 of file if_iwmreg.h.

◆ IWM_FW_MAC_TYPE_MAX

#define IWM_FW_MAC_TYPE_MAX IWM_FW_MAC_TYPE_TEST

Definition at line 3864 of file if_iwmreg.h.

◆ IWM_FW_MAC_TYPE_P2P_DEVICE

#define IWM_FW_MAC_TYPE_P2P_DEVICE 6

Definition at line 3860 of file if_iwmreg.h.

◆ IWM_FW_MAC_TYPE_P2P_STA

#define IWM_FW_MAC_TYPE_P2P_STA 7

Definition at line 3861 of file if_iwmreg.h.

◆ IWM_FW_MAC_TYPE_PIBSS

#define IWM_FW_MAC_TYPE_PIBSS 3

Definition at line 3857 of file if_iwmreg.h.

◆ IWM_FW_MAC_TYPE_TEST

#define IWM_FW_MAC_TYPE_TEST 9

Definition at line 3863 of file if_iwmreg.h.

◆ IWM_FW_MEM_EXTENDED_END

#define IWM_FW_MEM_EXTENDED_END 0x57FFF

Definition at line 554 of file if_iwmreg.h.

◆ IWM_FW_MEM_EXTENDED_START

#define IWM_FW_MEM_EXTENDED_START 0x40000

Definition at line 553 of file if_iwmreg.h.

◆ IWM_FW_PAGING_BLOCK_CMD

#define IWM_FW_PAGING_BLOCK_CMD 0x4f

Definition at line 2031 of file if_iwmreg.h.

◆ IWM_FW_PAGING_SIZE

#define IWM_FW_PAGING_SIZE (1 << IWM_PAGE_2_EXP_SIZE) /* page size is 4KB */

Definition at line 2436 of file if_iwmreg.h.

◆ IWM_FW_PHY_CFG_RADIO_DASH

#define IWM_FW_PHY_CFG_RADIO_DASH (0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS)

Definition at line 1007 of file if_iwmreg.h.

◆ IWM_FW_PHY_CFG_RADIO_DASH_POS

#define IWM_FW_PHY_CFG_RADIO_DASH_POS 4

Definition at line 1006 of file if_iwmreg.h.

◆ IWM_FW_PHY_CFG_RADIO_STEP

#define IWM_FW_PHY_CFG_RADIO_STEP (0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS)

Definition at line 1005 of file if_iwmreg.h.

◆ IWM_FW_PHY_CFG_RADIO_STEP_POS

#define IWM_FW_PHY_CFG_RADIO_STEP_POS 2

Definition at line 1004 of file if_iwmreg.h.

◆ IWM_FW_PHY_CFG_RADIO_TYPE

#define IWM_FW_PHY_CFG_RADIO_TYPE (0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS)

Definition at line 1003 of file if_iwmreg.h.

◆ IWM_FW_PHY_CFG_RADIO_TYPE_POS

#define IWM_FW_PHY_CFG_RADIO_TYPE_POS 0

Definition at line 1002 of file if_iwmreg.h.

◆ IWM_FW_PHY_CFG_RX_CHAIN

#define IWM_FW_PHY_CFG_RX_CHAIN (0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS)

Definition at line 1011 of file if_iwmreg.h.

◆ IWM_FW_PHY_CFG_RX_CHAIN_POS

#define IWM_FW_PHY_CFG_RX_CHAIN_POS 20

Definition at line 1010 of file if_iwmreg.h.

◆ IWM_FW_PHY_CFG_TX_CHAIN

#define IWM_FW_PHY_CFG_TX_CHAIN (0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS)

Definition at line 1009 of file if_iwmreg.h.

◆ IWM_FW_PHY_CFG_TX_CHAIN_POS

#define IWM_FW_PHY_CFG_TX_CHAIN_POS 16

Definition at line 1008 of file if_iwmreg.h.

◆ IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG

#define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)

Definition at line 1596 of file if_iwmreg.h.

◆ IWM_FW_SUBTYPE_ALIVE_ONLY

#define IWM_FW_SUBTYPE_ALIVE_ONLY 3

Definition at line 2517 of file if_iwmreg.h.

◆ IWM_FW_SUBTYPE_AP_SUBTYPE

#define IWM_FW_SUBTYPE_AP_SUBTYPE 5

Definition at line 2519 of file if_iwmreg.h.

◆ IWM_FW_SUBTYPE_BOOTSRAP

#define IWM_FW_SUBTYPE_BOOTSRAP 1 /* Not valid */

Definition at line 2515 of file if_iwmreg.h.

◆ IWM_FW_SUBTYPE_FULL_FEATURE

#define IWM_FW_SUBTYPE_FULL_FEATURE 0

Definition at line 2514 of file if_iwmreg.h.

◆ IWM_FW_SUBTYPE_INITIALIZE

#define IWM_FW_SUBTYPE_INITIALIZE 9

Definition at line 2521 of file if_iwmreg.h.

◆ IWM_FW_SUBTYPE_REDUCED

#define IWM_FW_SUBTYPE_REDUCED 2

Definition at line 2516 of file if_iwmreg.h.

◆ IWM_FW_SUBTYPE_WIPAN

#define IWM_FW_SUBTYPE_WIPAN 6

Definition at line 2520 of file if_iwmreg.h.

◆ IWM_FW_SUBTYPE_WOWLAN

#define IWM_FW_SUBTYPE_WOWLAN 4

Definition at line 2518 of file if_iwmreg.h.

◆ IWM_FW_TYPE_AP

#define IWM_FW_TYPE_AP 2

Definition at line 2508 of file if_iwmreg.h.

◆ IWM_FW_TYPE_HW

#define IWM_FW_TYPE_HW 0

Definition at line 2506 of file if_iwmreg.h.

◆ IWM_FW_TYPE_PROT

#define IWM_FW_TYPE_PROT 1

Definition at line 2507 of file if_iwmreg.h.

◆ IWM_FW_TYPE_TIMING

#define IWM_FW_TYPE_TIMING 4

Definition at line 2510 of file if_iwmreg.h.

◆ IWM_FW_TYPE_WIPAN

#define IWM_FW_TYPE_WIPAN 5

Definition at line 2511 of file if_iwmreg.h.

◆ IWM_FW_TYPE_WOWLAN

#define IWM_FW_TYPE_WOWLAN 3

Definition at line 2509 of file if_iwmreg.h.

◆ IWM_GEO_NO_INFO

#define IWM_GEO_NO_INFO 0

Definition at line 6712 of file if_iwmreg.h.

◆ IWM_GEO_WMM_ETSI_5GHZ_INFO

#define IWM_GEO_WMM_ETSI_5GHZ_INFO (1 << 0)

Definition at line 6713 of file if_iwmreg.h.

◆ IWM_GOOD_CRC_TH_DEFAULT

#define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)

Definition at line 5391 of file if_iwmreg.h.

◆ IWM_GSCAN_HOTLIST_CHANGE_EVENT

#define IWM_GSCAN_HOTLIST_CHANGE_EVENT 0xFE

Definition at line 6140 of file if_iwmreg.h.

◆ IWM_GSCAN_RESET_HOTLIST_CMD

#define IWM_GSCAN_RESET_HOTLIST_CMD 0x3

Definition at line 6136 of file if_iwmreg.h.

◆ IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD

#define IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5

Definition at line 6138 of file if_iwmreg.h.

◆ IWM_GSCAN_RESULTS_AVAILABLE_EVENT

#define IWM_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF

Definition at line 6141 of file if_iwmreg.h.

◆ IWM_GSCAN_SET_HOTLIST_CMD

#define IWM_GSCAN_SET_HOTLIST_CMD 0x2

Definition at line 6135 of file if_iwmreg.h.

◆ IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD

#define IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4

Definition at line 6137 of file if_iwmreg.h.

◆ IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT

#define IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD

Definition at line 6139 of file if_iwmreg.h.

◆ IWM_GSCAN_START_CMD

#define IWM_GSCAN_START_CMD 0x0

Definition at line 6133 of file if_iwmreg.h.

◆ IWM_GSCAN_STOP_CMD

#define IWM_GSCAN_STOP_CMD 0x1

Definition at line 6134 of file if_iwmreg.h.

◆ IWM_HALT_CARD_DISABLED

#define IWM_HALT_CARD_DISABLED 0x08

Definition at line 3434 of file if_iwmreg.h.

◆ IWM_HBUS_BASE

#define IWM_HBUS_BASE (0x400)

Definition at line 577 of file if_iwmreg.h.

◆ IWM_HBUS_TARG_MBX_C

#define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)

Definition at line 594 of file if_iwmreg.h.

◆ IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED

#define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)

Definition at line 595 of file if_iwmreg.h.

◆ IWM_HBUS_TARG_MEM_RADDR

#define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)

Definition at line 588 of file if_iwmreg.h.

◆ IWM_HBUS_TARG_MEM_RDAT

#define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)

Definition at line 591 of file if_iwmreg.h.

◆ IWM_HBUS_TARG_MEM_WADDR

#define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)

Definition at line 589 of file if_iwmreg.h.

◆ IWM_HBUS_TARG_MEM_WDAT

#define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)

Definition at line 590 of file if_iwmreg.h.

◆ IWM_HBUS_TARG_PRPH_RADDR

#define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)

Definition at line 606 of file if_iwmreg.h.

◆ IWM_HBUS_TARG_PRPH_RDAT

#define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)

Definition at line 608 of file if_iwmreg.h.

◆ IWM_HBUS_TARG_PRPH_WADDR

#define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)

Definition at line 605 of file if_iwmreg.h.

◆ IWM_HBUS_TARG_PRPH_WDAT

#define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)

Definition at line 607 of file if_iwmreg.h.

◆ IWM_HBUS_TARG_TEST_REG

#define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)

Definition at line 647 of file if_iwmreg.h.

◆ IWM_HBUS_TARG_WRPTR

#define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)

Definition at line 656 of file if_iwmreg.h.

◆ IWM_HOST_INT_OPER_MODE

#define IWM_HOST_INT_OPER_MODE (1U << 31)

Definition at line 671 of file if_iwmreg.h.

◆ IWM_HOST_INT_TIMEOUT_DEF

#define IWM_HOST_INT_TIMEOUT_DEF (0x40)

Definition at line 669 of file if_iwmreg.h.

◆ IWM_HOST_INT_TIMEOUT_MAX

#define IWM_HOST_INT_TIMEOUT_MAX (0xFF)

Definition at line 668 of file if_iwmreg.h.

◆ IWM_HOST_INT_TIMEOUT_MIN

#define IWM_HOST_INT_TIMEOUT_MIN (0x0)

Definition at line 670 of file if_iwmreg.h.

◆ IWM_HOT_SPOT_CMD

#define IWM_HOT_SPOT_CMD 0x53

Definition at line 2036 of file if_iwmreg.h.

◆ IWM_HPM_DEBUG

#define IWM_HPM_DEBUG 0xa03440

Definition at line 642 of file if_iwmreg.h.

◆ IWM_HPM_PERSISTENCE_BIT

#define IWM_HPM_PERSISTENCE_BIT (1 << 12)

Definition at line 643 of file if_iwmreg.h.

◆ IWM_HW_ADDR

#define IWM_HW_ADDR 0x15

Definition at line 2313 of file if_iwmreg.h.

◆ IWM_HW_ADDR0_PCIE_8000

#define IWM_HW_ADDR0_PCIE_8000 0x8A

Definition at line 2328 of file if_iwmreg.h.

◆ IWM_HW_ADDR0_WFPM_8000

#define IWM_HW_ADDR0_WFPM_8000 0x12

Definition at line 2326 of file if_iwmreg.h.

◆ IWM_HW_ADDR1_PCIE_8000

#define IWM_HW_ADDR1_PCIE_8000 0x8E

Definition at line 2329 of file if_iwmreg.h.

◆ IWM_HW_ADDR1_WFPM_8000

#define IWM_HW_ADDR1_WFPM_8000 0x16

Definition at line 2327 of file if_iwmreg.h.

◆ IWM_HW_CARD_DISABLED

#define IWM_HW_CARD_DISABLED 0x01

Definition at line 3431 of file if_iwmreg.h.

◆ IWM_HW_STEP_LOCATION_BITS

#define IWM_HW_STEP_LOCATION_BITS 24

Definition at line 622 of file if_iwmreg.h.

◆ IWM_INIT_COMPLETE_NOTIF

#define IWM_INIT_COMPLETE_NOTIF 0x4

Definition at line 1984 of file if_iwmreg.h.

◆ IWM_INIT_EXTENDED_CFG_CMD

#define IWM_INIT_EXTENDED_CFG_CMD 0x03

Definition at line 2152 of file if_iwmreg.h.

◆ IWM_KW_SIZE

#define IWM_KW_SIZE 0x1000 /* 4k */

Definition at line 1896 of file if_iwmreg.h.

◆ IWM_LAST_AGG_TX_QUEUE

#define IWM_LAST_AGG_TX_QUEUE (IWM_FIRST_AGG_TX_QUEUE + IWM_MAX_TID_COUNT - 1)

Definition at line 1963 of file if_iwmreg.h.

◆ IWM_LEGACY_GROUP

#define IWM_LEGACY_GROUP 0x0

Definition at line 2140 of file if_iwmreg.h.

◆ IWM_LMAC_24G_INDEX

#define IWM_LMAC_24G_INDEX 0

Definition at line 2988 of file if_iwmreg.h.

◆ IWM_LMAC_5G_INDEX

#define IWM_LMAC_5G_INDEX 1

Definition at line 2989 of file if_iwmreg.h.

◆ IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL

#define IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL (1 << 7)

Definition at line 5518 of file if_iwmreg.h.

◆ IWM_LMAC_SCAN_FLAG_FRAGMENTED

#define IWM_LMAC_SCAN_FLAG_FRAGMENTED (1 << 5)

Definition at line 5516 of file if_iwmreg.h.

◆ IWM_LMAC_SCAN_FLAG_ITER_COMPLETE

#define IWM_LMAC_SCAN_FLAG_ITER_COMPLETE (1 << 3)

Definition at line 5514 of file if_iwmreg.h.

◆ IWM_LMAC_SCAN_FLAG_MATCH

#define IWM_LMAC_SCAN_FLAG_MATCH (1 << 9)

Definition at line 5519 of file if_iwmreg.h.

◆ IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS

#define IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS (1 << 4)

Definition at line 5515 of file if_iwmreg.h.

◆ IWM_LMAC_SCAN_FLAG_PASS_ALL

#define IWM_LMAC_SCAN_FLAG_PASS_ALL (1 << 0)

LMAC scan flags @IWM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses without filtering. @IWM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels @IWM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan @IWM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification @IWM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching @IWM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented @IWM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report and DS parameter set IEs into probe requests. @IWM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels 1, 6 and 11. @IWM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches

Definition at line 5511 of file if_iwmreg.h.

◆ IWM_LMAC_SCAN_FLAG_PASSIVE

#define IWM_LMAC_SCAN_FLAG_PASSIVE (1 << 1)

Definition at line 5512 of file if_iwmreg.h.

◆ IWM_LMAC_SCAN_FLAG_PRE_CONNECTION

#define IWM_LMAC_SCAN_FLAG_PRE_CONNECTION (1 << 2)

Definition at line 5513 of file if_iwmreg.h.

◆ IWM_LMAC_SCAN_FLAGS_RRM_ENABLED

#define IWM_LMAC_SCAN_FLAGS_RRM_ENABLED (1 << 6)

Definition at line 5517 of file if_iwmreg.h.

◆ IWM_LMPM_CHICK

#define IWM_LMPM_CHICK 0xa01ff8

Definition at line 557 of file if_iwmreg.h.

◆ IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE

#define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01

Definition at line 558 of file if_iwmreg.h.

◆ IWM_LMPM_PMG_EN

#define IWM_LMPM_PMG_EN 0xa01cec

Definition at line 614 of file if_iwmreg.h.

◆ IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE

#define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000

Definition at line 547 of file if_iwmreg.h.

◆ IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE

#define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400

Definition at line 548 of file if_iwmreg.h.

◆ IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR

#define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78

Definition at line 544 of file if_iwmreg.h.

◆ IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR

#define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c

Definition at line 545 of file if_iwmreg.h.

◆ IWM_LONG_GROUP

#define IWM_LONG_GROUP 0x1

Definition at line 2141 of file if_iwmreg.h.

◆ IWM_LOW_RETRY_LIMIT

#define IWM_LOW_RETRY_LIMIT 7

Definition at line 4918 of file if_iwmreg.h.

◆ IWM_LQ_CMD

#define IWM_LQ_CMD 0x4e

Definition at line 2021 of file if_iwmreg.h.

◆ IWM_LQ_FLAG_COLOR_MSK

#define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)

Definition at line 4709 of file if_iwmreg.h.

◆ IWM_LQ_FLAG_COLOR_POS

#define IWM_LQ_FLAG_COLOR_POS 1

Definition at line 4708 of file if_iwmreg.h.

◆ IWM_LQ_FLAG_DYNAMIC_BW_MSK

#define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)

Definition at line 4725 of file if_iwmreg.h.

◆ IWM_LQ_FLAG_DYNAMIC_BW_POS

#define IWM_LQ_FLAG_DYNAMIC_BW_POS 6

Definition at line 4724 of file if_iwmreg.h.

◆ IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC

#define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)

Definition at line 4719 of file if_iwmreg.h.

◆ IWM_LQ_FLAG_RTS_BW_SIG_NONE

#define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)

Definition at line 4717 of file if_iwmreg.h.

◆ IWM_LQ_FLAG_RTS_BW_SIG_POS

#define IWM_LQ_FLAG_RTS_BW_SIG_POS 4

Definition at line 4716 of file if_iwmreg.h.

◆ IWM_LQ_FLAG_RTS_BW_SIG_STATIC

#define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)

Definition at line 4718 of file if_iwmreg.h.

◆ IWM_LQ_FLAG_USE_RTS_MSK

#define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)

Definition at line 4705 of file if_iwmreg.h.

◆ IWM_LQ_FLAG_USE_RTS_POS

#define IWM_LQ_FLAG_USE_RTS_POS 0

Definition at line 4704 of file if_iwmreg.h.

◆ IWM_LQ_MAX_RETRY_NUM

#define IWM_LQ_MAX_RETRY_NUM 16

Definition at line 4699 of file if_iwmreg.h.

◆ IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD

#define IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040

Definition at line 4149 of file if_iwmreg.h.

◆ IWM_LTR_CFG_FLAG_FEATURE_ENABLE

#define IWM_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001

masks for LTR config command flags @IWM_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status @IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow memory access @IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR reg change @IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from D0 to D3 @IWM_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register @IWM_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register @IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD

Definition at line 4143 of file if_iwmreg.h.

◆ IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3

#define IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008

Definition at line 4146 of file if_iwmreg.h.

◆ IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS

#define IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002

Definition at line 4144 of file if_iwmreg.h.

◆ IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH

#define IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004

Definition at line 4145 of file if_iwmreg.h.

◆ IWM_LTR_CFG_FLAG_SW_SET_LONG

#define IWM_LTR_CFG_FLAG_SW_SET_LONG 0x00000020

Definition at line 4148 of file if_iwmreg.h.

◆ IWM_LTR_CFG_FLAG_SW_SET_SHORT

#define IWM_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010

Definition at line 4147 of file if_iwmreg.h.

◆ IWM_LTR_CONFIG

#define IWM_LTR_CONFIG 0xee

Definition at line 2051 of file if_iwmreg.h.

◆ IWM_LTR_VALID_STATES_NUM

#define IWM_LTR_VALID_STATES_NUM 4

Definition at line 4161 of file if_iwmreg.h.

◆ IWM_MAC_ADDRESS_OVERRIDE_8000

#define IWM_MAC_ADDRESS_OVERRIDE_8000 1

Definition at line 2330 of file if_iwmreg.h.

◆ IWM_MAC_CONF_GROUP

#define IWM_MAC_CONF_GROUP 0x3

Definition at line 2143 of file if_iwmreg.h.

◆ IWM_MAC_CONTEXT_CMD

#define IWM_MAC_CONTEXT_CMD 0x28

Definition at line 2014 of file if_iwmreg.h.

◆ IWM_MAC_FILTER_ACCEPT_GRP

#define IWM_MAC_FILTER_ACCEPT_GRP (1 << 2)

Definition at line 4008 of file if_iwmreg.h.

◆ IWM_MAC_FILTER_DIS_DECRYPT

#define IWM_MAC_FILTER_DIS_DECRYPT (1 << 3)

Definition at line 4009 of file if_iwmreg.h.

◆ IWM_MAC_FILTER_DIS_GRP_DECRYPT

#define IWM_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4)

Definition at line 4010 of file if_iwmreg.h.

◆ IWM_MAC_FILTER_IN_BEACON

#define IWM_MAC_FILTER_IN_BEACON (1 << 6)

Definition at line 4011 of file if_iwmreg.h.

◆ IWM_MAC_FILTER_IN_CONTROL_AND_MGMT

#define IWM_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1)

Definition at line 4007 of file if_iwmreg.h.

◆ IWM_MAC_FILTER_IN_CRC32

#define IWM_MAC_FILTER_IN_CRC32 (1 << 11)

Definition at line 4013 of file if_iwmreg.h.

◆ IWM_MAC_FILTER_IN_PROBE_REQUEST

#define IWM_MAC_FILTER_IN_PROBE_REQUEST (1 << 12)

Definition at line 4014 of file if_iwmreg.h.

◆ IWM_MAC_FILTER_IN_PROMISC

#define IWM_MAC_FILTER_IN_PROMISC (1 << 0)

MAC context filter flags @IWM_MAC_FILTER_IN_PROMISC: accept all data frames @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and control frames to the host @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host (in station mode when associated) @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host

Definition at line 4006 of file if_iwmreg.h.

◆ IWM_MAC_FILTER_OUT_BCAST

#define IWM_MAC_FILTER_OUT_BCAST (1 << 8)

Definition at line 4012 of file if_iwmreg.h.

◆ IWM_MAC_FLG_SHORT_PREAMBLE

#define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)

Definition at line 3838 of file if_iwmreg.h.

◆ IWM_MAC_FLG_SHORT_SLOT

#define IWM_MAC_FLG_SHORT_SLOT (1 << 4)

Definition at line 3837 of file if_iwmreg.h.

◆ IWM_MAC_INDEX_AUX

#define IWM_MAC_INDEX_AUX 4

Definition at line 3813 of file if_iwmreg.h.

◆ IWM_MAC_INDEX_MIN_DRIVER

#define IWM_MAC_INDEX_MIN_DRIVER 0

Definition at line 3814 of file if_iwmreg.h.

◆ IWM_MAC_PM_POWER_TABLE

#define IWM_MAC_PM_POWER_TABLE 0xa9

Definition at line 2077 of file if_iwmreg.h.

◆ IWM_MAC_PROT_FLG_FAT_PROT

#define IWM_MAC_PROT_FLG_FAT_PROT (1 << 24)

Definition at line 3834 of file if_iwmreg.h.

◆ IWM_MAC_PROT_FLG_HT_PROT

#define IWM_MAC_PROT_FLG_HT_PROT (1 << 23)

Definition at line 3833 of file if_iwmreg.h.

◆ IWM_MAC_PROT_FLG_SELF_CTS_EN

#define IWM_MAC_PROT_FLG_SELF_CTS_EN (1 << 30)

Definition at line 3835 of file if_iwmreg.h.

◆ IWM_MAC_PROT_FLG_TGG_PROTECT

#define IWM_MAC_PROT_FLG_TGG_PROTECT (1 << 3)

MAC context flags @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames, this will require CCK RTS/CTS2self. RTS/CTS will protect full burst time. @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self

Definition at line 3832 of file if_iwmreg.h.

◆ IWM_MAC_QOS_FLG_TGN

#define IWM_MAC_QOS_FLG_TGN (1 << 1)

Definition at line 4024 of file if_iwmreg.h.

◆ IWM_MAC_QOS_FLG_TXOP_TYPE

#define IWM_MAC_QOS_FLG_TXOP_TYPE (1 << 4)

Definition at line 4025 of file if_iwmreg.h.

◆ IWM_MAC_QOS_FLG_UPDATE_EDCA

#define IWM_MAC_QOS_FLG_UPDATE_EDCA (1 << 0)

QoS flags @IWM_MAC_QOS_FLG_UPDATE_EDCA: ? @IWM_MAC_QOS_FLG_TGN: HT is enabled @IWM_MAC_QOS_FLG_TXOP_TYPE: ?

Definition at line 4023 of file if_iwmreg.h.

◆ IWM_MATCH_FOUND_NOTIFICATION

#define IWM_MATCH_FOUND_NOTIFICATION 0xd9

Definition at line 2040 of file if_iwmreg.h.

◆ IWM_MAX_BINDINGS

#define IWM_MAX_BINDINGS (4)

Definition at line 2646 of file if_iwmreg.h.

◆ IWM_MAX_CHAINS

#define IWM_MAX_CHAINS 3

Definition at line 3623 of file if_iwmreg.h.

◆ IWM_MAX_CMD_PAYLOAD_SIZE

#define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))

Definition at line 6881 of file if_iwmreg.h.

◆ IWM_MAX_DBM

#define IWM_MAX_DBM -33 /* realistic guess */

Definition at line 6952 of file if_iwmreg.h.

◆ IWM_MAX_DTS_TRIPS

#define IWM_MAX_DTS_TRIPS 8

Definition at line 2250 of file if_iwmreg.h.

◆ IWM_MAX_GLOBAL_KEYS

#define IWM_MAX_GLOBAL_KEYS (4)

Definition at line 6304 of file if_iwmreg.h.

◆ IWM_MAX_LMAC_SCANS

#define IWM_MAX_LMAC_SCANS 1

Definition at line 5716 of file if_iwmreg.h.

◆ IWM_MAX_MACS_IN_BINDING

#define IWM_MAX_MACS_IN_BINDING (3)

Definition at line 2645 of file if_iwmreg.h.

◆ IWM_MAX_MCAST_FILTERING_ADDRESSES

#define IWM_MAX_MCAST_FILTERING_ADDRESSES 256

Definition at line 3494 of file if_iwmreg.h.

◆ IWM_MAX_PAGING_IMAGE_SIZE

#define IWM_MAX_PAGING_IMAGE_SIZE (IWM_NUM_OF_BLOCK_PER_IMAGE * IWM_PAGING_BLOCK_SIZE)

Definition at line 2452 of file if_iwmreg.h.

◆ IWM_MAX_PHY_CALIBRATE_TBL_SIZE

#define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253

Definition at line 971 of file if_iwmreg.h.

◆ IWM_MAX_PHYS

#define IWM_MAX_PHYS (4)

Definition at line 2648 of file if_iwmreg.h.

◆ IWM_MAX_PORT_ID_NUM

#define IWM_MAX_PORT_ID_NUM 2

Definition at line 3493 of file if_iwmreg.h.

◆ IWM_MAX_QUEUES

#define IWM_MAX_QUEUES 31

Definition at line 1923 of file if_iwmreg.h.

◆ IWM_MAX_QUOTA

#define IWM_MAX_QUOTA 128

Definition at line 2992 of file if_iwmreg.h.

◆ IWM_MAX_SCHED_SCAN_PLANS

#define IWM_MAX_SCHED_SCAN_PLANS 2

Definition at line 5396 of file if_iwmreg.h.

◆ IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE

#define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19

Definition at line 970 of file if_iwmreg.h.

◆ IWM_MAX_TID_COUNT [1/2]

#define IWM_MAX_TID_COUNT 8

Definition at line 4907 of file if_iwmreg.h.

◆ IWM_MAX_TID_COUNT [2/2]

#define IWM_MAX_TID_COUNT 8

Definition at line 4907 of file if_iwmreg.h.

◆ IWM_MAX_UMAC_SCANS

#define IWM_MAX_UMAC_SCANS 8

Definition at line 5715 of file if_iwmreg.h.

◆ IWM_MCAST_FILTER_CMD

#define IWM_MCAST_FILTER_CMD 0xd0

Definition at line 2103 of file if_iwmreg.h.

◆ IWM_MCC_CHUB_UPDATE_CMD

#define IWM_MCC_CHUB_UPDATE_CMD 0xc9

Definition at line 2085 of file if_iwmreg.h.

◆ IWM_MCC_RESP_ILLEGAL

#define IWM_MCC_RESP_ILLEGAL 4

Definition at line 6767 of file if_iwmreg.h.

◆ IWM_MCC_RESP_INVALID

#define IWM_MCC_RESP_INVALID 2

Definition at line 6765 of file if_iwmreg.h.

◆ IWM_MCC_RESP_LOW_PRIORITY

#define IWM_MCC_RESP_LOW_PRIORITY 5

Definition at line 6768 of file if_iwmreg.h.

◆ IWM_MCC_RESP_NEW_CHAN_PROFILE

#define IWM_MCC_RESP_NEW_CHAN_PROFILE 0

Definition at line 6763 of file if_iwmreg.h.

◆ IWM_MCC_RESP_NVM_DISABLED

#define IWM_MCC_RESP_NVM_DISABLED 3

Definition at line 6766 of file if_iwmreg.h.

◆ IWM_MCC_RESP_SAME_CHAN_PROFILE

#define IWM_MCC_RESP_SAME_CHAN_PROFILE 1

Definition at line 6764 of file if_iwmreg.h.

◆ IWM_MCC_RESP_TEST_MODE_ACTIVE

#define IWM_MCC_RESP_TEST_MODE_ACTIVE 6

Definition at line 6769 of file if_iwmreg.h.

◆ IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE

#define IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE 8

Definition at line 6771 of file if_iwmreg.h.

◆ IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE

#define IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE 7

Definition at line 6770 of file if_iwmreg.h.

◆ IWM_MCC_SOURCE_3G_LTE_DEVICE

#define IWM_MCC_SOURCE_3G_LTE_DEVICE 4

Definition at line 6777 of file if_iwmreg.h.

◆ IWM_MCC_SOURCE_3G_LTE_HOST

#define IWM_MCC_SOURCE_3G_LTE_HOST 3

Definition at line 6776 of file if_iwmreg.h.

◆ IWM_MCC_SOURCE_BIOS

#define IWM_MCC_SOURCE_BIOS 2

Definition at line 6775 of file if_iwmreg.h.

◆ IWM_MCC_SOURCE_DEFAULT

#define IWM_MCC_SOURCE_DEFAULT 7

Definition at line 6780 of file if_iwmreg.h.

◆ IWM_MCC_SOURCE_GET_CURRENT

#define IWM_MCC_SOURCE_GET_CURRENT 0x10

Definition at line 6783 of file if_iwmreg.h.

◆ IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE

#define IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11

Definition at line 6784 of file if_iwmreg.h.

◆ IWM_MCC_SOURCE_MCC_API

#define IWM_MCC_SOURCE_MCC_API 9

Definition at line 6782 of file if_iwmreg.h.

◆ IWM_MCC_SOURCE_ME

#define IWM_MCC_SOURCE_ME 1

Definition at line 6774 of file if_iwmreg.h.

◆ IWM_MCC_SOURCE_OLD_FW

#define IWM_MCC_SOURCE_OLD_FW 0

Definition at line 6773 of file if_iwmreg.h.

◆ IWM_MCC_SOURCE_RESERVED

#define IWM_MCC_SOURCE_RESERVED 6

Definition at line 6779 of file if_iwmreg.h.

◆ IWM_MCC_SOURCE_UNINITIALIZED

#define IWM_MCC_SOURCE_UNINITIALIZED 8

Definition at line 6781 of file if_iwmreg.h.

◆ IWM_MCC_SOURCE_WIFI

#define IWM_MCC_SOURCE_WIFI 5

Definition at line 6778 of file if_iwmreg.h.

◆ IWM_MCC_UPDATE_CMD

#define IWM_MCC_UPDATE_CMD 0xc8

Definition at line 2084 of file if_iwmreg.h.

◆ IWM_MFUART_LOAD_NOTIFICATION

#define IWM_MFUART_LOAD_NOTIFICATION 0xb1

Definition at line 2074 of file if_iwmreg.h.

◆ IWM_MGMT_DFAULT_RETRY_LIMIT

#define IWM_MGMT_DFAULT_RETRY_LIMIT 3

Definition at line 4915 of file if_iwmreg.h.

◆ IWM_MGMT_MCAST_KEY

#define IWM_MGMT_MCAST_KEY 0x1f

Definition at line 2005 of file if_iwmreg.h.

◆ IWM_MIN_DBM

#define IWM_MIN_DBM -100

Definition at line 6951 of file if_iwmreg.h.

◆ IWM_MISSED_BEACONS_NOTIFICATION

#define IWM_MISSED_BEACONS_NOTIFICATION 0xa2

Definition at line 2072 of file if_iwmreg.h.

◆ IWM_MSIX_AUTO_CLEAR_CAUSE

#define IWM_MSIX_AUTO_CLEAR_CAUSE (0 << 7)

Definition at line 766 of file if_iwmreg.h.

◆ IWM_MSIX_NON_AUTO_CLEAR_CAUSE

#define IWM_MSIX_NON_AUTO_CLEAR_CAUSE (1 << 7)

Definition at line 767 of file if_iwmreg.h.

◆ IWM_N_HW_ADDRS

#define IWM_N_HW_ADDRS 3

Definition at line 2319 of file if_iwmreg.h.

◆ IWM_N_HW_ADDRS_8000

#define IWM_N_HW_ADDRS_8000 3

Definition at line 2337 of file if_iwmreg.h.

◆ IWM_NET_DETECT_CONFIG_CMD

#define IWM_NET_DETECT_CONFIG_CMD 0x54

Definition at line 2121 of file if_iwmreg.h.

◆ IWM_NET_DETECT_HOTSPOTS_CMD

#define IWM_NET_DETECT_HOTSPOTS_CMD 0x58

Definition at line 2124 of file if_iwmreg.h.

◆ IWM_NET_DETECT_HOTSPOTS_QUERY_CMD

#define IWM_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59

Definition at line 2125 of file if_iwmreg.h.

◆ IWM_NET_DETECT_PROFILES_CMD

#define IWM_NET_DETECT_PROFILES_CMD 0x57

Definition at line 2123 of file if_iwmreg.h.

◆ IWM_NET_DETECT_PROFILES_QUERY_CMD

#define IWM_NET_DETECT_PROFILES_QUERY_CMD 0x56

Definition at line 2122 of file if_iwmreg.h.

◆ IWM_NETWORK_TYPE_ANY

#define IWM_NETWORK_TYPE_ANY 3

Definition at line 5629 of file if_iwmreg.h.

◆ IWM_NETWORK_TYPE_BSS

#define IWM_NETWORK_TYPE_BSS 1

Definition at line 5627 of file if_iwmreg.h.

◆ IWM_NETWORK_TYPE_IBSS

#define IWM_NETWORK_TYPE_IBSS 2

Definition at line 5628 of file if_iwmreg.h.

◆ IWM_NON_QOS_TX_COUNTER_CMD

#define IWM_NON_QOS_TX_COUNTER_CMD 0x2d

Definition at line 2019 of file if_iwmreg.h.

◆ IWM_NONQOS_SEQ_GET

#define IWM_NONQOS_SEQ_GET 0x1

Definition at line 4111 of file if_iwmreg.h.

◆ IWM_NONQOS_SEQ_SET

#define IWM_NONQOS_SEQ_SET 0x2

Definition at line 4112 of file if_iwmreg.h.

◆ IWM_NUM_MAC_INDEX_DRIVER

#define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX

Definition at line 3815 of file if_iwmreg.h.

◆ IWM_NUM_OF_BLOCK_PER_IMAGE

#define IWM_NUM_OF_BLOCK_PER_IMAGE (1 << IWM_BLOCK_PER_IMAGE_2_EXP_SIZE)

Definition at line 2450 of file if_iwmreg.h.

◆ IWM_NUM_OF_FW_PAGING_BLOCKS

#define IWM_NUM_OF_FW_PAGING_BLOCKS 33 /* 32 for data and 1 block for CSS */

Definition at line 2462 of file if_iwmreg.h.

◆ IWM_NUM_OF_PAGE_PER_GROUP

#define IWM_NUM_OF_PAGE_PER_GROUP (1 << IWM_PAGE_PER_GROUP_2_EXP_SIZE)

Definition at line 2439 of file if_iwmreg.h.

◆ IWM_NUM_OF_TBS

#define IWM_NUM_OF_TBS 20

Definition at line 1839 of file if_iwmreg.h.

◆ IWM_NUM_PHY_CTX

#define IWM_NUM_PHY_CTX 3

Definition at line 3134 of file if_iwmreg.h.

◆ IWM_NUM_TSF_IDS

#define IWM_NUM_TSF_IDS 4

Definition at line 3879 of file if_iwmreg.h.

◆ IWM_NUM_UCODE_TLV_API

#define IWM_NUM_UCODE_TLV_API 128

Definition at line 858 of file if_iwmreg.h.

◆ IWM_NUM_UCODE_TLV_CAPA

#define IWM_NUM_UCODE_TLV_CAPA 128

Definition at line 966 of file if_iwmreg.h.

◆ IWM_NVM_ACCESS_CMD

#define IWM_NVM_ACCESS_CMD 0x88

Definition at line 2057 of file if_iwmreg.h.

◆ IWM_NVM_ACCESS_TARGET_CACHE

#define IWM_NVM_ACCESS_TARGET_CACHE 0

Definition at line 2394 of file if_iwmreg.h.

◆ IWM_NVM_ACCESS_TARGET_EEPROM

#define IWM_NVM_ACCESS_TARGET_EEPROM 2

Definition at line 2396 of file if_iwmreg.h.

◆ IWM_NVM_ACCESS_TARGET_OTP

#define IWM_NVM_ACCESS_TARGET_OTP 1

Definition at line 2395 of file if_iwmreg.h.

◆ IWM_NVM_CALIB_SECTION

#define IWM_NVM_CALIB_SECTION 0x2B8

Definition at line 2322 of file if_iwmreg.h.

◆ IWM_NVM_CALIB_SECTION_8000

#define IWM_NVM_CALIB_SECTION_8000 0x2B8

Definition at line 2346 of file if_iwmreg.h.

◆ IWM_NVM_CHANNEL_160MHZ

#define IWM_NVM_CHANNEL_160MHZ (1 << 11)

Definition at line 2391 of file if_iwmreg.h.

◆ IWM_NVM_CHANNEL_40MHZ

#define IWM_NVM_CHANNEL_40MHZ (1 << 9)

Definition at line 2389 of file if_iwmreg.h.

◆ IWM_NVM_CHANNEL_80MHZ

#define IWM_NVM_CHANNEL_80MHZ (1 << 10)

Definition at line 2390 of file if_iwmreg.h.

◆ IWM_NVM_CHANNEL_ACTIVE

#define IWM_NVM_CHANNEL_ACTIVE (1 << 3)

Definition at line 2385 of file if_iwmreg.h.

◆ IWM_NVM_CHANNEL_DFS

#define IWM_NVM_CHANNEL_DFS (1 << 7)

Definition at line 2387 of file if_iwmreg.h.

◆ IWM_NVM_CHANNEL_IBSS

#define IWM_NVM_CHANNEL_IBSS (1 << 1)

Definition at line 2384 of file if_iwmreg.h.

◆ IWM_NVM_CHANNEL_RADAR

#define IWM_NVM_CHANNEL_RADAR (1 << 4)

Definition at line 2386 of file if_iwmreg.h.

◆ IWM_NVM_CHANNEL_VALID

#define IWM_NVM_CHANNEL_VALID (1 << 0)

Definition at line 2383 of file if_iwmreg.h.

◆ IWM_NVM_CHANNEL_WIDE

#define IWM_NVM_CHANNEL_WIDE (1 << 8)

Definition at line 2388 of file if_iwmreg.h.

◆ IWM_NVM_CHANNELS

#define IWM_NVM_CHANNELS 0x1E0 - IWM_NVM_SW_SECTION

Definition at line 2320 of file if_iwmreg.h.

◆ IWM_NVM_CHANNELS_8000

#define IWM_NVM_CHANNELS_8000 0

Definition at line 2340 of file if_iwmreg.h.

◆ IWM_NVM_LAR_ENABLED_8000

#define IWM_NVM_LAR_ENABLED_8000 0x7

Definition at line 2343 of file if_iwmreg.h.

◆ IWM_NVM_LAR_OFFSET_8000

#define IWM_NVM_LAR_OFFSET_8000 0x507

Definition at line 2342 of file if_iwmreg.h.

◆ IWM_NVM_LAR_OFFSET_8000_OLD

#define IWM_NVM_LAR_OFFSET_8000_OLD 0x4C7

Definition at line 2341 of file if_iwmreg.h.

◆ IWM_NVM_NUM_OF_SECTIONS

#define IWM_NVM_NUM_OF_SECTIONS 13

Definition at line 2412 of file if_iwmreg.h.

◆ IWM_NVM_RF_CFG_DASH_MSK

#define IWM_NVM_RF_CFG_DASH_MSK ( x ) (x & 0x3) /* bits 0-1 */

Definition at line 2357 of file if_iwmreg.h.

◆ IWM_NVM_RF_CFG_DASH_MSK_8000

#define IWM_NVM_RF_CFG_DASH_MSK_8000 ( x ) ((x >> 4) & 0xF)

Definition at line 2365 of file if_iwmreg.h.

◆ IWM_NVM_RF_CFG_PNUM_MSK

#define IWM_NVM_RF_CFG_PNUM_MSK ( x ) ((x >> 6) & 0x3) /* bits 6-7 */

Definition at line 2360 of file if_iwmreg.h.

◆ IWM_NVM_RF_CFG_PNUM_MSK_8000

#define IWM_NVM_RF_CFG_PNUM_MSK_8000 ( x ) (x & 0xF)

Definition at line 2364 of file if_iwmreg.h.

◆ IWM_NVM_RF_CFG_RX_ANT_MSK

#define IWM_NVM_RF_CFG_RX_ANT_MSK ( x ) ((x >> 12) & 0xF) /* bits 12-15 */

Definition at line 2362 of file if_iwmreg.h.

◆ IWM_NVM_RF_CFG_RX_ANT_MSK_8000

#define IWM_NVM_RF_CFG_RX_ANT_MSK_8000 ( x ) ((x >> 28) & 0xF)

Definition at line 2369 of file if_iwmreg.h.

◆ IWM_NVM_RF_CFG_STEP_MSK

#define IWM_NVM_RF_CFG_STEP_MSK ( x ) ((x >> 2) & 0x3) /* bits 2-3 */

Definition at line 2358 of file if_iwmreg.h.

◆ IWM_NVM_RF_CFG_STEP_MSK_8000

#define IWM_NVM_RF_CFG_STEP_MSK_8000 ( x ) ((x >> 8) & 0xF)

Definition at line 2366 of file if_iwmreg.h.

◆ IWM_NVM_RF_CFG_TX_ANT_MSK

#define IWM_NVM_RF_CFG_TX_ANT_MSK ( x ) ((x >> 8) & 0xF) /* bits 8-11 */

Definition at line 2361 of file if_iwmreg.h.

◆ IWM_NVM_RF_CFG_TX_ANT_MSK_8000

#define IWM_NVM_RF_CFG_TX_ANT_MSK_8000 ( x ) ((x >> 24) & 0xF)

Definition at line 2368 of file if_iwmreg.h.

◆ IWM_NVM_RF_CFG_TYPE_MSK

#define IWM_NVM_RF_CFG_TYPE_MSK ( x ) ((x >> 4) & 0x3) /* bits 4-5 */

Definition at line 2359 of file if_iwmreg.h.

◆ IWM_NVM_RF_CFG_TYPE_MSK_8000

#define IWM_NVM_RF_CFG_TYPE_MSK_8000 ( x ) ((x >> 12) & 0xFFF)

Definition at line 2367 of file if_iwmreg.h.

◆ IWM_NVM_SECTION_TYPE_CALIBRATION

#define IWM_NVM_SECTION_TYPE_CALIBRATION 4

Definition at line 2403 of file if_iwmreg.h.

◆ IWM_NVM_SECTION_TYPE_HW

#define IWM_NVM_SECTION_TYPE_HW 0

Definition at line 2399 of file if_iwmreg.h.

◆ IWM_NVM_SECTION_TYPE_HW_8000

#define IWM_NVM_SECTION_TYPE_HW_8000 10

Definition at line 2409 of file if_iwmreg.h.

◆ IWM_NVM_SECTION_TYPE_MAC_OVERRIDE

#define IWM_NVM_SECTION_TYPE_MAC_OVERRIDE 11

Definition at line 2410 of file if_iwmreg.h.

◆ IWM_NVM_SECTION_TYPE_PAPD

#define IWM_NVM_SECTION_TYPE_PAPD 2

Definition at line 2401 of file if_iwmreg.h.

◆ IWM_NVM_SECTION_TYPE_PHY_SKU

#define IWM_NVM_SECTION_TYPE_PHY_SKU 12

Definition at line 2411 of file if_iwmreg.h.

◆ IWM_NVM_SECTION_TYPE_POST_FCS_CALIB

#define IWM_NVM_SECTION_TYPE_POST_FCS_CALIB 6

Definition at line 2405 of file if_iwmreg.h.

◆ IWM_NVM_SECTION_TYPE_PRODUCTION

#define IWM_NVM_SECTION_TYPE_PRODUCTION 5

Definition at line 2404 of file if_iwmreg.h.

◆ IWM_NVM_SECTION_TYPE_REGULATORY

#define IWM_NVM_SECTION_TYPE_REGULATORY 3

Definition at line 2402 of file if_iwmreg.h.

◆ IWM_NVM_SECTION_TYPE_REGULATORY_SDP

#define IWM_NVM_SECTION_TYPE_REGULATORY_SDP 8

Definition at line 2407 of file if_iwmreg.h.

◆ IWM_NVM_SECTION_TYPE_SW

#define IWM_NVM_SECTION_TYPE_SW 1

Definition at line 2400 of file if_iwmreg.h.

◆ IWM_NVM_SKU_CAP_11AC_ENABLE

#define IWM_NVM_SKU_CAP_11AC_ENABLE (1 << 3)

Definition at line 2353 of file if_iwmreg.h.

◆ IWM_NVM_SKU_CAP_11N_ENABLE

#define IWM_NVM_SKU_CAP_11N_ENABLE (1 << 2)

Definition at line 2352 of file if_iwmreg.h.

◆ IWM_NVM_SKU_CAP_BAND_24GHZ

#define IWM_NVM_SKU_CAP_BAND_24GHZ (1 << 0)

Definition at line 2350 of file if_iwmreg.h.

◆ IWM_NVM_SKU_CAP_BAND_52GHZ

#define IWM_NVM_SKU_CAP_BAND_52GHZ (1 << 1)

Definition at line 2351 of file if_iwmreg.h.

◆ IWM_NVM_SKU_CAP_MIMO_DISABLE

#define IWM_NVM_SKU_CAP_MIMO_DISABLE (1 << 5)

Definition at line 2354 of file if_iwmreg.h.

◆ IWM_NVM_SW_SECTION

#define IWM_NVM_SW_SECTION 0x1C0

Definition at line 2315 of file if_iwmreg.h.

◆ IWM_NVM_SW_SECTION_8000

#define IWM_NVM_SW_SECTION_8000 0x1C0

Definition at line 2333 of file if_iwmreg.h.

◆ IWM_NVM_VERSION

#define IWM_NVM_VERSION 0

Definition at line 2316 of file if_iwmreg.h.

◆ IWM_NVM_VERSION_8000

#define IWM_NVM_VERSION_8000 0

Definition at line 2334 of file if_iwmreg.h.

◆ IWM_OFDM_AGC_A_MSK

#define IWM_OFDM_AGC_A_MSK 0x0000007f

Definition at line 3198 of file if_iwmreg.h.

◆ IWM_OFDM_AGC_A_POS

#define IWM_OFDM_AGC_A_POS 0

Definition at line 3199 of file if_iwmreg.h.

◆ IWM_OFDM_AGC_B_MSK

#define IWM_OFDM_AGC_B_MSK 0x00003f80

Definition at line 3200 of file if_iwmreg.h.

◆ IWM_OFDM_AGC_B_POS

#define IWM_OFDM_AGC_B_POS 7

Definition at line 3201 of file if_iwmreg.h.

◆ IWM_OFDM_AGC_CODE_MSK

#define IWM_OFDM_AGC_CODE_MSK 0x3fe00000

Definition at line 3202 of file if_iwmreg.h.

◆ IWM_OFDM_AGC_CODE_POS

#define IWM_OFDM_AGC_CODE_POS 20

Definition at line 3203 of file if_iwmreg.h.

◆ IWM_OFDM_RSSI_A_POS

#define IWM_OFDM_RSSI_A_POS 0

Definition at line 3205 of file if_iwmreg.h.

◆ IWM_OFDM_RSSI_ALLBAND_A_MSK

#define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00

Definition at line 3206 of file if_iwmreg.h.

◆ IWM_OFDM_RSSI_ALLBAND_A_POS

#define IWM_OFDM_RSSI_ALLBAND_A_POS 8

Definition at line 3207 of file if_iwmreg.h.

◆ IWM_OFDM_RSSI_ALLBAND_B_MSK

#define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000

Definition at line 3210 of file if_iwmreg.h.

◆ IWM_OFDM_RSSI_ALLBAND_B_POS

#define IWM_OFDM_RSSI_ALLBAND_B_POS 24

Definition at line 3211 of file if_iwmreg.h.

◆ IWM_OFDM_RSSI_B_POS

#define IWM_OFDM_RSSI_B_POS 16

Definition at line 3209 of file if_iwmreg.h.

◆ IWM_OFDM_RSSI_INBAND_A_MSK

#define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff

Definition at line 3204 of file if_iwmreg.h.

◆ IWM_OFDM_RSSI_INBAND_B_MSK

#define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000

Definition at line 3208 of file if_iwmreg.h.

◆ IWM_OFFCHANNEL_QUEUE

#define IWM_OFFCHANNEL_QUEUE 8

Definition at line 1966 of file if_iwmreg.h.

◆ IWM_OFFLOADS_QUERY_CMD

#define IWM_OFFLOADS_QUERY_CMD 0xd5

Definition at line 2108 of file if_iwmreg.h.

◆ IWM_OSC_CLK

#define IWM_OSC_CLK (0xa04068)

Definition at line 1426 of file if_iwmreg.h.

◆ IWM_OSC_CLK_FORCE_CONTROL

#define IWM_OSC_CLK_FORCE_CONTROL (0x8)

Definition at line 1427 of file if_iwmreg.h.

◆ IWM_PAGE_2_EXP_SIZE

#define IWM_PAGE_2_EXP_SIZE 12 /* 4K == 2^12 */

Definition at line 2435 of file if_iwmreg.h.

◆ IWM_PAGE_PER_GROUP_2_EXP_SIZE

#define IWM_PAGE_PER_GROUP_2_EXP_SIZE 3

Definition at line 2437 of file if_iwmreg.h.

◆ IWM_PAGING_ADDR_SIG

#define IWM_PAGING_ADDR_SIG 0xAA000000

Definition at line 2455 of file if_iwmreg.h.

◆ IWM_PAGING_BLOCK_SIZE

#define IWM_PAGING_BLOCK_SIZE (IWM_NUM_OF_PAGE_PER_GROUP * IWM_FW_PAGING_SIZE)

Definition at line 2441 of file if_iwmreg.h.

◆ IWM_PAGING_CMD_IS_ENABLED

#define IWM_PAGING_CMD_IS_ENABLED (1 << 8)

Definition at line 2458 of file if_iwmreg.h.

◆ IWM_PAGING_CMD_IS_SECURED

#define IWM_PAGING_CMD_IS_SECURED (1 << 9)

Definition at line 2457 of file if_iwmreg.h.

◆ IWM_PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS

#define IWM_PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS 0

Definition at line 2459 of file if_iwmreg.h.

◆ IWM_PAGING_SEPARATOR_SECTION

#define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB

Definition at line 981 of file if_iwmreg.h.

◆ IWM_PAGING_TLV_SECURE_MASK

#define IWM_PAGING_TLV_SECURE_MASK 1

Definition at line 2460 of file if_iwmreg.h.

◆ IWM_PHY_BAND_24

#define IWM_PHY_BAND_24 (1)

Definition at line 3052 of file if_iwmreg.h.

◆ IWM_PHY_BAND_5

#define IWM_PHY_BAND_5 (0)

Definition at line 3051 of file if_iwmreg.h.

◆ IWM_PHY_CFG_PRODUCT_NUMBER

#define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))

Definition at line 2242 of file if_iwmreg.h.

◆ IWM_PHY_CFG_RADIO_DASH

#define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))

Definition at line 2241 of file if_iwmreg.h.

◆ IWM_PHY_CFG_RADIO_STEP

#define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))

Definition at line 2240 of file if_iwmreg.h.

◆ IWM_PHY_CFG_RADIO_TYPE

#define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))

Definition at line 2239 of file if_iwmreg.h.

◆ IWM_PHY_CFG_RX_CHAIN_A

#define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)

Definition at line 2246 of file if_iwmreg.h.

◆ IWM_PHY_CFG_RX_CHAIN_B

#define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)

Definition at line 2247 of file if_iwmreg.h.

◆ IWM_PHY_CFG_RX_CHAIN_C

#define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)

Definition at line 2248 of file if_iwmreg.h.

◆ IWM_PHY_CFG_TX_CHAIN_A

#define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)

Definition at line 2243 of file if_iwmreg.h.

◆ IWM_PHY_CFG_TX_CHAIN_B

#define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)

Definition at line 2244 of file if_iwmreg.h.

◆ IWM_PHY_CFG_TX_CHAIN_C

#define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)

Definition at line 2245 of file if_iwmreg.h.

◆ IWM_PHY_CONFIGURATION_CMD

#define IWM_PHY_CONFIGURATION_CMD 0x6a

Definition at line 2044 of file if_iwmreg.h.

◆ IWM_PHY_CONTEXT_CMD

#define IWM_PHY_CONTEXT_CMD 0x8

Definition at line 1987 of file if_iwmreg.h.

◆ IWM_PHY_DB_CMD

#define IWM_PHY_DB_CMD 0x6c

Definition at line 2046 of file if_iwmreg.h.

◆ IWM_PHY_INFO_FLAG_SHPREAMBLE

#define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)

Definition at line 3244 of file if_iwmreg.h.

◆ IWM_PHY_OPS_GROUP

#define IWM_PHY_OPS_GROUP 0x4

Definition at line 2144 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_CNT_MSK

#define IWM_PHY_RX_CHAIN_CNT_MSK (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)

Definition at line 3124 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_CNT_POS

#define IWM_PHY_RX_CHAIN_CNT_POS (10)

Definition at line 3123 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK

#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)

Definition at line 3112 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS

#define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)

Definition at line 3111 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK

#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)

Definition at line 3121 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS

#define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)

Definition at line 3120 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_FORCE_SEL_MSK

#define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)

Definition at line 3118 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_FORCE_SEL_POS

#define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)

Definition at line 3117 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_MIMO_CNT_MSK

#define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)

Definition at line 3127 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_MIMO_CNT_POS

#define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)

Definition at line 3126 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK

#define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)

Definition at line 3130 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_MIMO_FORCE_POS

#define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)

Definition at line 3129 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_VALID_MSK

#define IWM_PHY_RX_CHAIN_VALID_MSK (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)

Definition at line 3115 of file if_iwmreg.h.

◆ IWM_PHY_RX_CHAIN_VALID_POS

#define IWM_PHY_RX_CHAIN_VALID_POS (1)

Definition at line 3114 of file if_iwmreg.h.

◆ IWM_PHY_VHT_CHANNEL_MODE160

#define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)

Definition at line 3058 of file if_iwmreg.h.

◆ IWM_PHY_VHT_CHANNEL_MODE20

#define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)

Definition at line 3055 of file if_iwmreg.h.

◆ IWM_PHY_VHT_CHANNEL_MODE40

#define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)

Definition at line 3056 of file if_iwmreg.h.

◆ IWM_PHY_VHT_CHANNEL_MODE80

#define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)

Definition at line 3057 of file if_iwmreg.h.

◆ IWM_PHY_VHT_CTRL_POS_1_ABOVE

#define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)

Definition at line 3076 of file if_iwmreg.h.

◆ IWM_PHY_VHT_CTRL_POS_1_BELOW

#define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)

Definition at line 3072 of file if_iwmreg.h.

◆ IWM_PHY_VHT_CTRL_POS_2_ABOVE

#define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)

Definition at line 3077 of file if_iwmreg.h.

◆ IWM_PHY_VHT_CTRL_POS_2_BELOW

#define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)

Definition at line 3073 of file if_iwmreg.h.

◆ IWM_PHY_VHT_CTRL_POS_3_ABOVE

#define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)

Definition at line 3078 of file if_iwmreg.h.

◆ IWM_PHY_VHT_CTRL_POS_3_BELOW

#define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)

Definition at line 3074 of file if_iwmreg.h.

◆ IWM_PHY_VHT_CTRL_POS_4_ABOVE

#define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)

Definition at line 3079 of file if_iwmreg.h.

◆ IWM_PHY_VHT_CTRL_POS_4_BELOW

#define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)

Definition at line 3075 of file if_iwmreg.h.

◆ IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK

#define IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9)

Definition at line 4206 of file if_iwmreg.h.

◆ IWM_POWER_FLAGS_BT_SCO_ENA

#define IWM_POWER_FLAGS_BT_SCO_ENA (1 << 8)

Definition at line 4205 of file if_iwmreg.h.

◆ IWM_POWER_FLAGS_LPRX_ENA_MSK

#define IWM_POWER_FLAGS_LPRX_ENA_MSK (1 << 11)

Definition at line 4207 of file if_iwmreg.h.

◆ IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK

#define IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1)

Definition at line 4202 of file if_iwmreg.h.

◆ IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK

#define IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)

Masks for iwm_mac_power_cmd command flags @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off receiver and transmitter. '0' - does not allow. @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management, '1' Driver enables PM (use rest of parameters) @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM, '1' PM could sleep over DTIM till listen Interval. @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all access categories are both delivery and trigger enabled. @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and PBW Snoozing enabled @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable. @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving detection enablement

Definition at line 4201 of file if_iwmreg.h.

◆ IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK

#define IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2)

Definition at line 4203 of file if_iwmreg.h.

◆ IWM_POWER_FLAGS_SNOOZE_ENA_MSK

#define IWM_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5)

Definition at line 4204 of file if_iwmreg.h.

◆ IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK

#define IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12)

Definition at line 4208 of file if_iwmreg.h.

◆ IWM_POWER_LPRX_RSSI_THRESHOLD

#define IWM_POWER_LPRX_RSSI_THRESHOLD 75

Definition at line 4180 of file if_iwmreg.h.

◆ IWM_POWER_LPRX_RSSI_THRESHOLD_MAX

#define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94

Definition at line 4181 of file if_iwmreg.h.

◆ IWM_POWER_LPRX_RSSI_THRESHOLD_MIN

#define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30

Definition at line 4182 of file if_iwmreg.h.

◆ IWM_POWER_SCHEME_BPS

#define IWM_POWER_SCHEME_BPS 2

Definition at line 6877 of file if_iwmreg.h.

◆ IWM_POWER_SCHEME_CAM

#define IWM_POWER_SCHEME_CAM 1

Definition at line 6876 of file if_iwmreg.h.

◆ IWM_POWER_SCHEME_LP

#define IWM_POWER_SCHEME_LP 3

Definition at line 6878 of file if_iwmreg.h.

◆ IWM_POWER_TABLE_CMD

#define IWM_POWER_TABLE_CMD 0x77

Definition at line 2049 of file if_iwmreg.h.

◆ IWM_POWER_VEC_SIZE

#define IWM_POWER_VEC_SIZE 5

Definition at line 4210 of file if_iwmreg.h.

◆ IWM_PREG_AUX_BUS_WPROT_0

#define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0

Definition at line 628 of file if_iwmreg.h.

◆ IWM_PREG_PRPH_WPROT_22000

#define IWM_PREG_PRPH_WPROT_22000 0xa04d00

Definition at line 630 of file if_iwmreg.h.

◆ IWM_PREG_PRPH_WPROT_9000

#define IWM_PREG_PRPH_WPROT_9000 0xa04ce0

Definition at line 629 of file if_iwmreg.h.

◆ IWM_PREG_WFPM_ACCESS

#define IWM_PREG_WFPM_ACCESS (1 << 12)

Definition at line 644 of file if_iwmreg.h.

◆ IWM_PROBE_OPTION_MAX

#define IWM_PROBE_OPTION_MAX 20

Definition at line 5366 of file if_iwmreg.h.

◆ IWM_PROT_OFFLOAD_CONFIG_CMD

#define IWM_PROT_OFFLOAD_CONFIG_CMD 0xd4

Definition at line 2107 of file if_iwmreg.h.

◆ IWM_PROT_OFFLOAD_GROUP

#define IWM_PROT_OFFLOAD_GROUP 0xb

Definition at line 2146 of file if_iwmreg.h.

◆ IWM_PRPH_BASE

#define IWM_PRPH_BASE (0x00000)

Definition at line 1202 of file if_iwmreg.h.

◆ IWM_PRPH_END

#define IWM_PRPH_END (0xFFFFF)

Definition at line 1203 of file if_iwmreg.h.

◆ IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION

#define IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78

Definition at line 2050 of file if_iwmreg.h.

◆ IWM_QUOTA_LOW_LATENCY_NONE

#define IWM_QUOTA_LOW_LATENCY_NONE 0

Definition at line 3016 of file if_iwmreg.h.

◆ IWM_QUOTA_LOW_LATENCY_RX

#define IWM_QUOTA_LOW_LATENCY_RX (1 << 1)

Definition at line 3018 of file if_iwmreg.h.

◆ IWM_QUOTA_LOW_LATENCY_TX

#define IWM_QUOTA_LOW_LATENCY_TX (1 << 0)

Definition at line 3017 of file if_iwmreg.h.

◆ IWM_RADIO_CFG

#define IWM_RADIO_CFG 1

Definition at line 2317 of file if_iwmreg.h.

◆ IWM_RADIO_CFG_8000

#define IWM_RADIO_CFG_8000 0

Definition at line 2335 of file if_iwmreg.h.

◆ IWM_RADIO_REG_SYS_MANUAL_DFT_0

#define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078

Definition at line 615 of file if_iwmreg.h.

◆ IWM_RADIO_VERSION_NOTIFICATION

#define IWM_RADIO_VERSION_NOTIFICATION 0x68

Definition at line 2028 of file if_iwmreg.h.

◆ IWM_RATE_11M_PLCP

#define IWM_RATE_11M_PLCP 110

Definition at line 4539 of file if_iwmreg.h.

◆ IWM_RATE_12M_PLCP

#define IWM_RATE_12M_PLCP 5

Definition at line 4530 of file if_iwmreg.h.

◆ IWM_RATE_18M_PLCP

#define IWM_RATE_18M_PLCP 7

Definition at line 4531 of file if_iwmreg.h.

◆ IWM_RATE_1M_PLCP

#define IWM_RATE_1M_PLCP 10

Definition at line 4536 of file if_iwmreg.h.

◆ IWM_RATE_24M_PLCP

#define IWM_RATE_24M_PLCP 9

Definition at line 4532 of file if_iwmreg.h.

◆ IWM_RATE_2M_PLCP

#define IWM_RATE_2M_PLCP 20

Definition at line 4537 of file if_iwmreg.h.

◆ IWM_RATE_36M_PLCP

#define IWM_RATE_36M_PLCP 11

Definition at line 4533 of file if_iwmreg.h.

◆ IWM_RATE_48M_PLCP

#define IWM_RATE_48M_PLCP 1

Definition at line 4534 of file if_iwmreg.h.

◆ IWM_RATE_54M_PLCP

#define IWM_RATE_54M_PLCP 3

Definition at line 4535 of file if_iwmreg.h.

◆ IWM_RATE_5M_PLCP

#define IWM_RATE_5M_PLCP 55

Definition at line 4538 of file if_iwmreg.h.

◆ IWM_RATE_6M_PLCP

#define IWM_RATE_6M_PLCP 13

Definition at line 4528 of file if_iwmreg.h.

◆ IWM_RATE_9M_PLCP

#define IWM_RATE_9M_PLCP 15

Definition at line 4529 of file if_iwmreg.h.

◆ IWM_RATE_BIT_MSK

#define IWM_RATE_BIT_MSK ( r ) (1 << (IWM_RATE_##r##M_INDEX))

Definition at line 4525 of file if_iwmreg.h.

◆ IWM_RATE_HT_MCS_GF_MSK

#define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)

Definition at line 4604 of file if_iwmreg.h.

◆ IWM_RATE_HT_MCS_GF_POS

#define IWM_RATE_HT_MCS_GF_POS 10

Definition at line 4603 of file if_iwmreg.h.

◆ IWM_RATE_HT_MCS_INDEX_MSK

#define IWM_RATE_HT_MCS_INDEX_MSK 0x3f

Definition at line 4606 of file if_iwmreg.h.

◆ IWM_RATE_HT_MCS_NSS_MSK

#define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)

Definition at line 4600 of file if_iwmreg.h.

◆ IWM_RATE_HT_MCS_NSS_POS

#define IWM_RATE_HT_MCS_NSS_POS 3

Definition at line 4599 of file if_iwmreg.h.

◆ IWM_RATE_HT_MCS_RATE_CODE_MSK

#define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7

Definition at line 4598 of file if_iwmreg.h.

◆ IWM_RATE_HT_MIMO2_MCS_10_PLCP

#define IWM_RATE_HT_MIMO2_MCS_10_PLCP 0xA

Definition at line 4450 of file if_iwmreg.h.

◆ IWM_RATE_HT_MIMO2_MCS_11_PLCP

#define IWM_RATE_HT_MIMO2_MCS_11_PLCP 0xB

Definition at line 4451 of file if_iwmreg.h.

◆ IWM_RATE_HT_MIMO2_MCS_12_PLCP

#define IWM_RATE_HT_MIMO2_MCS_12_PLCP 0xC

Definition at line 4452 of file if_iwmreg.h.

◆ IWM_RATE_HT_MIMO2_MCS_13_PLCP

#define IWM_RATE_HT_MIMO2_MCS_13_PLCP 0xD

Definition at line 4453 of file if_iwmreg.h.

◆ IWM_RATE_HT_MIMO2_MCS_14_PLCP

#define IWM_RATE_HT_MIMO2_MCS_14_PLCP 0xE

Definition at line 4454 of file if_iwmreg.h.

◆ IWM_RATE_HT_MIMO2_MCS_15_PLCP

#define IWM_RATE_HT_MIMO2_MCS_15_PLCP 0xF

Definition at line 4455 of file if_iwmreg.h.

◆ IWM_RATE_HT_MIMO2_MCS_8_PLCP

#define IWM_RATE_HT_MIMO2_MCS_8_PLCP 0x8

Definition at line 4448 of file if_iwmreg.h.

◆ IWM_RATE_HT_MIMO2_MCS_9_PLCP

#define IWM_RATE_HT_MIMO2_MCS_9_PLCP 0x9

Definition at line 4449 of file if_iwmreg.h.

◆ IWM_RATE_HT_MIMO2_MCS_INV_PLCP

#define IWM_RATE_HT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP

Definition at line 4477 of file if_iwmreg.h.

◆ IWM_RATE_HT_SISO_MCS_0_PLCP

#define IWM_RATE_HT_SISO_MCS_0_PLCP 0

Definition at line 4440 of file if_iwmreg.h.

◆ IWM_RATE_HT_SISO_MCS_1_PLCP

#define IWM_RATE_HT_SISO_MCS_1_PLCP 1

Definition at line 4441 of file if_iwmreg.h.

◆ IWM_RATE_HT_SISO_MCS_2_PLCP

#define IWM_RATE_HT_SISO_MCS_2_PLCP 2

Definition at line 4442 of file if_iwmreg.h.

◆ IWM_RATE_HT_SISO_MCS_3_PLCP

#define IWM_RATE_HT_SISO_MCS_3_PLCP 3

Definition at line 4443 of file if_iwmreg.h.

◆ IWM_RATE_HT_SISO_MCS_4_PLCP

#define IWM_RATE_HT_SISO_MCS_4_PLCP 4

Definition at line 4444 of file if_iwmreg.h.

◆ IWM_RATE_HT_SISO_MCS_5_PLCP

#define IWM_RATE_HT_SISO_MCS_5_PLCP 5

Definition at line 4445 of file if_iwmreg.h.

◆ IWM_RATE_HT_SISO_MCS_6_PLCP

#define IWM_RATE_HT_SISO_MCS_6_PLCP 6

Definition at line 4446 of file if_iwmreg.h.

◆ IWM_RATE_HT_SISO_MCS_7_PLCP

#define IWM_RATE_HT_SISO_MCS_7_PLCP 7

Definition at line 4447 of file if_iwmreg.h.

◆ IWM_RATE_HT_SISO_MCS_8_PLCP

#define IWM_RATE_HT_SISO_MCS_8_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP

Definition at line 4480 of file if_iwmreg.h.

◆ IWM_RATE_HT_SISO_MCS_9_PLCP

#define IWM_RATE_HT_SISO_MCS_9_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP

Definition at line 4481 of file if_iwmreg.h.

◆ IWM_RATE_HT_SISO_MCS_INV_PLCP

#define IWM_RATE_HT_SISO_MCS_INV_PLCP 0x20

Definition at line 4476 of file if_iwmreg.h.

◆ IWM_RATE_INVM_PLCP

#define IWM_RATE_INVM_PLCP 0xff

Definition at line 4540 of file if_iwmreg.h.

◆ IWM_RATE_LEGACY_RATE_MSK

#define IWM_RATE_LEGACY_RATE_MSK 0xff

Definition at line 4645 of file if_iwmreg.h.

◆ IWM_RATE_MCS_ANT_A_MSK

#define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)

Definition at line 4665 of file if_iwmreg.h.

◆ IWM_RATE_MCS_ANT_AB_MSK

#define IWM_RATE_MCS_ANT_AB_MSK

Value:

(IWM_RATE_MCS_ANT_A_MSK | \

IWM_RATE_MCS_ANT_B_MSK)

IWM_RATE_MCS_ANT_A_MSK

#define IWM_RATE_MCS_ANT_A_MSK

Definition: if_iwmreg.h:4665

Definition at line 4668 of file if_iwmreg.h.

◆ IWM_RATE_MCS_ANT_ABC_MSK

#define IWM_RATE_MCS_ANT_ABC_MSK

Value:

(IWM_RATE_MCS_ANT_AB_MSK | \

IWM_RATE_MCS_ANT_C_MSK)

IWM_RATE_MCS_ANT_AB_MSK

#define IWM_RATE_MCS_ANT_AB_MSK

Definition: if_iwmreg.h:4668

Definition at line 4670 of file if_iwmreg.h.

◆ IWM_RATE_MCS_ANT_B_MSK

#define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)

Definition at line 4666 of file if_iwmreg.h.

◆ IWM_RATE_MCS_ANT_C_MSK

#define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)

Definition at line 4667 of file if_iwmreg.h.

◆ IWM_RATE_MCS_ANT_MSK

#define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK

Definition at line 4672 of file if_iwmreg.h.

◆ IWM_RATE_MCS_ANT_NUM

#define IWM_RATE_MCS_ANT_NUM 3

Definition at line 4673 of file if_iwmreg.h.

◆ IWM_RATE_MCS_ANT_POS

#define IWM_RATE_MCS_ANT_POS 14

Definition at line 4664 of file if_iwmreg.h.

◆ IWM_RATE_MCS_BF_MSK

#define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)

Definition at line 4681 of file if_iwmreg.h.

◆ IWM_RATE_MCS_BF_POS

#define IWM_RATE_MCS_BF_POS 19

Definition at line 4680 of file if_iwmreg.h.

◆ IWM_RATE_MCS_CCK_MSK

#define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)

Definition at line 4565 of file if_iwmreg.h.

◆ IWM_RATE_MCS_CCK_POS

#define IWM_RATE_MCS_CCK_POS 9

Definition at line 4564 of file if_iwmreg.h.

◆ IWM_RATE_MCS_CHAN_WIDTH_160

#define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)

Definition at line 4657 of file if_iwmreg.h.

◆ IWM_RATE_MCS_CHAN_WIDTH_20

#define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)

Definition at line 4654 of file if_iwmreg.h.

◆ IWM_RATE_MCS_CHAN_WIDTH_40

#define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)

Definition at line 4655 of file if_iwmreg.h.

◆ IWM_RATE_MCS_CHAN_WIDTH_80

#define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)

Definition at line 4656 of file if_iwmreg.h.

◆ IWM_RATE_MCS_CHAN_WIDTH_MSK

#define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)

Definition at line 4653 of file if_iwmreg.h.

◆ IWM_RATE_MCS_CHAN_WIDTH_POS

#define IWM_RATE_MCS_CHAN_WIDTH_POS 11

Definition at line 4652 of file if_iwmreg.h.

◆ IWM_RATE_MCS_DUP_MSK

#define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)

Definition at line 4689 of file if_iwmreg.h.

◆ IWM_RATE_MCS_DUP_POS

#define IWM_RATE_MCS_DUP_POS 24

Definition at line 4688 of file if_iwmreg.h.

◆ IWM_RATE_MCS_HT_MSK

#define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)

Definition at line 4561 of file if_iwmreg.h.

◆ IWM_RATE_MCS_HT_POS

#define IWM_RATE_MCS_HT_POS 8

Definition at line 4560 of file if_iwmreg.h.

◆ IWM_RATE_MCS_LDPC_MSK

#define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)

Definition at line 4693 of file if_iwmreg.h.

◆ IWM_RATE_MCS_LDPC_POS

#define IWM_RATE_MCS_LDPC_POS 27

Definition at line 4692 of file if_iwmreg.h.

◆ IWM_RATE_MCS_RTS_REQUIRED_MSK

#define IWM_RATE_MCS_RTS_REQUIRED_MSK (1 << IWM_RATE_MCS_RTS_REQUIRED_POS)

Definition at line 4573 of file if_iwmreg.h.

◆ IWM_RATE_MCS_RTS_REQUIRED_POS

#define IWM_RATE_MCS_RTS_REQUIRED_POS 30

Definition at line 4572 of file if_iwmreg.h.

◆ IWM_RATE_MCS_SGI_MSK

#define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)

Definition at line 4661 of file if_iwmreg.h.

◆ IWM_RATE_MCS_SGI_POS

#define IWM_RATE_MCS_SGI_POS 13

Definition at line 4660 of file if_iwmreg.h.

◆ IWM_RATE_MCS_STBC_MSK

#define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)

Definition at line 4677 of file if_iwmreg.h.

◆ IWM_RATE_MCS_STBC_POS

#define IWM_RATE_MCS_STBC_POS 17

Definition at line 4676 of file if_iwmreg.h.

◆ IWM_RATE_MCS_VHT_MSK

#define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)

Definition at line 4569 of file if_iwmreg.h.

◆ IWM_RATE_MCS_VHT_POS

#define IWM_RATE_MCS_VHT_POS 26

Definition at line 4568 of file if_iwmreg.h.

◆ IWM_RATE_MCS_ZLF_MSK

#define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)

Definition at line 4685 of file if_iwmreg.h.

◆ IWM_RATE_MCS_ZLF_POS

#define IWM_RATE_MCS_ZLF_POS 20

Definition at line 4684 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MCS_NSS_MSK

#define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)

Definition at line 4621 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MCS_NSS_POS

#define IWM_RATE_VHT_MCS_NSS_POS 4

Definition at line 4620 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MCS_RATE_CODE_MSK

#define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf

Definition at line 4619 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MIMO2_MCS_0_PLCP

#define IWM_RATE_VHT_MIMO2_MCS_0_PLCP 0x10

Definition at line 4466 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MIMO2_MCS_1_PLCP

#define IWM_RATE_VHT_MIMO2_MCS_1_PLCP 0x11

Definition at line 4467 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MIMO2_MCS_2_PLCP

#define IWM_RATE_VHT_MIMO2_MCS_2_PLCP 0x12

Definition at line 4468 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MIMO2_MCS_3_PLCP

#define IWM_RATE_VHT_MIMO2_MCS_3_PLCP 0x13

Definition at line 4469 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MIMO2_MCS_4_PLCP

#define IWM_RATE_VHT_MIMO2_MCS_4_PLCP 0x14

Definition at line 4470 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MIMO2_MCS_5_PLCP

#define IWM_RATE_VHT_MIMO2_MCS_5_PLCP 0x15

Definition at line 4471 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MIMO2_MCS_6_PLCP

#define IWM_RATE_VHT_MIMO2_MCS_6_PLCP 0x16

Definition at line 4472 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MIMO2_MCS_7_PLCP

#define IWM_RATE_VHT_MIMO2_MCS_7_PLCP 0x17

Definition at line 4473 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MIMO2_MCS_8_PLCP

#define IWM_RATE_VHT_MIMO2_MCS_8_PLCP 0x18

Definition at line 4474 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MIMO2_MCS_9_PLCP

#define IWM_RATE_VHT_MIMO2_MCS_9_PLCP 0x19

Definition at line 4475 of file if_iwmreg.h.

◆ IWM_RATE_VHT_MIMO2_MCS_INV_PLCP

#define IWM_RATE_VHT_MIMO2_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP

Definition at line 4479 of file if_iwmreg.h.

◆ IWM_RATE_VHT_SISO_MCS_0_PLCP

#define IWM_RATE_VHT_SISO_MCS_0_PLCP 0

Definition at line 4456 of file if_iwmreg.h.

◆ IWM_RATE_VHT_SISO_MCS_1_PLCP

#define IWM_RATE_VHT_SISO_MCS_1_PLCP 1

Definition at line 4457 of file if_iwmreg.h.

◆ IWM_RATE_VHT_SISO_MCS_2_PLCP

#define IWM_RATE_VHT_SISO_MCS_2_PLCP 2

Definition at line 4458 of file if_iwmreg.h.

◆ IWM_RATE_VHT_SISO_MCS_3_PLCP

#define IWM_RATE_VHT_SISO_MCS_3_PLCP 3

Definition at line 4459 of file if_iwmreg.h.

◆ IWM_RATE_VHT_SISO_MCS_4_PLCP

#define IWM_RATE_VHT_SISO_MCS_4_PLCP 4

Definition at line 4460 of file if_iwmreg.h.

◆ IWM_RATE_VHT_SISO_MCS_5_PLCP

#define IWM_RATE_VHT_SISO_MCS_5_PLCP 5

Definition at line 4461 of file if_iwmreg.h.

◆ IWM_RATE_VHT_SISO_MCS_6_PLCP

#define IWM_RATE_VHT_SISO_MCS_6_PLCP 6

Definition at line 4462 of file if_iwmreg.h.

◆ IWM_RATE_VHT_SISO_MCS_7_PLCP

#define IWM_RATE_VHT_SISO_MCS_7_PLCP 7

Definition at line 4463 of file if_iwmreg.h.

◆ IWM_RATE_VHT_SISO_MCS_8_PLCP

#define IWM_RATE_VHT_SISO_MCS_8_PLCP 8

Definition at line 4464 of file if_iwmreg.h.

◆ IWM_RATE_VHT_SISO_MCS_9_PLCP

#define IWM_RATE_VHT_SISO_MCS_9_PLCP 9

Definition at line 4465 of file if_iwmreg.h.

◆ IWM_RATE_VHT_SISO_MCS_INV_PLCP

#define IWM_RATE_VHT_SISO_MCS_INV_PLCP IWM_RATE_HT_SISO_MCS_INV_PLCP

Definition at line 4478 of file if_iwmreg.h.

◆ IWM_RBD_FETCH_IDLE

#define IWM_RBD_FETCH_IDLE (1 << 29)

Definition at line 492 of file if_iwmreg.h.

◆ IWM_READ

#define IWM_READ	(	sc,
		reg
	)	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))

Definition at line 6954 of file if_iwmreg.h.

◆ IWM_REDUCE_TX_POWER_CMD

#define IWM_REDUCE_TX_POWER_CMD 0x9f

Definition at line 2066 of file if_iwmreg.h.

◆ IWM_RELEASE_CPU_RESET

#define IWM_RELEASE_CPU_RESET 0x300c

Definition at line 1248 of file if_iwmreg.h.

◆ IWM_RELEASE_CPU_RESET_BIT

#define IWM_RELEASE_CPU_RESET_BIT 0x1000000

Definition at line 1249 of file if_iwmreg.h.

◆ IWM_REMOTE_WAKE_CONFIG_CMD

#define IWM_REMOTE_WAKE_CONFIG_CMD 0xd6

Definition at line 2109 of file if_iwmreg.h.

◆ IWM_REMOVE_STA

#define IWM_REMOVE_STA 0x19

Definition at line 2000 of file if_iwmreg.h.

◆ IWM_REPLY_BEACON_FILTERING_CMD

#define IWM_REPLY_BEACON_FILTERING_CMD 0xd2

Definition at line 2094 of file if_iwmreg.h.

◆ IWM_REPLY_DEBUG_CMD

#define IWM_REPLY_DEBUG_CMD 0xf0

Definition at line 2100 of file if_iwmreg.h.

◆ IWM_REPLY_ERROR

#define IWM_REPLY_ERROR 0x2

Definition at line 1983 of file if_iwmreg.h.

◆ IWM_REPLY_MAX

#define IWM_REPLY_MAX 0xff

Definition at line 2130 of file if_iwmreg.h.

◆ IWM_REPLY_RX_MPDU_CMD

#define IWM_REPLY_RX_MPDU_CMD 0xc1

Definition at line 2080 of file if_iwmreg.h.

◆ IWM_REPLY_RX_PHY_CMD

#define IWM_REPLY_RX_PHY_CMD 0xc0

Definition at line 2079 of file if_iwmreg.h.

◆ IWM_REPLY_SF_CFG_CMD

#define IWM_REPLY_SF_CFG_CMD 0xd1

Definition at line 2093 of file if_iwmreg.h.

◆ IWM_REPLY_THERMAL_MNG_BACKOFF

#define IWM_REPLY_THERMAL_MNG_BACKOFF 0x7e

Definition at line 2054 of file if_iwmreg.h.

◆ IWM_RFH_DMA_EN_ENABLE_VAL

#define IWM_RFH_DMA_EN_ENABLE_VAL (1U << 31)

Definition at line 530 of file if_iwmreg.h.

◆ IWM_RFH_DMA_EN_MASK

#define IWM_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/

Definition at line 529 of file if_iwmreg.h.

◆ IWM_RFH_GEN_CFG

#define IWM_RFH_GEN_CFG 0xA09800

Definition at line 534 of file if_iwmreg.h.

◆ IWM_RFH_GEN_CFG_DEFAULT_RXQ_NUM

#define IWM_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00

Definition at line 540 of file if_iwmreg.h.

◆ IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128

#define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010

Definition at line 537 of file if_iwmreg.h.

◆ IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64

#define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000

Definition at line 538 of file if_iwmreg.h.

◆ IWM_RFH_GEN_CFG_RFH_DMA_SNOOP

#define IWM_RFH_GEN_CFG_RFH_DMA_SNOOP (1 << 1)

Definition at line 536 of file if_iwmreg.h.

◆ IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP

#define IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0)

Definition at line 535 of file if_iwmreg.h.

◆ IWM_RFH_GEN_STATUS

#define IWM_RFH_GEN_STATUS 0xA09808

RFH Status Register

Bit fields:

Bit 29: RBD_FETCH_IDLE This status flag is set by the RFH when there is no active RBD fetch from DRAM. Once the RFH RBD controller starts fetching (or when there is a pending RBD read response from DRAM), this flag is immediately turned off.

Bit 30: SRAM_DMA_IDLE This status flag is set by the RFH when there is no active transaction from SRAM to DRAM. Once the SRAM to DRAM DMA is active, this flag is immediately turned off.

Bit 31: RXF_DMA_IDLE This status flag is set by the RFH when there is no active transaction from RXF to DRAM. Once the RXF-to-DRAM DMA is active, this flag is immediately turned off.

Definition at line 490 of file if_iwmreg.h.

◆ IWM_RFH_GEN_STATUS_GEN3

#define IWM_RFH_GEN_STATUS_GEN3 0xA07824

Definition at line 491 of file if_iwmreg.h.

◆ IWM_RFH_Q0_FRBDCB_BA_LSB

#define IWM_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */

Definition at line 441 of file if_iwmreg.h.

◆ IWM_RFH_Q0_FRBDCB_RIDX

#define IWM_RFH_Q0_FRBDCB_RIDX 0xA080C0

Definition at line 450 of file if_iwmreg.h.

◆ IWM_RFH_Q0_FRBDCB_WIDX

#define IWM_RFH_Q0_FRBDCB_WIDX 0xA08080

Definition at line 444 of file if_iwmreg.h.

◆ IWM_RFH_Q0_FRBDCB_WIDX_TRG

#define IWM_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80

Definition at line 447 of file if_iwmreg.h.

◆ IWM_RFH_Q0_ORB_WPTR_LSB

#define IWM_RFH_Q0_ORB_WPTR_LSB 0xA08280

Definition at line 464 of file if_iwmreg.h.

◆ IWM_RFH_Q0_URBD_STTS_WPTR_LSB

#define IWM_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */

Definition at line 461 of file if_iwmreg.h.

◆ IWM_RFH_Q0_URBDCB_BA_LSB

#define IWM_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */

Definition at line 453 of file if_iwmreg.h.

◆ IWM_RFH_Q0_URBDCB_VAID

#define IWM_RFH_Q0_URBDCB_VAID 0xA081C0

Definition at line 458 of file if_iwmreg.h.

◆ IWM_RFH_Q0_URBDCB_WIDX

#define IWM_RFH_Q0_URBDCB_WIDX 0xA08180

Definition at line 456 of file if_iwmreg.h.

◆ IWM_RFH_Q_FRBDCB_BA_LSB

#define IWM_RFH_Q_FRBDCB_BA_LSB ( q ) (IWM_RFH_Q0_FRBDCB_BA_LSB + (q) * 8)

Definition at line 442 of file if_iwmreg.h.

◆ IWM_RFH_Q_FRBDCB_RIDX

#define IWM_RFH_Q_FRBDCB_RIDX ( q ) (IWM_RFH_Q0_FRBDCB_RIDX + (q) * 4)

Definition at line 451 of file if_iwmreg.h.

◆ IWM_RFH_Q_FRBDCB_WIDX

#define IWM_RFH_Q_FRBDCB_WIDX ( q ) (IWM_RFH_Q0_FRBDCB_WIDX + (q) * 4)

Definition at line 445 of file if_iwmreg.h.

◆ IWM_RFH_Q_FRBDCB_WIDX_TRG

#define IWM_RFH_Q_FRBDCB_WIDX_TRG ( q ) (IWM_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4)

Definition at line 448 of file if_iwmreg.h.

◆ IWM_RFH_Q_ORB_WPTR_LSB

#define IWM_RFH_Q_ORB_WPTR_LSB ( q ) (IWM_RFH_Q0_ORB_WPTR_LSB + (q) * 8)

Definition at line 465 of file if_iwmreg.h.

◆ IWM_RFH_Q_URBD_STTS_WPTR_LSB

#define IWM_RFH_Q_URBD_STTS_WPTR_LSB ( q ) (IWM_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)

Definition at line 462 of file if_iwmreg.h.

◆ IWM_RFH_Q_URBDCB_BA_LSB

#define IWM_RFH_Q_URBDCB_BA_LSB ( q ) (IWM_RFH_Q0_URBDCB_BA_LSB + (q) * 8)

Definition at line 454 of file if_iwmreg.h.

◆ IWM_RFH_Q_URBDCB_VAID

#define IWM_RFH_Q_URBDCB_VAID ( q ) (IWM_RFH_Q0_URBDCB_VAID + (q) * 4)

Definition at line 459 of file if_iwmreg.h.

◆ IWM_RFH_Q_URBDCB_WIDX

#define IWM_RFH_Q_URBDCB_WIDX ( q ) (IWM_RFH_Q0_URBDCB_WIDX + (q) * 4)

Definition at line 457 of file if_iwmreg.h.

◆ IWM_RFH_RBDBUF_RBD0_LSB

#define IWM_RFH_RBDBUF_RBD0_LSB 0xA08300

Definition at line 466 of file if_iwmreg.h.

◆ IWM_RFH_RBDBUF_RBD_LSB

#define IWM_RFH_RBDBUF_RBD_LSB ( q ) (IWM_RFH_RBDBUF_RBD0_LSB + (q) * 8)

Definition at line 467 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_CFG

#define IWM_RFH_RXF_DMA_CFG 0xA09820

Definition at line 497 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_CFG_GEN3

#define IWM_RFH_RXF_DMA_CFG_GEN3 0xA07880

Definition at line 498 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK

#define IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */

Definition at line 527 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_MIN_RB_4_8

#define IWM_RFH_RXF_DMA_MIN_RB_4_8 (3 << IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS)

Definition at line 526 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_MIN_RB_SIZE_MASK

#define IWM_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */

Definition at line 524 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS

#define IWM_RFH_RXF_DMA_MIN_RB_SIZE_POS 24

Definition at line 525 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RB_SIZE_12K

#define IWM_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWM_RFH_RXF_DMA_RB_SIZE_POS)

Definition at line 506 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RB_SIZE_16K

#define IWM_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWM_RFH_RXF_DMA_RB_SIZE_POS)

Definition at line 507 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RB_SIZE_1K

#define IWM_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWM_RFH_RXF_DMA_RB_SIZE_POS)

Definition at line 502 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RB_SIZE_20K

#define IWM_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWM_RFH_RXF_DMA_RB_SIZE_POS)

Definition at line 508 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RB_SIZE_24K

#define IWM_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWM_RFH_RXF_DMA_RB_SIZE_POS)

Definition at line 509 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RB_SIZE_28K

#define IWM_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWM_RFH_RXF_DMA_RB_SIZE_POS)

Definition at line 510 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RB_SIZE_2K

#define IWM_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWM_RFH_RXF_DMA_RB_SIZE_POS)

Definition at line 503 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RB_SIZE_32K

#define IWM_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWM_RFH_RXF_DMA_RB_SIZE_POS)

Definition at line 511 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RB_SIZE_4K

#define IWM_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWM_RFH_RXF_DMA_RB_SIZE_POS)

Definition at line 504 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RB_SIZE_8K

#define IWM_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWM_RFH_RXF_DMA_RB_SIZE_POS)

Definition at line 505 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RB_SIZE_MASK

#define IWM_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */

Definition at line 500 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RB_SIZE_POS

#define IWM_RFH_RXF_DMA_RB_SIZE_POS 16

Definition at line 501 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RBDCB_SIZE_1024

#define IWM_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

Definition at line 522 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RBDCB_SIZE_128

#define IWM_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

Definition at line 519 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RBDCB_SIZE_16

#define IWM_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

Definition at line 516 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RBDCB_SIZE_2048

#define IWM_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

Definition at line 523 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RBDCB_SIZE_256

#define IWM_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

Definition at line 520 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RBDCB_SIZE_32

#define IWM_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

Definition at line 517 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RBDCB_SIZE_512

#define IWM_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

Definition at line 521 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RBDCB_SIZE_64

#define IWM_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

Definition at line 518 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RBDCB_SIZE_8

#define IWM_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)

Definition at line 515 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RBDCB_SIZE_MASK

#define IWM_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */

Definition at line 513 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_RBDCB_SIZE_POS

#define IWM_RFH_RXF_DMA_RBDCB_SIZE_POS 20

Definition at line 514 of file if_iwmreg.h.

◆ IWM_RFH_RXF_DMA_SINGLE_FRAME_MASK

#define IWM_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */

Definition at line 528 of file if_iwmreg.h.

◆ IWM_RFH_RXF_RXQ_ACTIVE

#define IWM_RFH_RXF_RXQ_ACTIVE 0xA0980C

Definition at line 532 of file if_iwmreg.h.

◆ IWM_RFIC_REG_RD

#define IWM_RFIC_REG_RD 0xad0470

Definition at line 616 of file if_iwmreg.h.

◆ IWM_RSA_ENABLE

#define IWM_RSA_ENABLE 0xa24b08

Definition at line 627 of file if_iwmreg.h.

◆ IWM_RTS_DFAULT_RETRY_LIMIT

#define IWM_RTS_DFAULT_RETRY_LIMIT 3

Definition at line 4916 of file if_iwmreg.h.

◆ IWM_RX_FREE_BUFFERS

#define IWM_RX_FREE_BUFFERS 64

Definition at line 1812 of file if_iwmreg.h.

◆ IWM_RX_INFO_AGC_IDX

#define IWM_RX_INFO_AGC_IDX 1

Definition at line 3196 of file if_iwmreg.h.

◆ IWM_RX_INFO_ENERGY_ANT_A_MSK

#define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff

Definition at line 3189 of file if_iwmreg.h.

◆ IWM_RX_INFO_ENERGY_ANT_A_POS

#define IWM_RX_INFO_ENERGY_ANT_A_POS 0

Definition at line 3192 of file if_iwmreg.h.

◆ IWM_RX_INFO_ENERGY_ANT_ABC_IDX

#define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1

Definition at line 3188 of file if_iwmreg.h.

◆ IWM_RX_INFO_ENERGY_ANT_B_MSK

#define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00

Definition at line 3190 of file if_iwmreg.h.

◆ IWM_RX_INFO_ENERGY_ANT_B_POS

#define IWM_RX_INFO_ENERGY_ANT_B_POS 8

Definition at line 3193 of file if_iwmreg.h.

◆ IWM_RX_INFO_ENERGY_ANT_C_MSK

#define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000

Definition at line 3191 of file if_iwmreg.h.

◆ IWM_RX_INFO_ENERGY_ANT_C_POS

#define IWM_RX_INFO_ENERGY_ANT_C_POS 16

Definition at line 3194 of file if_iwmreg.h.

◆ IWM_RX_INFO_PHY_CNT

#define IWM_RX_INFO_PHY_CNT 8

Definition at line 3187 of file if_iwmreg.h.

◆ IWM_RX_INFO_RSSI_AB_IDX

#define IWM_RX_INFO_RSSI_AB_IDX 2

Definition at line 3197 of file if_iwmreg.h.

◆ IWM_RX_LOW_WATERMARK

#define IWM_RX_LOW_WATERMARK 8

Definition at line 1813 of file if_iwmreg.h.

◆ IWM_RX_MPDU_AMSDU_LAST_SUBFRAME

#define IWM_RX_MPDU_AMSDU_LAST_SUBFRAME 0x80

Definition at line 3357 of file if_iwmreg.h.

◆ IWM_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK

#define IWM_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK 0x7f

Definition at line 3356 of file if_iwmreg.h.

◆ IWM_RX_MPDU_MFLG1_ADDRTYPE_MASK

#define IWM_RX_MPDU_MFLG1_ADDRTYPE_MASK 0x03

Definition at line 3348 of file if_iwmreg.h.

◆ IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK

#define IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK 0xf0

Definition at line 3349 of file if_iwmreg.h.

◆ IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT

#define IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT 3

Definition at line 3350 of file if_iwmreg.h.

◆ IWM_RX_MPDU_MFLG2_AMSDU

#define IWM_RX_MPDU_MFLG2_AMSDU 0x40

Definition at line 3354 of file if_iwmreg.h.

◆ IWM_RX_MPDU_MFLG2_HDR_LEN_MASK

#define IWM_RX_MPDU_MFLG2_HDR_LEN_MASK 0x1f

Definition at line 3352 of file if_iwmreg.h.

◆ IWM_RX_MPDU_MFLG2_PAD

#define IWM_RX_MPDU_MFLG2_PAD 0x20

Definition at line 3353 of file if_iwmreg.h.

◆ IWM_RX_MPDU_PHY_AMPDU

#define IWM_RX_MPDU_PHY_AMPDU (1 << 5)

Definition at line 3359 of file if_iwmreg.h.

◆ IWM_RX_MPDU_PHY_AMPDU_TOGGLE

#define IWM_RX_MPDU_PHY_AMPDU_TOGGLE (1 << 6)

Definition at line 3360 of file if_iwmreg.h.

◆ IWM_RX_MPDU_PHY_NCCK_ADDTL_NTFY

#define IWM_RX_MPDU_PHY_NCCK_ADDTL_NTFY (1 << 7)

Definition at line 3362 of file if_iwmreg.h.

◆ IWM_RX_MPDU_PHY_SHORT_PREAMBLE

#define IWM_RX_MPDU_PHY_SHORT_PREAMBLE (1 << 7)

Definition at line 3361 of file if_iwmreg.h.

◆ IWM_RX_MPDU_PHY_TSF_OVERLOAD

#define IWM_RX_MPDU_PHY_TSF_OVERLOAD (1 << 8)

Definition at line 3363 of file if_iwmreg.h.

◆ IWM_RX_MPDU_REORDER_BA_OLD_SN

#define IWM_RX_MPDU_REORDER_BA_OLD_SN 0x80000000

Definition at line 3396 of file if_iwmreg.h.

◆ IWM_RX_MPDU_REORDER_BAID_MASK

#define IWM_RX_MPDU_REORDER_BAID_MASK 0x7f000000

Definition at line 3394 of file if_iwmreg.h.

◆ IWM_RX_MPDU_REORDER_BAID_SHIFT

#define IWM_RX_MPDU_REORDER_BAID_SHIFT 24

Definition at line 3395 of file if_iwmreg.h.

◆ IWM_RX_MPDU_REORDER_NSSN_MASK

#define IWM_RX_MPDU_REORDER_NSSN_MASK 0x00000fff

Definition at line 3391 of file if_iwmreg.h.

◆ IWM_RX_MPDU_REORDER_SN_MASK

#define IWM_RX_MPDU_REORDER_SN_MASK 0x00fff000

Definition at line 3392 of file if_iwmreg.h.

◆ IWM_RX_MPDU_REORDER_SN_SHIFT

#define IWM_RX_MPDU_REORDER_SN_SHIFT 12

Definition at line 3393 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK

#define IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000)

Definition at line 3346 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_CRC_OK

#define IWM_RX_MPDU_RES_STATUS_CRC_OK (1 << 0)

Values written by fw for each Rx packet @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND: @IWM_RX_MPDU_RES_STATUS_KEY_VALID: @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK: @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked in the driver. @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or alg = CCM only. Checks replay attack for 11w frames. Relevant only if IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP: @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK: @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK: @IWM_RX_MPDU_RES_STATUS_RRF_KILL: @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK: @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:

Definition at line 3320 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_DEC_DONE

#define IWM_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11)

Definition at line 3337 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP

#define IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13)

Definition at line 3339 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_FILTERING_MSK

#define IWM_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000)

Definition at line 3345 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK

#define IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000)

Definition at line 3342 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_ICV_OK

#define IWM_RX_MPDU_RES_STATUS_ICV_OK (1 << 5)

Definition at line 3325 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT

#define IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14)

Definition at line 3340 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK

#define IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4)

Definition at line 3324 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_KEY_VALID

#define IWM_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3)

Definition at line 3323 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_MIC_OK

#define IWM_RX_MPDU_RES_STATUS_MIC_OK (1 << 6)

Definition at line 3326 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR

#define IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7)

Definition at line 3328 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_OVERRUN_OK

#define IWM_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1)

Definition at line 3321 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP

#define IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12)

Definition at line 3338 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME

#define IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15)

Definition at line 3341 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_RRF_KILL

#define IWM_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29)

Definition at line 3344 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC

#define IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8)

Definition at line 3334 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC

#define IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8)

Definition at line 3331 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR

#define IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8)

Definition at line 3335 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK

#define IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8)

Definition at line 3336 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC

#define IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8)

Definition at line 3333 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC

#define IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8)

Definition at line 3329 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC

#define IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8)

Definition at line 3332 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC

#define IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8)

Definition at line 3330 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND

#define IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2)

Definition at line 3322 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_STA_ID_MSK

#define IWM_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000)

Definition at line 3343 of file if_iwmreg.h.

◆ IWM_RX_MPDU_RES_STATUS_TTAK_OK

#define IWM_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)

Definition at line 3327 of file if_iwmreg.h.

◆ IWM_RX_QUEUE_MASK

#define IWM_RX_QUEUE_MASK 255

Definition at line 1806 of file if_iwmreg.h.

◆ IWM_RX_QUEUE_SIZE

#define IWM_RX_QUEUE_SIZE 256

Definition at line 1805 of file if_iwmreg.h.

◆ IWM_RX_QUEUE_SIZE_LOG

#define IWM_RX_QUEUE_SIZE_LOG 8

Definition at line 1807 of file if_iwmreg.h.

◆ IWM_RX_RB_TIMEOUT

#define IWM_RX_RB_TIMEOUT (0x11)

Definition at line 1642 of file if_iwmreg.h.

◆ IWM_RX_REORDER_DATA_INVALID_BAID

#define IWM_RX_REORDER_DATA_INVALID_BAID 0x7f

Definition at line 3389 of file if_iwmreg.h.

◆ IWM_RX_RES_PHY_FLAGS_AGG

#define IWM_RX_RES_PHY_FLAGS_AGG (1 << 7)

Definition at line 3283 of file if_iwmreg.h.

◆ IWM_RX_RES_PHY_FLAGS_ANTENNA

#define IWM_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4)

Definition at line 3281 of file if_iwmreg.h.

◆ IWM_RX_RES_PHY_FLAGS_ANTENNA_POS

#define IWM_RX_RES_PHY_FLAGS_ANTENNA_POS 4

Definition at line 3282 of file if_iwmreg.h.

◆ IWM_RX_RES_PHY_FLAGS_BAND_24

#define IWM_RX_RES_PHY_FLAGS_BAND_24 (1 << 0)

Values to parse iwm_rx_phy_info phy_flags @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band @IWM_RX_RES_PHY_FLAGS_MOD_CCK: @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short @IWM_RX_RES_PHY_FLAGS_NARROW_BAND: @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame

Definition at line 3277 of file if_iwmreg.h.

◆ IWM_RX_RES_PHY_FLAGS_MOD_CCK

#define IWM_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1)

Definition at line 3278 of file if_iwmreg.h.

◆ IWM_RX_RES_PHY_FLAGS_NARROW_BAND

#define IWM_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3)

Definition at line 3280 of file if_iwmreg.h.

◆ IWM_RX_RES_PHY_FLAGS_OFDM_GF

#define IWM_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9)

Definition at line 3285 of file if_iwmreg.h.

◆ IWM_RX_RES_PHY_FLAGS_OFDM_HT

#define IWM_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8)

Definition at line 3284 of file if_iwmreg.h.

◆ IWM_RX_RES_PHY_FLAGS_OFDM_VHT

#define IWM_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10)

Definition at line 3286 of file if_iwmreg.h.

◆ IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE

#define IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2)

Definition at line 3279 of file if_iwmreg.h.

◆ IWM_RXF_DMA_IDLE

#define IWM_RXF_DMA_IDLE (1U << 31)

Definition at line 494 of file if_iwmreg.h.

◆ IWM_SB_CFG_BASE_OVERRIDE

#define IWM_SB_CFG_BASE_OVERRIDE 0xa20000

Definition at line 633 of file if_iwmreg.h.

◆ IWM_SB_CFG_OVERRIDE_ADDR

#define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78

Definition at line 631 of file if_iwmreg.h.

◆ IWM_SB_CFG_OVERRIDE_ENABLE

#define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000

Definition at line 632 of file if_iwmreg.h.

◆ IWM_SB_CPU_1_STATUS

#define IWM_SB_CPU_1_STATUS 0xa01e30

Definition at line 635 of file if_iwmreg.h.

◆ IWM_SB_CPU_2_STATUS

#define IWM_SB_CPU_2_STATUS 0Xa01e34

Definition at line 636 of file if_iwmreg.h.

◆ IWM_SB_MODIFY_CFG_FLAG

#define IWM_SB_MODIFY_CFG_FLAG 0xa03088

Definition at line 634 of file if_iwmreg.h.

◆ IWM_SCAN_ABORT_UMAC

#define IWM_SCAN_ABORT_UMAC 0xe

Definition at line 1994 of file if_iwmreg.h.

◆ IWM_SCAN_CFG_CMD

#define IWM_SCAN_CFG_CMD 0xc

Definition at line 1992 of file if_iwmreg.h.

◆ IWM_SCAN_CHANNEL_FLAG_CACHE_ADD

#define IWM_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2)

Definition at line 5482 of file if_iwmreg.h.

◆ IWM_SCAN_CHANNEL_FLAG_EBS

#define IWM_SCAN_CHANNEL_FLAG_EBS (1 << 0)

Definition at line 5480 of file if_iwmreg.h.

◆ IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE

#define IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1)

Definition at line 5481 of file if_iwmreg.h.

◆ IWM_SCAN_CHANNEL_NSSIDS

#define IWM_SCAN_CHANNEL_NSSIDS ( x ) (((1 << (x)) - 1) << 1)

Definition at line 5363 of file if_iwmreg.h.

◆ IWM_SCAN_CHANNEL_TYPE_ACTIVE

#define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0)

Definition at line 5362 of file if_iwmreg.h.

◆ IWM_SCAN_CHANNEL_UMAC_NSSIDS

#define IWM_SCAN_CHANNEL_UMAC_NSSIDS ( x ) ((1 << (x)) - 1)

Definition at line 5852 of file if_iwmreg.h.

◆ IWM_SCAN_CLIENT_ASSET_TRACKING

#define IWM_SCAN_CLIENT_ASSET_TRACKING (1 << 2)

Definition at line 5613 of file if_iwmreg.h.

◆ IWM_SCAN_CLIENT_NETDETECT

#define IWM_SCAN_CLIENT_NETDETECT (1 << 1)

Definition at line 5612 of file if_iwmreg.h.

◆ IWM_SCAN_CLIENT_SCHED_SCAN

#define IWM_SCAN_CLIENT_SCHED_SCAN (1 << 0)

Definition at line 5611 of file if_iwmreg.h.

◆ IWM_SCAN_COMPLETE_UMAC

#define IWM_SCAN_COMPLETE_UMAC 0xf

Definition at line 1995 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_ACTIVATE

#define IWM_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0)

Definition at line 5718 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS

#define IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3)

Definition at line 5721 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE

#define IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19)

Definition at line 5733 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED

#define IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17)

Definition at line 5731 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE

#define IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21)

Definition at line 5735 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_DEACTIVATE

#define IWM_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1)

Definition at line 5719 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS

#define IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2)

Definition at line 5720 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES

#define IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11)

Definition at line 5725 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID

#define IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10)

Definition at line 5724 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE

#define IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18)

Definition at line 5732 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS

#define IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13)

Definition at line 5727 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES

#define IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12)

Definition at line 5726 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED

#define IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16)

Definition at line 5730 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES

#define IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14)

Definition at line 5728 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR

#define IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15)

Definition at line 5729 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE

#define IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20)

Definition at line 5734 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS

#define IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9)

Definition at line 5723 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS

#define IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8)

Definition at line 5722 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_N_CHANNELS

#define IWM_SCAN_CONFIG_N_CHANNELS ( n ) ((n) << 26)

Definition at line 5738 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_RATE_11M

#define IWM_SCAN_CONFIG_RATE_11M (1 << 11)

Definition at line 5753 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_RATE_12M

#define IWM_SCAN_CONFIG_RATE_12M (1 << 2)

Definition at line 5743 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_RATE_18M

#define IWM_SCAN_CONFIG_RATE_18M (1 << 3)

Definition at line 5744 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_RATE_1M

#define IWM_SCAN_CONFIG_RATE_1M (1 << 8)

Definition at line 5750 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_RATE_24M

#define IWM_SCAN_CONFIG_RATE_24M (1 << 4)

Definition at line 5745 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_RATE_2M

#define IWM_SCAN_CONFIG_RATE_2M (1 << 9)

Definition at line 5751 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_RATE_36M

#define IWM_SCAN_CONFIG_RATE_36M (1 << 5)

Definition at line 5746 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_RATE_48M

#define IWM_SCAN_CONFIG_RATE_48M (1 << 6)

Definition at line 5747 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_RATE_54M

#define IWM_SCAN_CONFIG_RATE_54M (1 << 7)

Definition at line 5748 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_RATE_5M

#define IWM_SCAN_CONFIG_RATE_5M (1 << 10)

Definition at line 5752 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_RATE_6M

#define IWM_SCAN_CONFIG_RATE_6M (1 << 0)

Definition at line 5741 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_RATE_9M

#define IWM_SCAN_CONFIG_RATE_9M (1 << 1)

Definition at line 5742 of file if_iwmreg.h.

◆ IWM_SCAN_CONFIG_SUPPORTED_RATE

#define IWM_SCAN_CONFIG_SUPPORTED_RATE ( rate ) ((rate) << 16)

Definition at line 5756 of file if_iwmreg.h.

◆ IWM_SCAN_HB_LMAC_IDX

#define IWM_SCAN_HB_LMAC_IDX 1

Definition at line 5921 of file if_iwmreg.h.

◆ IWM_SCAN_ITERATION_COMPLETE

#define IWM_SCAN_ITERATION_COMPLETE 0xe7

Definition at line 2041 of file if_iwmreg.h.

◆ IWM_SCAN_ITERATION_COMPLETE_UMAC

#define IWM_SCAN_ITERATION_COMPLETE_UMAC 0xb5

Definition at line 1991 of file if_iwmreg.h.

◆ IWM_SCAN_LB_LMAC_IDX

#define IWM_SCAN_LB_LMAC_IDX 0

Definition at line 5920 of file if_iwmreg.h.

◆ IWM_SCAN_MAX_BLACKLIST_LEN

#define IWM_SCAN_MAX_BLACKLIST_LEN 64

Definition at line 5383 of file if_iwmreg.h.

◆ IWM_SCAN_MAX_PROFILES

#define IWM_SCAN_MAX_PROFILES 11

Definition at line 5385 of file if_iwmreg.h.

◆ IWM_SCAN_OFFLOAD_ABORT_CMD

#define IWM_SCAN_OFFLOAD_ABORT_CMD 0x52

Definition at line 2035 of file if_iwmreg.h.

◆ IWM_SCAN_OFFLOAD_COMPLETE

#define IWM_SCAN_OFFLOAD_COMPLETE 0x6d

Definition at line 2037 of file if_iwmreg.h.

◆ IWM_SCAN_OFFLOAD_CONFIG_CMD

#define IWM_SCAN_OFFLOAD_CONFIG_CMD 0x6f

Definition at line 2039 of file if_iwmreg.h.

◆ IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN

#define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5

Definition at line 6066 of file if_iwmreg.h.

◆ IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE

#define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512

Definition at line 5386 of file if_iwmreg.h.

◆ IWM_SCAN_OFFLOAD_REQUEST_CMD

#define IWM_SCAN_OFFLOAD_REQUEST_CMD 0x51

Definition at line 2034 of file if_iwmreg.h.

◆ IWM_SCAN_OFFLOAD_SELECT_2_4

#define IWM_SCAN_OFFLOAD_SELECT_2_4 0x4

Definition at line 5631 of file if_iwmreg.h.

◆ IWM_SCAN_OFFLOAD_SELECT_5_2

#define IWM_SCAN_OFFLOAD_SELECT_5_2 0x8

Definition at line 5632 of file if_iwmreg.h.

◆ IWM_SCAN_OFFLOAD_SELECT_ANY

#define IWM_SCAN_OFFLOAD_SELECT_ANY 0xc

Definition at line 5633 of file if_iwmreg.h.

◆ IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD

#define IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD 0x6e

Definition at line 2038 of file if_iwmreg.h.

◆ IWM_SCAN_PRIORITY_HIGH

#define IWM_SCAN_PRIORITY_HIGH 2

Definition at line 5523 of file if_iwmreg.h.

◆ IWM_SCAN_PRIORITY_LOW

#define IWM_SCAN_PRIORITY_LOW 0

Definition at line 5521 of file if_iwmreg.h.

◆ IWM_SCAN_PRIORITY_MEDIUM

#define IWM_SCAN_PRIORITY_MEDIUM 1

Definition at line 5522 of file if_iwmreg.h.

◆ IWM_SCAN_REQ_UMAC

#define IWM_SCAN_REQ_UMAC 0xd

Definition at line 1993 of file if_iwmreg.h.

◆ IWM_SCAN_REQ_UMAC_SIZE_V1

#define IWM_SCAN_REQ_UMAC_SIZE_V1 36

Definition at line 6034 of file if_iwmreg.h.

◆ IWM_SCAN_REQ_UMAC_SIZE_V6

#define IWM_SCAN_REQ_UMAC_SIZE_V6 44

Definition at line 6033 of file if_iwmreg.h.

◆ IWM_SCAN_REQ_UMAC_SIZE_V7

#define IWM_SCAN_REQ_UMAC_SIZE_V7 48

Definition at line 6032 of file if_iwmreg.h.

◆ IWM_SCAN_REQ_UMAC_SIZE_V8

#define IWM_SCAN_REQ_UMAC_SIZE_V8 sizeof(struct iwm_scan_req_umac)

Definition at line 6031 of file if_iwmreg.h.

◆ IWM_SCAN_SHORT_BLACKLIST_LEN

#define IWM_SCAN_SHORT_BLACKLIST_LEN 16

Definition at line 5384 of file if_iwmreg.h.

◆ IWM_SCD_ACTIVE

#define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)

Definition at line 1394 of file if_iwmreg.h.

◆ IWM_SCD_AGGR_SEL

#define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)

Definition at line 1397 of file if_iwmreg.h.

◆ IWM_SCD_AIT

#define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)

Definition at line 1392 of file if_iwmreg.h.

◆ IWM_SCD_BASE

#define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)

Definition at line 1388 of file if_iwmreg.h.

◆ IWM_SCD_CHAINEXT_EN

#define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)

Definition at line 1396 of file if_iwmreg.h.

◆ IWM_SCD_CONTEXT_MEM_LOWER_BOUND

#define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)

Definition at line 1368 of file if_iwmreg.h.

◆ IWM_SCD_CONTEXT_MEM_UPPER_BOUND

#define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)

Definition at line 1369 of file if_iwmreg.h.

◆ IWM_SCD_CONTEXT_QUEUE_OFFSET

#define IWM_SCD_CONTEXT_QUEUE_OFFSET ( x ) (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))

Definition at line 1379 of file if_iwmreg.h.

◆ IWM_SCD_DRAM_BASE_ADDR

#define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)

Definition at line 1391 of file if_iwmreg.h.

◆ IWM_SCD_EN_CTRL

#define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)

Definition at line 1400 of file if_iwmreg.h.

◆ IWM_SCD_FRAME_LIMIT

#define IWM_SCD_FRAME_LIMIT 64

Definition at line 1343 of file if_iwmreg.h.

◆ IWM_SCD_GP_CTRL

#define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)

Definition at line 1399 of file if_iwmreg.h.

◆ IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE

#define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18)

Definition at line 1365 of file if_iwmreg.h.

◆ IWM_SCD_GP_CTRL_ENABLE_31_QUEUES

#define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0)

Definition at line 1364 of file if_iwmreg.h.

◆ IWM_SCD_INTERRUPT_MASK

#define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)

Definition at line 1398 of file if_iwmreg.h.

◆ IWM_SCD_MEM_LOWER_BOUND

#define IWM_SCD_MEM_LOWER_BOUND (0x0000)

Tx Scheduler

The Tx Scheduler selects the next frame to be transmitted, choosing TFDs (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in host DRAM. It steers each frame's Tx command (which contains the frame data) into one of up to 7 prioritized Tx DMA FIFO channels within the device. A queue maps to only one (selectable by driver) Tx DMA channel, but one DMA channel may take input from several queues.

Tx DMA FIFOs have dedicated purposes.

For 5000 series and up, they are used differently (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):

0 – EDCA BK (background) frames, lowest priority 1 – EDCA BE (best effort) frames, normal priority 2 – EDCA VI (video) frames, higher priority 3 – EDCA VO (voice) and management frames, highest priority 4 – unused 5 – unused 6 – unused 7 – Commands

Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. In addition, driver can map the remaining queues to Tx DMA/FIFO channels 0-3 to support 11n aggregation via EDCA DMA channels.

The driver sets up each queue to work in one of two modes:

1) Scheduler-Ack, in which the scheduler automatically supports a block-ack (BA) window of up to 64 TFDs. In this mode, each queue contains TFDs for a unique combination of Recipient Address (RA) and Traffic Identifier (TID), that is, traffic of a given Quality-Of-Service (QOS) priority, destined for a single station.

In scheduler-ack mode, the scheduler keeps track of the Tx status of each frame within the BA window, including whether it's been transmitted, and whether it's been acknowledged by the receiving station. The device automatically processes block-acks received from the receiving STA, and reschedules un-acked frames to be retransmitted (successful Tx completion may end up being out-of-order).

The driver must maintain the queue's Byte Count table in host DRAM for this mode. This mode does not support fragmentation.

2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. The device may automatically retry Tx, but will retry only one frame at a time, until receiving ACK from receiving station, or reaching retry limit and giving up.

The command queue (#4/#9) must use this mode! This mode does not require use of the Byte Count table in host DRAM.

Driver controls scheduler operation via 3 means: 1) Scheduler registers 2) Shared scheduler data base in internal SRAM 3) Shared data in host DRAM

Initialization:

When loading, driver should allocate memory for: 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory (1024 bytes for each queue).

After receiving "Alive" response from uCode, driver must initialize the scheduler (especially for queue #4/#9, the command queue, otherwise the driver can't issue commands!):

Definition at line 1335 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_CFG

#define IWM_SCD_QUEUE_CFG 0x1d

Definition at line 2008 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK

#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)

Definition at line 1357 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS

#define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)

Definition at line 1356 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK

#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)

Definition at line 1359 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS

#define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)

Definition at line 1358 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK

#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)

Definition at line 1363 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS

#define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)

Definition at line 1362 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK

#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)

Definition at line 1361 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS

#define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)

Definition at line 1360 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK

#define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)

Definition at line 1347 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_STTS_REG_MSK

#define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)

Definition at line 1354 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE

#define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)

Definition at line 1351 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN

#define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)

Definition at line 1353 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_STTS_REG_POS_TXF

#define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)

Definition at line 1350 of file if_iwmreg.h.

◆ IWM_SCD_QUEUE_STTS_REG_POS_WSL

#define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)

Definition at line 1352 of file if_iwmreg.h.

◆ IWM_SCD_QUEUECHAIN_SEL

#define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)

Definition at line 1395 of file if_iwmreg.h.

◆ IWM_SCD_SRAM_BASE_ADDR

#define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)

Definition at line 1390 of file if_iwmreg.h.

◆ IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND

#define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)

Definition at line 1376 of file if_iwmreg.h.

◆ IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND

#define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)

Definition at line 1377 of file if_iwmreg.h.

◆ IWM_SCD_TRANS_TBL_OFFSET_QUEUE

#define IWM_SCD_TRANS_TBL_OFFSET_QUEUE ( x ) ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)

Definition at line 1385 of file if_iwmreg.h.

◆ IWM_SCD_TX_STTS_MEM_LOWER_BOUND

#define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)

Definition at line 1372 of file if_iwmreg.h.

◆ IWM_SCD_TX_STTS_MEM_UPPER_BOUND

#define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)

Definition at line 1373 of file if_iwmreg.h.

◆ IWM_SCD_TX_STTS_QUEUE_OFFSET

#define IWM_SCD_TX_STTS_QUEUE_OFFSET ( x ) (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))

Definition at line 1382 of file if_iwmreg.h.

◆ IWM_SCD_TXFACT

#define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)

Definition at line 1393 of file if_iwmreg.h.

◆ IWM_SCD_TXFIFO_POS_RA

#define IWM_SCD_TXFIFO_POS_RA (4)

Definition at line 1346 of file if_iwmreg.h.

◆ IWM_SCD_TXFIFO_POS_TID

#define IWM_SCD_TXFIFO_POS_TID (0)

Definition at line 1345 of file if_iwmreg.h.

◆ IWM_SCD_WIN_SIZE

#define IWM_SCD_WIN_SIZE 64

Max Tx window size is the max number of contiguous TFDs that the scheduler can keep track of at one time when creating block-ack chains of frames. Note that "64" matches the number of ack bits in a block-ack packet.

Definition at line 1342 of file if_iwmreg.h.

◆ IWM_SCHED_SCAN_WATCHDOG

#define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)

Definition at line 5389 of file if_iwmreg.h.

◆ IWM_SET_CALIB_DEFAULT_CMD

#define IWM_SET_CALIB_DEFAULT_CMD 0x8e

Definition at line 2059 of file if_iwmreg.h.

◆ IWM_SETBITS

#define IWM_SETBITS	(	sc,
		reg,
		mask
	)	IWM_WRITE(sc, reg, IWM_READ(sc, reg) \| (mask))

Definition at line 6963 of file if_iwmreg.h.

◆ IWM_SF_AGG_UNICAST_AGING_TIMER

#define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */

Definition at line 3774 of file if_iwmreg.h.

◆ IWM_SF_AGG_UNICAST_AGING_TIMER_DEF

#define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */

Definition at line 3762 of file if_iwmreg.h.

◆ IWM_SF_AGG_UNICAST_IDLE_TIMER

#define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */

Definition at line 3773 of file if_iwmreg.h.

◆ IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF

#define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */

Definition at line 3761 of file if_iwmreg.h.

◆ IWM_SF_BA_AGING_TIMER

#define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */

Definition at line 3778 of file if_iwmreg.h.

◆ IWM_SF_BA_AGING_TIMER_DEF

#define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */

Definition at line 3766 of file if_iwmreg.h.

◆ IWM_SF_BA_IDLE_TIMER

#define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */

Definition at line 3777 of file if_iwmreg.h.

◆ IWM_SF_BA_IDLE_TIMER_DEF

#define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */

Definition at line 3765 of file if_iwmreg.h.

◆ IWM_SF_CFG_DUMMY_NOTIF_OFF

#define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)

Definition at line 3784 of file if_iwmreg.h.

◆ IWM_SF_LONG_DELAY_AGING_TIMER

#define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */

Definition at line 3782 of file if_iwmreg.h.

◆ IWM_SF_MCAST_AGING_TIMER

#define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */

Definition at line 3776 of file if_iwmreg.h.

◆ IWM_SF_MCAST_AGING_TIMER_DEF

#define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */

Definition at line 3764 of file if_iwmreg.h.

◆ IWM_SF_MCAST_IDLE_TIMER

#define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */

Definition at line 3775 of file if_iwmreg.h.

◆ IWM_SF_MCAST_IDLE_TIMER_DEF

#define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */

Definition at line 3763 of file if_iwmreg.h.

◆ IWM_SF_NUM_TIMEOUT_TYPES

#define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */

Definition at line 3749 of file if_iwmreg.h.

◆ IWM_SF_SINGLE_UNICAST_AGING_TIMER

#define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */

Definition at line 3772 of file if_iwmreg.h.

◆ IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF

#define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */

Definition at line 3760 of file if_iwmreg.h.

◆ IWM_SF_SINGLE_UNICAST_IDLE_TIMER

#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */

Definition at line 3771 of file if_iwmreg.h.

◆ IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF

#define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */

Definition at line 3759 of file if_iwmreg.h.

◆ IWM_SF_TRANSIENT_STATES_NUMBER

#define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */

Definition at line 3748 of file if_iwmreg.h.

◆ IWM_SF_TX_RE_AGING_TIMER

#define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */

Definition at line 3780 of file if_iwmreg.h.

◆ IWM_SF_TX_RE_AGING_TIMER_DEF

#define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */

Definition at line 3768 of file if_iwmreg.h.

◆ IWM_SF_TX_RE_IDLE_TIMER

#define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */

Definition at line 3779 of file if_iwmreg.h.

◆ IWM_SF_TX_RE_IDLE_TIMER_DEF

#define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */

Definition at line 3767 of file if_iwmreg.h.

◆ IWM_SF_W_MARK_LEGACY

#define IWM_SF_W_MARK_LEGACY 4096

Definition at line 3755 of file if_iwmreg.h.

◆ IWM_SF_W_MARK_MIMO2

#define IWM_SF_W_MARK_MIMO2 8192

Definition at line 3753 of file if_iwmreg.h.

◆ IWM_SF_W_MARK_MIMO3

#define IWM_SF_W_MARK_MIMO3 6144

Definition at line 3754 of file if_iwmreg.h.

◆ IWM_SF_W_MARK_SCAN

#define IWM_SF_W_MARK_SCAN 4096

Definition at line 3756 of file if_iwmreg.h.

◆ IWM_SF_W_MARK_SISO

#define IWM_SF_W_MARK_SISO 4096

Definition at line 3752 of file if_iwmreg.h.

◆ IWM_SHARED_MEM_CFG_CMD

#define IWM_SHARED_MEM_CFG_CMD 0x00

Definition at line 2150 of file if_iwmreg.h.

◆ IWM_SHR_MISC_WFM_DTS_EN

#define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)

Definition at line 1256 of file if_iwmreg.h.

◆ IWM_SKU

#define IWM_SKU 2

Definition at line 2318 of file if_iwmreg.h.

◆ IWM_SKU_8000

#define IWM_SKU_8000 2

Definition at line 2336 of file if_iwmreg.h.

◆ IWM_SOC_CONFIG_CMD_FLAGS_DISCRETE

#define IWM_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0)

Definition at line 2568 of file if_iwmreg.h.

◆ IWM_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY

#define IWM_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY (1 << 1)

Definition at line 2569 of file if_iwmreg.h.

◆ IWM_SOC_CONFIGURATION_CMD

#define IWM_SOC_CONFIGURATION_CMD 0x01

Definition at line 2151 of file if_iwmreg.h.

◆ IWM_SOC_FLAGS_LTR_APPLY_DELAY_1820

#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_1820 3

Definition at line 2575 of file if_iwmreg.h.

◆ IWM_SOC_FLAGS_LTR_APPLY_DELAY_200

#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_200 1

Definition at line 2573 of file if_iwmreg.h.

◆ IWM_SOC_FLAGS_LTR_APPLY_DELAY_2500

#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_2500 2

Definition at line 2574 of file if_iwmreg.h.

◆ IWM_SOC_FLAGS_LTR_APPLY_DELAY_MASK

#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc

Definition at line 2571 of file if_iwmreg.h.

◆ IWM_SOC_FLAGS_LTR_APPLY_DELAY_NONE

#define IWM_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0

Definition at line 2572 of file if_iwmreg.h.

◆ IWM_SRAM_DMA_IDLE

#define IWM_SRAM_DMA_IDLE (1 << 30)

Definition at line 493 of file if_iwmreg.h.

◆ IWM_STA_AUX_ACTIVITY

#define IWM_STA_AUX_ACTIVITY 4

Definition at line 6483 of file if_iwmreg.h.

◆ IWM_STA_COLOR_MSK

#define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)

Definition at line 6294 of file if_iwmreg.h.

◆ IWM_STA_COLOR_POS

#define IWM_STA_COLOR_POS (4)

Definition at line 6293 of file if_iwmreg.h.

◆ IWM_STA_COLOR_SEED

#define IWM_STA_COLOR_SEED (0x7)

Definition at line 6292 of file if_iwmreg.h.

◆ IWM_STA_FLG_AGG_MPDU_DENS_16US

#define IWM_STA_FLG_AGG_MPDU_DENS_16US (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)

Definition at line 6204 of file if_iwmreg.h.

◆ IWM_STA_FLG_AGG_MPDU_DENS_2US

#define IWM_STA_FLG_AGG_MPDU_DENS_2US (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)

Definition at line 6201 of file if_iwmreg.h.

◆ IWM_STA_FLG_AGG_MPDU_DENS_4US

#define IWM_STA_FLG_AGG_MPDU_DENS_4US (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)

Definition at line 6202 of file if_iwmreg.h.

◆ IWM_STA_FLG_AGG_MPDU_DENS_8US

#define IWM_STA_FLG_AGG_MPDU_DENS_8US (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)

Definition at line 6203 of file if_iwmreg.h.

◆ IWM_STA_FLG_AGG_MPDU_DENS_MSK

#define IWM_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT)

Definition at line 6205 of file if_iwmreg.h.

◆ IWM_STA_FLG_AGG_MPDU_DENS_SHIFT

#define IWM_STA_FLG_AGG_MPDU_DENS_SHIFT 23

Definition at line 6200 of file if_iwmreg.h.

◆ IWM_STA_FLG_CLASS_ASSOC

#define IWM_STA_FLG_CLASS_ASSOC (1 << 15)

Definition at line 6186 of file if_iwmreg.h.

◆ IWM_STA_FLG_CLASS_AUTH

#define IWM_STA_FLG_CLASS_AUTH (1 << 14)

Definition at line 6185 of file if_iwmreg.h.

◆ IWM_STA_FLG_DISABLE_TX

#define IWM_STA_FLG_DISABLE_TX (1 << 4)

Definition at line 6180 of file if_iwmreg.h.

◆ IWM_STA_FLG_DRAIN_FLOW

#define IWM_STA_FLG_DRAIN_FLOW (1 << 12)

Definition at line 6183 of file if_iwmreg.h.

◆ IWM_STA_FLG_FAT_EN_160MHZ

#define IWM_STA_FLG_FAT_EN_160MHZ (3 << 26)

Definition at line 6210 of file if_iwmreg.h.

◆ IWM_STA_FLG_FAT_EN_20MHZ

#define IWM_STA_FLG_FAT_EN_20MHZ (0 << 26)

Definition at line 6207 of file if_iwmreg.h.

◆ IWM_STA_FLG_FAT_EN_40MHZ

#define IWM_STA_FLG_FAT_EN_40MHZ (1 << 26)

Definition at line 6208 of file if_iwmreg.h.

◆ IWM_STA_FLG_FAT_EN_80MHZ

#define IWM_STA_FLG_FAT_EN_80MHZ (2 << 26)

Definition at line 6209 of file if_iwmreg.h.

◆ IWM_STA_FLG_FAT_EN_MSK

#define IWM_STA_FLG_FAT_EN_MSK (3 << 26)

Definition at line 6211 of file if_iwmreg.h.

◆ IWM_STA_FLG_MAX_AGG_SIZE_1024K

#define IWM_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

Definition at line 6197 of file if_iwmreg.h.

◆ IWM_STA_FLG_MAX_AGG_SIZE_128K

#define IWM_STA_FLG_MAX_AGG_SIZE_128K (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

Definition at line 6194 of file if_iwmreg.h.

◆ IWM_STA_FLG_MAX_AGG_SIZE_16K

#define IWM_STA_FLG_MAX_AGG_SIZE_16K (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

Definition at line 6191 of file if_iwmreg.h.

◆ IWM_STA_FLG_MAX_AGG_SIZE_256K

#define IWM_STA_FLG_MAX_AGG_SIZE_256K (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

Definition at line 6195 of file if_iwmreg.h.

◆ IWM_STA_FLG_MAX_AGG_SIZE_32K

#define IWM_STA_FLG_MAX_AGG_SIZE_32K (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

Definition at line 6192 of file if_iwmreg.h.

◆ IWM_STA_FLG_MAX_AGG_SIZE_512K

#define IWM_STA_FLG_MAX_AGG_SIZE_512K (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

Definition at line 6196 of file if_iwmreg.h.

◆ IWM_STA_FLG_MAX_AGG_SIZE_64K

#define IWM_STA_FLG_MAX_AGG_SIZE_64K (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

Definition at line 6193 of file if_iwmreg.h.

◆ IWM_STA_FLG_MAX_AGG_SIZE_8K

#define IWM_STA_FLG_MAX_AGG_SIZE_8K (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

Definition at line 6190 of file if_iwmreg.h.

◆ IWM_STA_FLG_MAX_AGG_SIZE_MSK

#define IWM_STA_FLG_MAX_AGG_SIZE_MSK (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)

Definition at line 6198 of file if_iwmreg.h.

◆ IWM_STA_FLG_MAX_AGG_SIZE_SHIFT

#define IWM_STA_FLG_MAX_AGG_SIZE_SHIFT 19

Definition at line 6189 of file if_iwmreg.h.

◆ IWM_STA_FLG_MIMO_EN_MIMO2

#define IWM_STA_FLG_MIMO_EN_MIMO2 (1 << 28)

Definition at line 6214 of file if_iwmreg.h.

◆ IWM_STA_FLG_MIMO_EN_MIMO3

#define IWM_STA_FLG_MIMO_EN_MIMO3 (2 << 28)

Definition at line 6215 of file if_iwmreg.h.

◆ IWM_STA_FLG_MIMO_EN_MSK

#define IWM_STA_FLG_MIMO_EN_MSK (3 << 28)

Definition at line 6216 of file if_iwmreg.h.

◆ IWM_STA_FLG_MIMO_EN_SISO

#define IWM_STA_FLG_MIMO_EN_SISO (0 << 28)

Definition at line 6213 of file if_iwmreg.h.

◆ IWM_STA_FLG_PAN

#define IWM_STA_FLG_PAN (1 << 13)

Definition at line 6184 of file if_iwmreg.h.

◆ IWM_STA_FLG_PS

#define IWM_STA_FLG_PS (1 << 8)

Definition at line 6182 of file if_iwmreg.h.

◆ IWM_STA_FLG_REDUCED_TX_PWR_CTRL

#define IWM_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3)

flags for the ADD_STA host command @IWM_STA_FLG_REDUCED_TX_PWR_CTRL: @IWM_STA_FLG_REDUCED_TX_PWR_DATA: @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled @IWM_STA_FLG_PS: set if STA is in Power Save @IWM_STA_FLG_INVALID: set if STA is invalid @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs @IWM_STA_FLG_DRAIN_FLOW: drain flow @IWM_STA_FLG_PAN: STA is for PAN interface @IWM_STA_FLG_CLASS_AUTH: @IWM_STA_FLG_CLASS_ASSOC: @IWM_STA_FLG_CLASS_MIMO_PROT: @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is initialised by driver and can be updated by fw upon reception of action frames that can change the channel width. When cleared the fw will send all the frames in 20MHz even when FAT channel is requested. @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the driver and can be updated by fw upon reception of action frames. @IWM_STA_FLG_MFP_EN: Management Frame Protection

Definition at line 6177 of file if_iwmreg.h.

◆ IWM_STA_FLG_REDUCED_TX_PWR_DATA

#define IWM_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6)

Definition at line 6178 of file if_iwmreg.h.

◆ IWM_STA_FLG_RTS_MIMO_PROT

#define IWM_STA_FLG_RTS_MIMO_PROT (1 << 17)

Definition at line 6187 of file if_iwmreg.h.

◆ IWM_STA_GENERAL_PURPOSE

#define IWM_STA_GENERAL_PURPOSE 1

Definition at line 6480 of file if_iwmreg.h.

◆ IWM_STA_ID_MSK

#define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)

Definition at line 6290 of file if_iwmreg.h.

◆ IWM_STA_ID_N_COLOR_GET_COLOR

#define IWM_STA_ID_N_COLOR_GET_COLOR ( id_n_color ) (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)

Definition at line 6296 of file if_iwmreg.h.

◆ IWM_STA_ID_N_COLOR_GET_ID

#define IWM_STA_ID_N_COLOR_GET_ID ( id_n_color ) (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)

Definition at line 6298 of file if_iwmreg.h.

◆ IWM_STA_ID_POS

#define IWM_STA_ID_POS (0)

Definition at line 6289 of file if_iwmreg.h.

◆ IWM_STA_ID_SEED

#define IWM_STA_ID_SEED (0x0f)

Definition at line 6288 of file if_iwmreg.h.

◆ IWM_STA_KEY_FLG_CCM

#define IWM_STA_KEY_FLG_CCM (2 << 0)

Definition at line 6238 of file if_iwmreg.h.

◆ IWM_STA_KEY_FLG_CMAC

#define IWM_STA_KEY_FLG_CMAC (6 << 0)

Definition at line 6241 of file if_iwmreg.h.

◆ IWM_STA_KEY_FLG_EN_MSK

#define IWM_STA_KEY_FLG_EN_MSK (7 << 0)

Definition at line 6243 of file if_iwmreg.h.

◆ IWM_STA_KEY_FLG_ENC_UNKNOWN

#define IWM_STA_KEY_FLG_ENC_UNKNOWN (7 << 0)

Definition at line 6242 of file if_iwmreg.h.

◆ IWM_STA_KEY_FLG_EXT

#define IWM_STA_KEY_FLG_EXT (4 << 0)

Definition at line 6240 of file if_iwmreg.h.

◆ IWM_STA_KEY_FLG_KEYID_MSK

#define IWM_STA_KEY_FLG_KEYID_MSK (3 << IWM_STA_KEY_FLG_KEYID_POS)

Definition at line 6246 of file if_iwmreg.h.

◆ IWM_STA_KEY_FLG_KEYID_POS

#define IWM_STA_KEY_FLG_KEYID_POS 8

Definition at line 6245 of file if_iwmreg.h.

◆ IWM_STA_KEY_FLG_NO_ENC

#define IWM_STA_KEY_FLG_NO_ENC (0 << 0)

key flags for the ADD_STA host command @IWM_STA_KEY_FLG_NO_ENC: no encryption @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support) @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from station info array (1 - n 1X mode) @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key @IWM_STA_KEY_NOT_VALID: key is invalid @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key @IWM_STA_KEY_MULTICAST: set for multicast key @IWM_STA_KEY_MFP: key is used for Management Frame Protection

Definition at line 6236 of file if_iwmreg.h.

◆ IWM_STA_KEY_FLG_TKIP

#define IWM_STA_KEY_FLG_TKIP (3 << 0)

Definition at line 6239 of file if_iwmreg.h.

◆ IWM_STA_KEY_FLG_WEP

#define IWM_STA_KEY_FLG_WEP (1 << 0)

Definition at line 6237 of file if_iwmreg.h.

◆ IWM_STA_KEY_FLG_WEP_13BYTES

#define IWM_STA_KEY_FLG_WEP_13BYTES (1 << 12)

Definition at line 6248 of file if_iwmreg.h.

◆ IWM_STA_KEY_FLG_WEP_KEY_MAP

#define IWM_STA_KEY_FLG_WEP_KEY_MAP (1 << 3)

Definition at line 6244 of file if_iwmreg.h.

◆ IWM_STA_KEY_IDX_INVALID

#define IWM_STA_KEY_IDX_INVALID (0xff)

Definition at line 6302 of file if_iwmreg.h.

◆ IWM_STA_KEY_LEN_WEP104

#define IWM_STA_KEY_LEN_WEP104 (13)

Definition at line 6306 of file if_iwmreg.h.

◆ IWM_STA_KEY_LEN_WEP40

#define IWM_STA_KEY_LEN_WEP40 (5)

Definition at line 6305 of file if_iwmreg.h.

◆ IWM_STA_KEY_MAX_DATA_KEY_NUM

#define IWM_STA_KEY_MAX_DATA_KEY_NUM (4)

Definition at line 6303 of file if_iwmreg.h.

◆ IWM_STA_KEY_MAX_NUM

#define IWM_STA_KEY_MAX_NUM (16)

Definition at line 6301 of file if_iwmreg.h.

◆ IWM_STA_KEY_MFP

#define IWM_STA_KEY_MFP (1 << 15)

Definition at line 6250 of file if_iwmreg.h.

◆ IWM_STA_KEY_MULTICAST

#define IWM_STA_KEY_MULTICAST (1 << 14)

Definition at line 6249 of file if_iwmreg.h.

◆ IWM_STA_KEY_NOT_VALID

#define IWM_STA_KEY_NOT_VALID (1 << 11)

Definition at line 6247 of file if_iwmreg.h.

◆ IWM_STA_LINK

#define IWM_STA_LINK 0

FW station types ( REPLY_ADD_STA = 0x18 ) @IWM_STA_LINK: Link station - normal RX and TX traffic. @IWM_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons and probe responses. @IWM_STA_MULTICAST: multicast traffic, @IWM_STA_TDLS_LINK: TDLS link station @IWM_STA_AUX_ACTIVITY: auxilary station (scan, ROC and so on).

Definition at line 6479 of file if_iwmreg.h.

◆ IWM_STA_MODE_MODIFY

#define IWM_STA_MODE_MODIFY 1

Definition at line 6272 of file if_iwmreg.h.

◆ IWM_STA_MODIFY_ADD_BA_TID

#define IWM_STA_MODIFY_ADD_BA_TID (1 << 3)

Definition at line 6266 of file if_iwmreg.h.

◆ IWM_STA_MODIFY_PROT_TH

#define IWM_STA_MODIFY_PROT_TH (1 << 6)

Definition at line 6269 of file if_iwmreg.h.

◆ IWM_STA_MODIFY_QUEUE_REMOVAL

#define IWM_STA_MODIFY_QUEUE_REMOVAL (1 << 0)

indicate to the fw what flag are being changed @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies tid_disable_tx @IWM_STA_MODIFY_TX_RATE: unused @IWM_STA_MODIFY_ADD_BA_TID: this command modifies add_immediate_ba_tid @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies remove_immediate_ba_tid @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies sleep_tx_count @IWM_STA_MODIFY_PROT_TH: @IWM_STA_MODIFY_QUEUES: modify the queues used by this station

Definition at line 6263 of file if_iwmreg.h.

◆ IWM_STA_MODIFY_QUEUES

#define IWM_STA_MODIFY_QUEUES (1 << 7)

Definition at line 6270 of file if_iwmreg.h.

◆ IWM_STA_MODIFY_REMOVE_BA_TID

#define IWM_STA_MODIFY_REMOVE_BA_TID (1 << 4)

Definition at line 6267 of file if_iwmreg.h.

◆ IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT

#define IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5)

Definition at line 6268 of file if_iwmreg.h.

◆ IWM_STA_MODIFY_TID_DISABLE_TX

#define IWM_STA_MODIFY_TID_DISABLE_TX (1 << 1)

Definition at line 6264 of file if_iwmreg.h.

◆ IWM_STA_MODIFY_TX_RATE

#define IWM_STA_MODIFY_TX_RATE (1 << 2)

Definition at line 6265 of file if_iwmreg.h.

◆ IWM_STA_MULTICAST

#define IWM_STA_MULTICAST 2

Definition at line 6481 of file if_iwmreg.h.

◆ IWM_STA_SLEEP_STATE_AWAKE

#define IWM_STA_SLEEP_STATE_AWAKE 0

type of sleep of the station @IWM_STA_SLEEP_STATE_AWAKE: @IWM_STA_SLEEP_STATE_PS_POLL: @IWM_STA_SLEEP_STATE_UAPSD: @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on (last) released frame

Definition at line 6282 of file if_iwmreg.h.

◆ IWM_STA_SLEEP_STATE_MOREDATA

#define IWM_STA_SLEEP_STATE_MOREDATA (1 << 2)

Definition at line 6285 of file if_iwmreg.h.

◆ IWM_STA_SLEEP_STATE_PS_POLL

#define IWM_STA_SLEEP_STATE_PS_POLL (1 << 0)

Definition at line 6283 of file if_iwmreg.h.

◆ IWM_STA_SLEEP_STATE_UAPSD

#define IWM_STA_SLEEP_STATE_UAPSD (1 << 1)

Definition at line 6284 of file if_iwmreg.h.

◆ IWM_STA_TDLS_LINK

#define IWM_STA_TDLS_LINK 3

Definition at line 6482 of file if_iwmreg.h.

◆ IWM_STATION_COUNT

#define IWM_STATION_COUNT 16

Definition at line 1977 of file if_iwmreg.h.

◆ IWM_STATISTICS_NOTIFICATION

#define IWM_STATISTICS_NOTIFICATION 0x9d

Definition at line 2065 of file if_iwmreg.h.

◆ IWM_SW_CARD_DISABLED

#define IWM_SW_CARD_DISABLED 0x02

Definition at line 3432 of file if_iwmreg.h.

◆ IWM_SYSTEM_GROUP

#define IWM_SYSTEM_GROUP 0x2

Definition at line 2142 of file if_iwmreg.h.

◆ IWM_T2_V2_START_IMMEDIATELY

#define IWM_T2_V2_START_IMMEDIATELY (1 << 11)

Definition at line 2863 of file if_iwmreg.h.

◆ IWM_TE_BSS_EAP_DHCP_PROT

#define IWM_TE_BSS_EAP_DHCP_PROT 2

Definition at line 2675 of file if_iwmreg.h.

◆ IWM_TE_BSS_QUIET_PERIOD

#define IWM_TE_BSS_QUIET_PERIOD 3

Definition at line 2676 of file if_iwmreg.h.

◆ IWM_TE_BSS_STA_AGGRESSIVE_ASSOC

#define IWM_TE_BSS_STA_AGGRESSIVE_ASSOC 0

Definition at line 2673 of file if_iwmreg.h.

◆ IWM_TE_BSS_STA_ASSOC

#define IWM_TE_BSS_STA_ASSOC 1

Definition at line 2674 of file if_iwmreg.h.

◆ IWM_TE_MAX

#define IWM_TE_MAX 15

Definition at line 2697 of file if_iwmreg.h.

◆ IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC

#define IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8

Definition at line 2685 of file if_iwmreg.h.

◆ IWM_TE_P2P_CLIENT_ASSOC

#define IWM_TE_P2P_CLIENT_ASSOC 9

Definition at line 2686 of file if_iwmreg.h.

◆ IWM_TE_P2P_CLIENT_QUIET_PERIOD

#define IWM_TE_P2P_CLIENT_QUIET_PERIOD 10

Definition at line 2687 of file if_iwmreg.h.

◆ IWM_TE_P2P_DEVICE_ACTION_SCAN

#define IWM_TE_P2P_DEVICE_ACTION_SCAN 6

Definition at line 2681 of file if_iwmreg.h.

◆ IWM_TE_P2P_DEVICE_DISCOVERABLE

#define IWM_TE_P2P_DEVICE_DISCOVERABLE 4

Definition at line 2679 of file if_iwmreg.h.

◆ IWM_TE_P2P_DEVICE_FULL_SCAN

#define IWM_TE_P2P_DEVICE_FULL_SCAN 7

Definition at line 2682 of file if_iwmreg.h.

◆ IWM_TE_P2P_DEVICE_LISTEN

#define IWM_TE_P2P_DEVICE_LISTEN 5

Definition at line 2680 of file if_iwmreg.h.

◆ IWM_TE_P2P_GO_ASSOC_PROT

#define IWM_TE_P2P_GO_ASSOC_PROT 11

Definition at line 2690 of file if_iwmreg.h.

◆ IWM_TE_P2P_GO_CT_WINDOW

#define IWM_TE_P2P_GO_CT_WINDOW 13

Definition at line 2692 of file if_iwmreg.h.

◆ IWM_TE_P2P_GO_REPETITIVE_NOA

#define IWM_TE_P2P_GO_REPETITIVE_NOA 12

Definition at line 2691 of file if_iwmreg.h.

◆ IWM_TE_V1_DEP_OTHER

#define IWM_TE_V1_DEP_OTHER (1 << 0)

Definition at line 2731 of file if_iwmreg.h.

◆ IWM_TE_V1_DEP_TSF

#define IWM_TE_V1_DEP_TSF (1 << 1)

Definition at line 2732 of file if_iwmreg.h.

◆ IWM_TE_V1_EVENT_SOCIOPATHIC

#define IWM_TE_V1_EVENT_SOCIOPATHIC (1 << 2)

Definition at line 2733 of file if_iwmreg.h.

◆ IWM_TE_V1_FRAG_DUAL

#define IWM_TE_V1_FRAG_DUAL 2

Definition at line 2719 of file if_iwmreg.h.

◆ IWM_TE_V1_FRAG_ENDLESS

#define IWM_TE_V1_FRAG_ENDLESS 0xffffffff

Definition at line 2720 of file if_iwmreg.h.

◆ IWM_TE_V1_FRAG_MAX_MSK

#define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff

Definition at line 2723 of file if_iwmreg.h.

◆ IWM_TE_V1_FRAG_NONE

#define IWM_TE_V1_FRAG_NONE 0

Definition at line 2717 of file if_iwmreg.h.

◆ IWM_TE_V1_FRAG_SINGLE

#define IWM_TE_V1_FRAG_SINGLE 1

Definition at line 2718 of file if_iwmreg.h.

◆ IWM_TE_V1_INDEPENDENT

#define IWM_TE_V1_INDEPENDENT 0

Definition at line 2730 of file if_iwmreg.h.

◆ IWM_TE_V1_NOTIF_HOST_EVENT_END

#define IWM_TE_V1_NOTIF_HOST_EVENT_END (1 << 1)

Definition at line 2755 of file if_iwmreg.h.

◆ IWM_TE_V1_NOTIF_HOST_EVENT_START

#define IWM_TE_V1_NOTIF_HOST_EVENT_START (1 << 0)

Definition at line 2754 of file if_iwmreg.h.

◆ IWM_TE_V1_NOTIF_HOST_FRAG_END

#define IWM_TE_V1_NOTIF_HOST_FRAG_END (1 << 5)

Definition at line 2759 of file if_iwmreg.h.

◆ IWM_TE_V1_NOTIF_HOST_FRAG_START

#define IWM_TE_V1_NOTIF_HOST_FRAG_START (1 << 4)

Definition at line 2758 of file if_iwmreg.h.

◆ IWM_TE_V1_NOTIF_INTERNAL_EVENT_END

#define IWM_TE_V1_NOTIF_INTERNAL_EVENT_END (1 << 3)

Definition at line 2757 of file if_iwmreg.h.

◆ IWM_TE_V1_NOTIF_INTERNAL_EVENT_START

#define IWM_TE_V1_NOTIF_INTERNAL_EVENT_START (1 << 2)

Definition at line 2756 of file if_iwmreg.h.

◆ IWM_TE_V1_NOTIF_INTERNAL_FRAG_END

#define IWM_TE_V1_NOTIF_INTERNAL_FRAG_END (1 << 7)

Definition at line 2761 of file if_iwmreg.h.

◆ IWM_TE_V1_NOTIF_INTERNAL_FRAG_START

#define IWM_TE_V1_NOTIF_INTERNAL_FRAG_START (1 << 6)

Definition at line 2760 of file if_iwmreg.h.

◆ IWM_TE_V1_NOTIF_NONE

#define IWM_TE_V1_NOTIF_NONE 0

Definition at line 2753 of file if_iwmreg.h.

◆ IWM_TE_V1_REPEAT_ENDLESS

#define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff

Definition at line 2725 of file if_iwmreg.h.

◆ IWM_TE_V1_REPEAT_MAX_MSK_V1

#define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff

Definition at line 2727 of file if_iwmreg.h.

◆ IWM_TE_V2_ABSENCE

#define IWM_TE_V2_ABSENCE (1 << IWM_TE_V2_ABSENCE_POS)

Definition at line 2873 of file if_iwmreg.h.

◆ IWM_TE_V2_ABSENCE_POS

#define IWM_TE_V2_ABSENCE_POS 15

Definition at line 2829 of file if_iwmreg.h.

◆ IWM_TE_V2_DEFAULT_POLICY

#define IWM_TE_V2_DEFAULT_POLICY 0x0

Definition at line 2851 of file if_iwmreg.h.

◆ IWM_TE_V2_DEP_OTHER

#define IWM_TE_V2_DEP_OTHER (1 << IWM_TE_V2_PLACEMENT_POS)

Definition at line 2868 of file if_iwmreg.h.

◆ IWM_TE_V2_DEP_TSF

#define IWM_TE_V2_DEP_TSF (1 << (IWM_TE_V2_PLACEMENT_POS + 1))

Definition at line 2869 of file if_iwmreg.h.

◆ IWM_TE_V2_EVENT_SOCIOPATHIC

#define IWM_TE_V2_EVENT_SOCIOPATHIC (1 << (IWM_TE_V2_PLACEMENT_POS + 2))

Definition at line 2870 of file if_iwmreg.h.

◆ IWM_TE_V2_FRAG_DUAL

#define IWM_TE_V2_FRAG_DUAL 2

Definition at line 2819 of file if_iwmreg.h.

◆ IWM_TE_V2_FRAG_ENDLESS

#define IWM_TE_V2_FRAG_ENDLESS 0xff

Definition at line 2821 of file if_iwmreg.h.

◆ IWM_TE_V2_FRAG_MAX

#define IWM_TE_V2_FRAG_MAX 0xfe

Definition at line 2820 of file if_iwmreg.h.

◆ IWM_TE_V2_FRAG_NONE

#define IWM_TE_V2_FRAG_NONE 0

DOC: Time Events - what is it?

Time Events are a fw feature that allows the driver to control the presence of the device on the channel. Since the fw supports multiple channels concurrently, the fw may choose to jump to another channel at any time. In order to make sure that the fw is on a specific channel at a certain time and for a certain duration, the driver needs to issue a time event.

The simplest example is for BSS association. The driver issues a time event, waits for it to start, and only then tells mac80211 that we can start the association. This way, we make sure that the association will be done smoothly and won't be interrupted by channel switch decided within the fw. DOC: The flow against the fw

When the driver needs to make sure we are in a certain channel, at a certain time and for a certain duration, it sends a Time Event. The flow against the fw goes like this: 1) Driver sends a TIME_EVENT_CMD to the fw 2) Driver gets the response for that command. This response contains the Unique ID (UID) of the event. 3) The fw sends notification when the event starts.

Of course the API provides various options that allow to cover parameters of the flow. What is the duration of the event? What is the start time of the event? Is there an end-time for the event? How much can the event be delayed? Can the event be split? If yes what is the maximal number of chunks? etc...

Definition at line 2817 of file if_iwmreg.h.

◆ IWM_TE_V2_FRAG_SINGLE

#define IWM_TE_V2_FRAG_SINGLE 1

Definition at line 2818 of file if_iwmreg.h.

◆ IWM_TE_V2_NOTIF_HOST_EVENT_END

#define IWM_TE_V2_NOTIF_HOST_EVENT_END (1 << 1)

Definition at line 2855 of file if_iwmreg.h.

◆ IWM_TE_V2_NOTIF_HOST_EVENT_START

#define IWM_TE_V2_NOTIF_HOST_EVENT_START (1 << 0)

Definition at line 2854 of file if_iwmreg.h.

◆ IWM_TE_V2_NOTIF_HOST_FRAG_END

#define IWM_TE_V2_NOTIF_HOST_FRAG_END (1 << 5)

Definition at line 2860 of file if_iwmreg.h.

◆ IWM_TE_V2_NOTIF_HOST_FRAG_START

#define IWM_TE_V2_NOTIF_HOST_FRAG_START (1 << 4)

Definition at line 2859 of file if_iwmreg.h.

◆ IWM_TE_V2_NOTIF_INTERNAL_EVENT_END

#define IWM_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3)

Definition at line 2857 of file if_iwmreg.h.

◆ IWM_TE_V2_NOTIF_INTERNAL_EVENT_START

#define IWM_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2)

Definition at line 2856 of file if_iwmreg.h.

◆ IWM_TE_V2_NOTIF_INTERNAL_FRAG_END

#define IWM_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7)

Definition at line 2862 of file if_iwmreg.h.

◆ IWM_TE_V2_NOTIF_INTERNAL_FRAG_START

#define IWM_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6)

Definition at line 2861 of file if_iwmreg.h.

◆ IWM_TE_V2_NOTIF_MSK

#define IWM_TE_V2_NOTIF_MSK 0xff

Definition at line 2865 of file if_iwmreg.h.

◆ IWM_TE_V2_PLACEMENT_POS

#define IWM_TE_V2_PLACEMENT_POS 12

Definition at line 2828 of file if_iwmreg.h.

◆ IWM_TE_V2_REPEAT_ENDLESS

#define IWM_TE_V2_REPEAT_ENDLESS 0xff

Definition at line 2824 of file if_iwmreg.h.

◆ IWM_TE_V2_REPEAT_MAX

#define IWM_TE_V2_REPEAT_MAX 0xfe

Definition at line 2826 of file if_iwmreg.h.

◆ IWM_TE_WIDI_TX_SYNC

#define IWM_TE_WIDI_TX_SYNC 14

Definition at line 2695 of file if_iwmreg.h.

◆ IWM_TEMP_REPORTING_THRESHOLDS_CMD

#define IWM_TEMP_REPORTING_THRESHOLDS_CMD 0x04

Definition at line 2135 of file if_iwmreg.h.

◆ IWM_TEMPERATURE_NOTIFICATION

#define IWM_TEMPERATURE_NOTIFICATION 0x62

Definition at line 2024 of file if_iwmreg.h.

◆ IWM_TFD_QUEUE_BC_SIZE

#define IWM_TFD_QUEUE_BC_SIZE

Value:

(IWM_TFD_QUEUE_SIZE_MAX + \

IWM_TFD_QUEUE_SIZE_BC_DUP)

IWM_TFD_QUEUE_SIZE_MAX

#define IWM_TFD_QUEUE_SIZE_MAX

Definition: if_iwmreg.h:1834

Definition at line 1836 of file if_iwmreg.h.

◆ IWM_TFD_QUEUE_SIZE_BC_DUP

#define IWM_TFD_QUEUE_SIZE_BC_DUP (64)

Definition at line 1835 of file if_iwmreg.h.

◆ IWM_TFD_QUEUE_SIZE_MAX

#define IWM_TFD_QUEUE_SIZE_MAX (256)

Definition at line 1834 of file if_iwmreg.h.

◆ IWM_TID_MGMT

#define IWM_TID_MGMT 15

Definition at line 4909 of file if_iwmreg.h.

◆ IWM_TID_NON_QOS

#define IWM_TID_NON_QOS 0

Definition at line 4908 of file if_iwmreg.h.

◆ IWM_TIME_EVENT_CMD

#define IWM_TIME_EVENT_CMD 0x29 /* both CMD and response */

Definition at line 2015 of file if_iwmreg.h.

◆ IWM_TIME_EVENT_NOTIFICATION

#define IWM_TIME_EVENT_NOTIFICATION 0x2a

Definition at line 2016 of file if_iwmreg.h.

◆ IWM_TIME_QUOTA_CMD

#define IWM_TIME_QUOTA_CMD 0x2c

Definition at line 2018 of file if_iwmreg.h.

◆ IWM_TLV_UCODE_MAGIC

#define IWM_TLV_UCODE_MAGIC 0x0a4c5749

Definition at line 1166 of file if_iwmreg.h.

◆ IWM_TSF_ID_A

#define IWM_TSF_ID_A 0

TSF hw timer ID @IWM_TSF_ID_A: use TSF A @IWM_TSF_ID_B: use TSF B @IWM_TSF_ID_C: use TSF C @IWM_TSF_ID_D: use TSF D @IWM_NUM_TSF_IDS: number of TSF timers available

Definition at line 3875 of file if_iwmreg.h.

◆ IWM_TSF_ID_B

#define IWM_TSF_ID_B 1

Definition at line 3876 of file if_iwmreg.h.

◆ IWM_TSF_ID_C

#define IWM_TSF_ID_C 2

Definition at line 3877 of file if_iwmreg.h.

◆ IWM_TSF_ID_D

#define IWM_TSF_ID_D 3

Definition at line 3878 of file if_iwmreg.h.

◆ IWM_TX_ANT_CONFIGURATION_CMD

#define IWM_TX_ANT_CONFIGURATION_CMD 0x98

Definition at line 2063 of file if_iwmreg.h.

◆ IWM_TX_CMD

#define IWM_TX_CMD 0x1c

Definition at line 2003 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_ACK

#define IWM_TX_CMD_FLG_ACK (1 << 3)

Definition at line 4822 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_AGG_START

#define IWM_TX_CMD_FLG_AGG_START (1 << 19)

Definition at line 4837 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_BA

#define IWM_TX_CMD_FLG_BA (1 << 5)

Definition at line 4824 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_BAR

#define IWM_TX_CMD_FLG_BAR (1 << 6)

Definition at line 4825 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_BT_DIS

#define IWM_TX_CMD_FLG_BT_DIS (1 << 12)

Definition at line 4830 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_CALIB

#define IWM_TX_CMD_FLG_CALIB (1 << 17)

Definition at line 4835 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_CCMP_AGG

#define IWM_TX_CMD_FLG_CCMP_AGG (1 << 22)

Definition at line 4840 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_CSI_FDBK2HOST

#define IWM_TX_CMD_FLG_CSI_FDBK2HOST (1 << 10)

Definition at line 4829 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_DUR

#define IWM_TX_CMD_FLG_DUR (1 << 25)

Definition at line 4842 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_EXEC_PAPD

#define IWM_TX_CMD_FLG_EXEC_PAPD (1 << 27)

Definition at line 4844 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_FW_DROP

#define IWM_TX_CMD_FLG_FW_DROP (1 << 26)

Definition at line 4843 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_HCCA_CHUNK

#define IWM_TX_CMD_FLG_HCCA_CHUNK (1U << 31)

Definition at line 4846 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_HT_NDPA

#define IWM_TX_CMD_FLG_HT_NDPA (1 << 9)

Definition at line 4828 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_KEEP_SEQ_CTL

#define IWM_TX_CMD_FLG_KEEP_SEQ_CTL (1 << 18)

Definition at line 4836 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_MH_PAD

#define IWM_TX_CMD_FLG_MH_PAD (1 << 20)

Definition at line 4838 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_MORE_FRAG

#define IWM_TX_CMD_FLG_MORE_FRAG (1 << 14)

Definition at line 4832 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_NEXT_FRAME

#define IWM_TX_CMD_FLG_NEXT_FRAME (1 << 15)

Definition at line 4833 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_PAPD_TYPE

#define IWM_TX_CMD_FLG_PAPD_TYPE (1 << 28)

Definition at line 4845 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_PROT_REQUIRE

#define IWM_TX_CMD_FLG_PROT_REQUIRE (1 << 0)

bitmasks for tx_flags in TX command @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command. Otherwise, use rate_n_flags from the TX command @IWM_TX_CMD_FLG_BA: this frame is a block ack @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected Must set IWM_TX_CMD_FLG_ACK with this flag. @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC) @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control. Should be set for mgmt, non-QOS data, mcast, bcast and in scan command @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame Should be set for beacons and probe responses @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header. Should be set for 26/30 length MAC headers @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk

Definition at line 4821 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_RESP_TO_DRV

#define IWM_TX_CMD_FLG_RESP_TO_DRV (1 << 21)

Definition at line 4839 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_SEQ_CTL

#define IWM_TX_CMD_FLG_SEQ_CTL (1 << 13)

Definition at line 4831 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_STA_RATE

#define IWM_TX_CMD_FLG_STA_RATE (1 << 4)

Definition at line 4823 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_TKIP_MIC_DONE

#define IWM_TX_CMD_FLG_TKIP_MIC_DONE (1 << 23)

Definition at line 4841 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_TSF

#define IWM_TX_CMD_FLG_TSF (1 << 16)

Definition at line 4834 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_TXOP_PROT

#define IWM_TX_CMD_FLG_TXOP_PROT (1 << 7)

Definition at line 4826 of file if_iwmreg.h.

◆ IWM_TX_CMD_FLG_VHT_NDPA

#define IWM_TX_CMD_FLG_VHT_NDPA (1 << 8)

Definition at line 4827 of file if_iwmreg.h.

◆ IWM_TX_CMD_LIFE_TIME_DEFAULT

#define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/

Definition at line 4900 of file if_iwmreg.h.

◆ IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME

#define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0

Definition at line 4902 of file if_iwmreg.h.

◆ IWM_TX_CMD_LIFE_TIME_INFINITE

#define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF

Definition at line 4899 of file if_iwmreg.h.

◆ IWM_TX_CMD_LIFE_TIME_PROBE_RESP

#define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */

Definition at line 4901 of file if_iwmreg.h.

◆ IWM_TX_CMD_NEXT_FRAME_ACK_MSK

#define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)

Definition at line 4886 of file if_iwmreg.h.

◆ IWM_TX_CMD_NEXT_FRAME_BA_MSK

#define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)

Definition at line 4888 of file if_iwmreg.h.

◆ IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK

#define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)

Definition at line 4890 of file if_iwmreg.h.

◆ IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK

#define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)

Definition at line 4889 of file if_iwmreg.h.

◆ IWM_TX_CMD_NEXT_FRAME_RATE_MSK

#define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)

Definition at line 4893 of file if_iwmreg.h.

◆ IWM_TX_CMD_NEXT_FRAME_RATE_POS

#define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)

Definition at line 4894 of file if_iwmreg.h.

◆ IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK

#define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)

Definition at line 4891 of file if_iwmreg.h.

◆ IWM_TX_CMD_NEXT_FRAME_STA_ID_POS

#define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)

Definition at line 4892 of file if_iwmreg.h.

◆ IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK

#define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)

Definition at line 4887 of file if_iwmreg.h.

◆ IWM_TX_CMD_OFFLD_AMSDU

#define IWM_TX_CMD_OFFLD_AMSDU (1 << 14)

Definition at line 4942 of file if_iwmreg.h.

◆ IWM_TX_CMD_OFFLD_IP_HDR

#define IWM_TX_CMD_OFFLD_IP_HDR (1 << 0)

enum iwm_tx_offload_assist_flags_pos - set iwm_tx_cmd offload_assist values @TX_CMD_OFFLD_IP_HDR: offset to start of IP header (in words) from mac header end. For normal case it is 4 words for SNAP. note: tx_cmd, mac header and pad are not counted in the offset. This is used to help the offload in case there is tunneling such as IPv6 in IPv4, in such case the ip header offset should point to the inner ip header and IPv4 checksum of the external header should be calculated by driver. @TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum @TX_CMD_OFFLD_L3_EN: enable IP header checksum @TX_CMD_OFFLD_MH_SIZE: size of the mac header in words. Includes the IV field. Doesn't include the pad. @TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for alignment @TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU

Definition at line 4937 of file if_iwmreg.h.

◆ IWM_TX_CMD_OFFLD_L3_EN

#define IWM_TX_CMD_OFFLD_L3_EN (1 << 7)

Definition at line 4939 of file if_iwmreg.h.

◆ IWM_TX_CMD_OFFLD_L4_EN

#define IWM_TX_CMD_OFFLD_L4_EN (1 << 6)

Definition at line 4938 of file if_iwmreg.h.

◆ IWM_TX_CMD_OFFLD_MH_SIZE

#define IWM_TX_CMD_OFFLD_MH_SIZE (1 << 8)

Definition at line 4940 of file if_iwmreg.h.

◆ IWM_TX_CMD_OFFLD_PAD

#define IWM_TX_CMD_OFFLD_PAD (1 << 13)

Definition at line 4941 of file if_iwmreg.h.

◆ IWM_TX_CMD_SEC_CCM

#define IWM_TX_CMD_SEC_CCM 0x02

Definition at line 4865 of file if_iwmreg.h.

◆ IWM_TX_CMD_SEC_EXT

#define IWM_TX_CMD_SEC_EXT 0x04

Definition at line 4867 of file if_iwmreg.h.

◆ IWM_TX_CMD_SEC_KEY128

#define IWM_TX_CMD_SEC_KEY128 0x08

Definition at line 4871 of file if_iwmreg.h.

◆ IWM_TX_CMD_SEC_MSK

#define IWM_TX_CMD_SEC_MSK 0x07

Definition at line 4868 of file if_iwmreg.h.

◆ IWM_TX_CMD_SEC_TKIP

#define IWM_TX_CMD_SEC_TKIP 0x03

Definition at line 4866 of file if_iwmreg.h.

◆ IWM_TX_CMD_SEC_WEP

#define IWM_TX_CMD_SEC_WEP 0x01

Definition at line 4864 of file if_iwmreg.h.

◆ IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK

#define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0

Definition at line 4870 of file if_iwmreg.h.

◆ IWM_TX_CMD_SEC_WEP_KEY_IDX_POS

#define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6

Definition at line 4869 of file if_iwmreg.h.

◆ IWM_TX_CRC_SIZE

#define IWM_TX_CRC_SIZE 4

Definition at line 1919 of file if_iwmreg.h.

◆ IWM_TX_DELIMITER_SIZE

#define IWM_TX_DELIMITER_SIZE 4

Definition at line 1920 of file if_iwmreg.h.

◆ IWM_TX_DMA_MASK

#define IWM_TX_DMA_MASK DMA_BIT_MASK(36)

Definition at line 1838 of file if_iwmreg.h.

◆ IWM_TX_FIFO_BE

#define IWM_TX_FIFO_BE 1

Definition at line 1971 of file if_iwmreg.h.

◆ IWM_TX_FIFO_BK

#define IWM_TX_FIFO_BK 0

Definition at line 1970 of file if_iwmreg.h.

◆ IWM_TX_FIFO_CMD

#define IWM_TX_FIFO_CMD 7

Definition at line 1975 of file if_iwmreg.h.

◆ IWM_TX_FIFO_MCAST

#define IWM_TX_FIFO_MCAST 5

Definition at line 1974 of file if_iwmreg.h.

◆ IWM_TX_FIFO_VI

#define IWM_TX_FIFO_VI 2

Definition at line 1972 of file if_iwmreg.h.

◆ IWM_TX_FIFO_VO

#define IWM_TX_FIFO_VO 3

Definition at line 1973 of file if_iwmreg.h.

◆ IWM_TX_MODE_FIRST_IN_BURST

#define IWM_TX_MODE_FIRST_IN_BURST 0x00000200

Definition at line 5052 of file if_iwmreg.h.

◆ IWM_TX_MODE_IN_BURST_SEQ

#define IWM_TX_MODE_IN_BURST_SEQ 0x00000100

Definition at line 5051 of file if_iwmreg.h.

◆ IWM_TX_MODE_MSK

#define IWM_TX_MODE_MSK 0x00000f00

Definition at line 5049 of file if_iwmreg.h.

◆ IWM_TX_MODE_NO_BURST

#define IWM_TX_MODE_NO_BURST 0x00000000

Definition at line 5050 of file if_iwmreg.h.

◆ IWM_TX_NARROW_BW_1DIV2

#define IWM_TX_NARROW_BW_1DIV2 0x00020000

Definition at line 5055 of file if_iwmreg.h.

◆ IWM_TX_NARROW_BW_1DIV4

#define IWM_TX_NARROW_BW_1DIV4 0x00040000

Definition at line 5056 of file if_iwmreg.h.

◆ IWM_TX_NARROW_BW_1DIV8

#define IWM_TX_NARROW_BW_1DIV8 0x00060000

Definition at line 5057 of file if_iwmreg.h.

◆ IWM_TX_NARROW_BW_MSK

#define IWM_TX_NARROW_BW_MSK 0x00060000

Definition at line 5054 of file if_iwmreg.h.

◆ IWM_TX_QUEUE_NUM_MSK

#define IWM_TX_QUEUE_NUM_MSK 0x0001f000

Definition at line 5053 of file if_iwmreg.h.

◆ IWM_TX_RES_GET_RA

#define IWM_TX_RES_GET_RA ( _ra_tid ) ((_ra_tid) >> 4)

Definition at line 5147 of file if_iwmreg.h.

◆ IWM_TX_RES_GET_TID

#define IWM_TX_RES_GET_TID ( _ra_tid ) ((_ra_tid) & 0x0f)

Definition at line 5146 of file if_iwmreg.h.

◆ IWM_TX_RES_INIT_RATE_INDEX_MSK

#define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f

Definition at line 5142 of file if_iwmreg.h.

◆ IWM_TX_RES_INV_RATE_INDEX_MSK

#define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80

Definition at line 5144 of file if_iwmreg.h.

◆ IWM_TX_RES_RATE_TABLE_COLOR_MSK

#define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70

Definition at line 5143 of file if_iwmreg.h.

◆ IWM_TX_STATUS_DIRECT_DONE

#define IWM_TX_STATUS_DIRECT_DONE 0x02

Definition at line 5023 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_BT_RETRY

#define IWM_TX_STATUS_FAIL_BT_RETRY 0x8a

Definition at line 5040 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_DEST_PS

#define IWM_TX_STATUS_FAIL_DEST_PS 0x88

Definition at line 5038 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_DRAIN_FLOW

#define IWM_TX_STATUS_FAIL_DRAIN_FLOW 0x85

Definition at line 5035 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_FIFO_FLUSHED

#define IWM_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e

Definition at line 5044 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_FRAG_DROPPED

#define IWM_TX_STATUS_FAIL_FRAG_DROPPED 0x8c

Definition at line 5042 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_FW_DROP

#define IWM_TX_STATUS_FAIL_FW_DROP 0x90

Definition at line 5046 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_HOST_ABORTED

#define IWM_TX_STATUS_FAIL_HOST_ABORTED 0x89

Definition at line 5039 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY

#define IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81

Definition at line 5031 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_LIFE_EXPIRE

#define IWM_TX_STATUS_FAIL_LIFE_EXPIRE 0x87

Definition at line 5037 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_LONG_LIMIT

#define IWM_TX_STATUS_FAIL_LONG_LIMIT 0x83

Definition at line 5033 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_RFKILL_FLUSH

#define IWM_TX_STATUS_FAIL_RFKILL_FLUSH 0x86

Definition at line 5036 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_SHORT_LIMIT

#define IWM_TX_STATUS_FAIL_SHORT_LIMIT 0x82

Definition at line 5032 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_SMALL_CF_POLL

#define IWM_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f

Definition at line 5045 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH

#define IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91

Definition at line 5047 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_STA_INVALID

#define IWM_TX_STATUS_FAIL_STA_INVALID 0x8b

Definition at line 5041 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_TID_DISABLE

#define IWM_TX_STATUS_FAIL_TID_DISABLE 0x8d

Definition at line 5043 of file if_iwmreg.h.

◆ IWM_TX_STATUS_FAIL_UNDERRUN

#define IWM_TX_STATUS_FAIL_UNDERRUN 0x84

Definition at line 5034 of file if_iwmreg.h.

◆ IWM_TX_STATUS_INTERNAL_ABORT

#define IWM_TX_STATUS_INTERNAL_ABORT 0x92

Definition at line 5048 of file if_iwmreg.h.

◆ IWM_TX_STATUS_MSK

#define IWM_TX_STATUS_MSK 0x000000ff

Definition at line 5021 of file if_iwmreg.h.

◆ IWM_TX_STATUS_POSTPONE_BT_PRIO

#define IWM_TX_STATUS_POSTPONE_BT_PRIO 0x42

Definition at line 5027 of file if_iwmreg.h.

◆ IWM_TX_STATUS_POSTPONE_CALC_TTAK

#define IWM_TX_STATUS_POSTPONE_CALC_TTAK 0x44

Definition at line 5029 of file if_iwmreg.h.

◆ IWM_TX_STATUS_POSTPONE_DELAY

#define IWM_TX_STATUS_POSTPONE_DELAY 0x40

Definition at line 5025 of file if_iwmreg.h.

◆ IWM_TX_STATUS_POSTPONE_FEW_BYTES

#define IWM_TX_STATUS_POSTPONE_FEW_BYTES 0x41

Definition at line 5026 of file if_iwmreg.h.

◆ IWM_TX_STATUS_POSTPONE_QUIET_PERIOD

#define IWM_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43

Definition at line 5028 of file if_iwmreg.h.

◆ IWM_TX_STATUS_SUCCESS

#define IWM_TX_STATUS_SUCCESS 0x01

Definition at line 5022 of file if_iwmreg.h.

◆ IWM_TXPATH_FLUSH

#define IWM_TXPATH_FLUSH 0x1e

Definition at line 2004 of file if_iwmreg.h.

◆ IWM_UCODE_API

#define IWM_UCODE_API ( ver ) (((ver) & 0x0000FF00) >> 8)

Definition at line 986 of file if_iwmreg.h.

◆ IWM_UCODE_MAJOR

#define IWM_UCODE_MAJOR ( ver ) (((ver) & 0xFF000000) >> 24)

Definition at line 984 of file if_iwmreg.h.

◆ IWM_UCODE_MAX_CS

#define IWM_UCODE_MAX_CS 1

Definition at line 1013 of file if_iwmreg.h.

◆ IWM_UCODE_MINOR

#define IWM_UCODE_MINOR ( ver ) (((ver) & 0x00FF0000) >> 16)

Definition at line 985 of file if_iwmreg.h.

◆ IWM_UCODE_SERIAL

#define IWM_UCODE_SERIAL ( ver ) ((ver) & 0x000000FF)

Definition at line 987 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_ADAPTIVE_DWELL

#define IWM_UCODE_TLV_API_ADAPTIVE_DWELL 32

Definition at line 853 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2

#define IWM_UCODE_TLV_API_ADAPTIVE_DWELL_V2 42

Definition at line 856 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_BITS

#define IWM_UCODE_TLV_API_BITS "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS"

Definition at line 860 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY

#define IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY 24

Definition at line 847 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_FRAGMENTED_SCAN

#define IWM_UCODE_TLV_API_FRAGMENTED_SCAN 8

uCode TLV api @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time longer than the passive one, which is essential for fragmented scan. @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source. @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params @IWM_UCODE_TLV_API_NEW_VERSION: new versioning format @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size (command version 3) that supports per-chain limits @IWM_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan iteration complete notification, and the timestamp reported for RX received during scan, are reported in TSF of the mac specified in the scan request. @IWM_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of ADD_MODIFY_STA_KEY_API_S_VER_2. @IWM_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignement. @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority instead of 3. @IWM_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used

@IWM_NUM_UCODE_TLV_API: number of bits used

Definition at line 842 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_LQ_SS_PARAMS

#define IWM_UCODE_TLV_API_LQ_SS_PARAMS 18

Definition at line 845 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_NAN2_VER2

#define IWM_UCODE_TLV_API_NAN2_VER2 31

Definition at line 852 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_NEW_RX_STATS

#define IWM_UCODE_TLV_API_NEW_RX_STATS 35

Definition at line 854 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_NEW_VERSION

#define IWM_UCODE_TLV_API_NEW_VERSION 20

Definition at line 846 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY

#define IWM_UCODE_TLV_API_QUOTA_LOW_LATENCY 38

Definition at line 855 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_SCAN_EXT_CHAN_VER

#define IWM_UCODE_TLV_API_SCAN_EXT_CHAN_VER 58

Definition at line 857 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_SCAN_TSF_REPORT

#define IWM_UCODE_TLV_API_SCAN_TSF_REPORT 28

Definition at line 849 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_STA_TYPE

#define IWM_UCODE_TLV_API_STA_TYPE 30

Definition at line 851 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_TKIP_MIC_KEYS

#define IWM_UCODE_TLV_API_TKIP_MIC_KEYS 29

Definition at line 850 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_TX_POWER_CHAIN

#define IWM_UCODE_TLV_API_TX_POWER_CHAIN 27

Definition at line 848 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_WIDE_CMD_HDR

#define IWM_UCODE_TLV_API_WIDE_CMD_HDR 14

Definition at line 844 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_API_WIFI_MCC_UPDATE

#define IWM_UCODE_TLV_API_WIFI_MCC_UPDATE 9

Definition at line 843 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT

#define IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20

Definition at line 936 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION

#define IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71

Definition at line 955 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_BEACON_STORING

#define IWM_UCODE_TLV_CAPA_BEACON_STORING 72

Definition at line 956 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_BEAMFORMER

#define IWM_UCODE_TLV_CAPA_BEAMFORMER 3

Definition at line 924 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT

#define IWM_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT 39

Definition at line 947 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_BT_COEX_PLCR

#define IWM_UCODE_TLV_CAPA_BT_COEX_PLCR 28

Definition at line 940 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_BT_COEX_RRC

#define IWM_UCODE_TLV_CAPA_BT_COEX_RRC 30

Definition at line 942 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT

#define IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67

Definition at line 953 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_CDB_SUPPORT

#define IWM_UCODE_TLV_CAPA_CDB_SUPPORT 40

Definition at line 948 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG

#define IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17

Definition at line 933 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_CSUM_SUPPORT

#define IWM_UCODE_TLV_CAPA_CSUM_SUPPORT 21

Definition at line 937 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW

#define IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW 74

Definition at line 958 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_CTDP_SUPPORT

#define IWM_UCODE_TLV_CAPA_CTDP_SUPPORT 76

Definition at line 960 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_D0I3_SUPPORT

#define IWM_UCODE_TLV_CAPA_D0I3_SUPPORT 0

uCode capabilities @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3 @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan. @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM) @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current tx power value into TPC Report action frame and Link Measurement Report action frame @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current channel in DS parameter set element in probe requests. @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in probe requests. @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA), which also implies support for the scheduler configuration command @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different sources for the MCC. This TLV bit is a future replacement to IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR is supported. @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported, 0=no support) @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what antenna the beacon should be transmitted @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon from AP and will send it upon d0i3 exit. @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2 @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature thresholds reporting @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in regular image. @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared memory addresses from the firmware. @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported, 0=no support)

@IWM_NUM_UCODE_TLV_CAPA: number of bits used

Definition at line 921 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT

#define IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19

Definition at line 935 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_DQA_SUPPORT

#define IWM_UCODE_TLV_CAPA_DQA_SUPPORT 12

Definition at line 931 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT

#define IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9

Definition at line 928 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_DYNAMIC_QUOTA

#define IWM_UCODE_TLV_CAPA_DYNAMIC_QUOTA 44

Definition at line 949 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG

#define IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80

Definition at line 963 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE

#define IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64

Definition at line 951 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT

#define IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT 31

Definition at line 943 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT

#define IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18

Definition at line 934 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC

#define IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC 29

Definition at line 941 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_LAR_SUPPORT

#define IWM_UCODE_TLV_CAPA_LAR_SUPPORT 1

Definition at line 922 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2

#define IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 73

Definition at line 957 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_LMAC_UPLOAD

#define IWM_UCODE_TLV_CAPA_LMAC_UPLOAD 79

Definition at line 962 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_LQM_SUPPORT

#define IWM_UCODE_TLV_CAPA_LQM_SUPPORT 81

Definition at line 964 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT

#define IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68

Definition at line 954 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_NAN_SUPPORT

#define IWM_UCODE_TLV_CAPA_NAN_SUPPORT 34

Definition at line 944 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD

#define IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26

Definition at line 939 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT

#define IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11

Definition at line 930 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS

#define IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22

Definition at line 938 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS

#define IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65

Definition at line 952 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT

#define IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT 37

Definition at line 946 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH

#define IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13

Definition at line 932 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_TDLS_SUPPORT

#define IWM_UCODE_TLV_CAPA_TDLS_SUPPORT 6

Definition at line 926 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT

#define IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75

Definition at line 959 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_TOF_SUPPORT

#define IWM_UCODE_TLV_CAPA_TOF_SUPPORT 5

Definition at line 925 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT

#define IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8

Definition at line 927 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS

#define IWM_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS 48

Definition at line 950 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_UMAC_SCAN

#define IWM_UCODE_TLV_CAPA_UMAC_SCAN 2

Definition at line 923 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_UMAC_UPLOAD

#define IWM_UCODE_TLV_CAPA_UMAC_UPLOAD 35

Definition at line 945 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED

#define IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77

Definition at line 961 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT

#define IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10

Definition at line 929 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_DEBUG_BASE

#define IWM_UCODE_TLV_DEBUG_BASE 0x1000005

Definition at line 1142 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_DEBUG_MAX

#define IWM_UCODE_TLV_DEBUG_MAX IWM_UCODE_TLV_TYPE_TRIGGERS

Definition at line 1148 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAG_BITS

#define IWM_UCODE_TLV_FLAG_BITS "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"

Definition at line 816 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_BCAST_FILTERING

#define IWM_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29)

Definition at line 812 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM

#define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22)

Definition at line 807 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM

#define IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23)

Definition at line 808 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS

#define IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10)

Definition at line 802 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_DW_BC_TABLE

#define IWM_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4)

Definition at line 800 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_EBS_SUPPORT

#define IWM_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25)

Definition at line 810 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_GO_UAPSD

#define IWM_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30)

Definition at line 813 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_LTE_COEX

#define IWM_UCODE_TLV_FLAGS_LTE_COEX (1U << 31)

Definition at line 814 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_MFP

#define IWM_UCODE_TLV_FLAGS_MFP (1 << 2)

Definition at line 798 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE

#define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16)

Definition at line 805 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL

#define IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15)

Definition at line 804 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_NEWSCAN

#define IWM_UCODE_TLV_FLAGS_NEWSCAN (1 << 1)

Definition at line 797 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID

#define IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12)

Definition at line 803 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_P2P

#define IWM_UCODE_TLV_FLAGS_P2P (1 << 3)

Definition at line 799 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_P2P_PS

#define IWM_UCODE_TLV_FLAGS_P2P_PS (1 << 21)

Definition at line 806 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD

#define IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26)

Definition at line 811 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_PAN

#define IWM_UCODE_TLV_FLAGS_PAN (1 << 0)

uCode API flags @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously was a separate TLV but moved here to save space. @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID, treats good CRC threshold as a boolean @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w). @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P. @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan offload profile config command. @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six (rather than two) IPv6 addresses @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element from the probe request template. @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version) @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version) @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a single bound interface). @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS. @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering. @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients

Definition at line 796 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_SHORT_BL

#define IWM_UCODE_TLV_FLAGS_SHORT_BL (1 << 7)

Definition at line 801 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT

#define IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24)

Definition at line 809 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_TYPE_BUFFER_ALLOCATION

#define IWM_UCODE_TLV_TYPE_BUFFER_ALLOCATION (IWM_UCODE_TLV_DEBUG_BASE + 1)

Definition at line 1144 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_TYPE_DEBUG_INFO

#define IWM_UCODE_TLV_TYPE_DEBUG_INFO (IWM_UCODE_TLV_DEBUG_BASE + 0)

Definition at line 1143 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_TYPE_HCMD

#define IWM_UCODE_TLV_TYPE_HCMD (IWM_UCODE_TLV_DEBUG_BASE + 2)

Definition at line 1145 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_TYPE_REGIONS

#define IWM_UCODE_TLV_TYPE_REGIONS (IWM_UCODE_TLV_DEBUG_BASE + 3)

Definition at line 1146 of file if_iwmreg.h.

◆ IWM_UCODE_TLV_TYPE_TRIGGERS

#define IWM_UCODE_TLV_TYPE_TRIGGERS (IWM_UCODE_TLV_DEBUG_BASE + 4)

Definition at line 1147 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_FLAG_PREEMPTIVE

#define IWM_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0)

iwm_umac_scan_flags @IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request can be preempted by other scan requests with higher priority. The low priority scan will be resumed when the higher proirity scan is completed. @IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver when scan starts.

Definition at line 5807 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_FLAG_START_NOTIF

#define IWM_UMAC_SCAN_FLAG_START_NOTIF (1 << 1)

Definition at line 5808 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER

#define IWM_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER (1 << 1)

Definition at line 5841 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL

#define IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL (1 << 0)

UMAC scan general flags #2 @IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL: Whether to send a complete notification per channel or not. @IWM_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER: Whether to allow channel reorder optimization or not.

Definition at line 5840 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL

#define IWM_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL (1 << 13)

Definition at line 5829 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL

#define IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10)

Definition at line 5823 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED

#define IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7)

Definition at line 5820 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE

#define IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5)

Definition at line 5818 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED

#define IWM_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED (1 << 11)

Definition at line 5828 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_MATCH

#define IWM_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9)

Definition at line 5822 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME

#define IWM_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME (1 << 14)

Definition at line 5830 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID

#define IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6)

Definition at line 5819 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT

#define IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1)

Definition at line 5814 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL

#define IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2)

Definition at line 5815 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE

#define IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3)

Definition at line 5816 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC

#define IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0)

Definition at line 5813 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT

#define IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4)

Definition at line 5817 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP

#define IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP (1 << 10)

Definition at line 5827 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE

#define IWM_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE (1 << 15)

Definition at line 5831 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED

#define IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8)

Definition at line 5821 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_UID_SEQ_OFFSET

#define IWM_UMAC_SCAN_UID_SEQ_OFFSET 8

Definition at line 5811 of file if_iwmreg.h.

◆ IWM_UMAC_SCAN_UID_TYPE_OFFSET

#define IWM_UMAC_SCAN_UID_TYPE_OFFSET 0

Definition at line 5810 of file if_iwmreg.h.

◆ IWM_UNIFIED_SCAN_CHANNEL_FULL

#define IWM_UNIFIED_SCAN_CHANNEL_FULL (1 << 27)

Definition at line 5425 of file if_iwmreg.h.

◆ IWM_UNIFIED_SCAN_CHANNEL_PARTIAL

#define IWM_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28)

Definition at line 5426 of file if_iwmreg.h.

◆ IWM_UREG_CHICK

#define IWM_UREG_CHICK 0xa05c00

Definition at line 638 of file if_iwmreg.h.

◆ IWM_UREG_CHICK_MSI_ENABLE

#define IWM_UREG_CHICK_MSI_ENABLE (1 << 24)

Definition at line 639 of file if_iwmreg.h.

◆ IWM_UREG_CHICK_MSIX_ENABLE

#define IWM_UREG_CHICK_MSIX_ENABLE (1 << 25)

Definition at line 640 of file if_iwmreg.h.

◆ IWM_WEP_KEY

#define IWM_WEP_KEY 0x20

Definition at line 2011 of file if_iwmreg.h.

◆ IWM_WFMP_MAC_ADDR_0

#define IWM_WFMP_MAC_ADDR_0 0xa03080

Definition at line 612 of file if_iwmreg.h.

◆ IWM_WFMP_MAC_ADDR_1

#define IWM_WFMP_MAC_ADDR_1 0xa03084

Definition at line 613 of file if_iwmreg.h.

◆ IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK

#define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000

Definition at line 618 of file if_iwmreg.h.

◆ IWM_WFPM_CTRL_REG

#define IWM_WFPM_CTRL_REG 0xa03030

Definition at line 617 of file if_iwmreg.h.

◆ IWM_WFPM_PS_CTL_CLR

#define IWM_WFPM_PS_CTL_CLR 0xa0300c

Definition at line 611 of file if_iwmreg.h.

◆ IWM_WIDE_ID

#define IWM_WIDE_ID	(	grp,
		opcode
	)	((grp << 8) \| opcode)

Definition at line 6854 of file if_iwmreg.h.

◆ IWM_WOWLAN_CONFIGURATION

#define IWM_WOWLAN_CONFIGURATION 0xe1

Definition at line 2113 of file if_iwmreg.h.

◆ IWM_WOWLAN_GET_STATUSES

#define IWM_WOWLAN_GET_STATUSES 0xe5

Definition at line 2117 of file if_iwmreg.h.

◆ IWM_WOWLAN_KEK_KCK_MATERIAL

#define IWM_WOWLAN_KEK_KCK_MATERIAL 0xe4

Definition at line 2116 of file if_iwmreg.h.

◆ IWM_WOWLAN_PATTERNS

#define IWM_WOWLAN_PATTERNS 0xe0

Definition at line 2112 of file if_iwmreg.h.

◆ IWM_WOWLAN_TKIP_PARAM

#define IWM_WOWLAN_TKIP_PARAM 0xe3

Definition at line 2115 of file if_iwmreg.h.

◆ IWM_WOWLAN_TSC_RSC_PARAM

#define IWM_WOWLAN_TSC_RSC_PARAM 0xe2

Definition at line 2114 of file if_iwmreg.h.

◆ IWM_WOWLAN_TX_POWER_PER_DB

#define IWM_WOWLAN_TX_POWER_PER_DB 0xe6

Definition at line 2118 of file if_iwmreg.h.

◆ IWM_WRITE

#define IWM_WRITE	(	sc,
		reg,
		val
	)	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))

Definition at line 6957 of file if_iwmreg.h.

◆ IWM_WRITE_1

#define IWM_WRITE_1	(	sc,
		reg,
		val
	)	bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))

Definition at line 6960 of file if_iwmreg.h.

◆ IWM_XTAL_CALIB

#define IWM_XTAL_CALIB (0x316 - IWM_NVM_CALIB_SECTION)

Definition at line 2323 of file if_iwmreg.h.

◆ IWM_XTAL_CALIB_8000

#define IWM_XTAL_CALIB_8000 (0x316 - IWM_NVM_CALIB_SECTION_8000)

Definition at line 2347 of file if_iwmreg.h.

◆ le16_to_cpup

#define le16_to_cpup ( _a_ ) (le16toh(*(const uint16_t *)(_a_)))

Definition at line 69 of file if_iwmreg.h.

◆ le32_to_cpup

#define le32_to_cpup ( _a_ ) (le32toh(*(const uint32_t *)(_a_)))

Definition at line 70 of file if_iwmreg.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

hw_rev values

Enumerator
IWM_SILICON_A_STEP
IWM_SILICON_B_STEP
IWM_SILICON_C_STEP

Definition at line 303 of file if_iwmreg.h.

◆ anonymous enum

anonymous enum

Enumerator
IWM_RATE_1M_INDEX
IWM_FIRST_CCK_RATE
IWM_RATE_2M_INDEX
IWM_RATE_5M_INDEX
IWM_RATE_11M_INDEX
IWM_LAST_CCK_RATE
IWM_RATE_6M_INDEX
IWM_FIRST_OFDM_RATE
IWM_RATE_MCS_0_INDEX
IWM_FIRST_HT_RATE
IWM_FIRST_VHT_RATE
IWM_RATE_9M_INDEX
IWM_RATE_12M_INDEX
IWM_RATE_MCS_1_INDEX
IWM_RATE_18M_INDEX
IWM_RATE_MCS_2_INDEX
IWM_RATE_24M_INDEX
IWM_RATE_MCS_3_INDEX
IWM_RATE_36M_INDEX
IWM_RATE_MCS_4_INDEX
IWM_RATE_48M_INDEX
IWM_RATE_MCS_5_INDEX
IWM_RATE_54M_INDEX
IWM_RATE_MCS_6_INDEX
IWM_LAST_NON_HT_RATE
IWM_RATE_60M_INDEX
IWM_RATE_MCS_7_INDEX
IWM_LAST_HT_RATE
IWM_RATE_MCS_8_INDEX
IWM_RATE_MCS_9_INDEX
IWM_LAST_VHT_RATE
IWM_RATE_COUNT_LEGACY
IWM_RATE_COUNT

Definition at line 4488 of file if_iwmreg.h.

◆ iwm_phy_db_section_type

enum iwm_phy_db_section_type

Enumerator
IWM_PHY_DB_CFG
IWM_PHY_DB_CALIB_NCH
IWM_PHY_DB_UNUSED
IWM_PHY_DB_CALIB_CHG_PAPD
IWM_PHY_DB_CALIB_CHG_TXP
IWM_PHY_DB_MAX

Definition at line 2279 of file if_iwmreg.h.

◆ iwm_scan_ebs_status

enum iwm_scan_ebs_status

Enumerator
IWM_SCAN_EBS_SUCCESS
IWM_SCAN_EBS_FAILED
IWM_SCAN_EBS_CHAN_NOT_FOUND
IWM_SCAN_EBS_INACTIVE

Definition at line 5681 of file if_iwmreg.h.

◆ iwm_scan_offload_complete_status

enum iwm_scan_offload_complete_status

Enumerator
IWM_SCAN_OFFLOAD_COMPLETED
IWM_SCAN_OFFLOAD_ABORTED

Definition at line 5676 of file if_iwmreg.h.

◆ iwm_sf_scenario

enum iwm_sf_scenario

Enumerator
IWM_SF_SCENARIO_SINGLE_UNICAST
IWM_SF_SCENARIO_AGG_UNICAST
IWM_SF_SCENARIO_MULTICAST
IWM_SF_SCENARIO_BA_RESP
IWM_SF_SCENARIO_TX_RESP
IWM_SF_NUM_SCENARIO

Definition at line 3739 of file if_iwmreg.h.

◆ iwm_sf_state

enum iwm_sf_state

Enumerator
IWM_SF_LONG_DELAY_ON
IWM_SF_FULL_ON
IWM_SF_UNINIT
IWM_SF_INIT_OFF
IWM_SF_HW_NUM_STATES

Definition at line 3730 of file if_iwmreg.h.

◆ iwm_tx_pm_timeouts

enum iwm_tx_pm_timeouts

enum iwm_tx_pm_timeouts - pm timeout values in TX command @IWM_PM_FRAME_NONE: no need to suspend sleep mode @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec

Enumerator
IWM_PM_FRAME_NONE
IWM_PM_FRAME_MGMT
IWM_PM_FRAME_ASSOC

Definition at line 4855 of file if_iwmreg.h.

◆ iwm_ucode_tlv_type

enum iwm_ucode_tlv_type

Enumerator
IWM_UCODE_TLV_INVALID
IWM_UCODE_TLV_INST
IWM_UCODE_TLV_DATA
IWM_UCODE_TLV_INIT
IWM_UCODE_TLV_INIT_DATA
IWM_UCODE_TLV_BOOT
IWM_UCODE_TLV_PROBE_MAX_LEN
IWM_UCODE_TLV_PAN
IWM_UCODE_TLV_RUNT_EVTLOG_PTR
IWM_UCODE_TLV_RUNT_EVTLOG_SIZE
IWM_UCODE_TLV_RUNT_ERRLOG_PTR
IWM_UCODE_TLV_INIT_EVTLOG_PTR
IWM_UCODE_TLV_INIT_EVTLOG_SIZE
IWM_UCODE_TLV_INIT_ERRLOG_PTR
IWM_UCODE_TLV_ENHANCE_SENS_TBL
IWM_UCODE_TLV_PHY_CALIBRATION_SIZE
IWM_UCODE_TLV_WOWLAN_INST
IWM_UCODE_TLV_WOWLAN_DATA
IWM_UCODE_TLV_FLAGS
IWM_UCODE_TLV_SEC_RT
IWM_UCODE_TLV_SEC_INIT
IWM_UCODE_TLV_SEC_WOWLAN
IWM_UCODE_TLV_DEF_CALIB
IWM_UCODE_TLV_PHY_SKU
IWM_UCODE_TLV_SECURE_SEC_RT
IWM_UCODE_TLV_SECURE_SEC_INIT
IWM_UCODE_TLV_SECURE_SEC_WOWLAN
IWM_UCODE_TLV_NUM_OF_CPU
IWM_UCODE_TLV_CSCHEME
IWM_UCODE_TLV_API_CHANGES_SET
IWM_UCODE_TLV_ENABLED_CAPABILITIES
IWM_UCODE_TLV_N_SCAN_CHANNELS
IWM_UCODE_TLV_PAGING
IWM_UCODE_TLV_SEC_RT_USNIFFER
IWM_UCODE_TLV_SDIO_ADMA_ADDR
IWM_UCODE_TLV_FW_VERSION
IWM_UCODE_TLV_FW_DBG_DEST
IWM_UCODE_TLV_FW_DBG_CONF
IWM_UCODE_TLV_FW_DBG_TRIGGER
IWM_UCODE_TLV_CMD_VERSIONS
IWM_UCODE_TLV_FW_GSCAN_CAPA
IWM_UCODE_TLV_FW_MEM_SEG
IWM_UCODE_TLV_UMAC_DEBUG_ADDRS
IWM_UCODE_TLV_LMAC_DEBUG_ADDRS
IWM_UCODE_TLV_HW_TYPE

Definition at line 1090 of file if_iwmreg.h.

◆ msix_fh_int_causes

enum msix_fh_int_causes

Enumerator
IWM_MSIX_FH_INT_CAUSES_Q0
IWM_MSIX_FH_INT_CAUSES_Q1
IWM_MSIX_FH_INT_CAUSES_D2S_CH0_NUM
IWM_MSIX_FH_INT_CAUSES_D2S_CH1_NUM
IWM_MSIX_FH_INT_CAUSES_S2D
IWM_MSIX_FH_INT_CAUSES_FH_ERR

Definition at line 709 of file if_iwmreg.h.

◆ msix_hw_int_causes

enum msix_hw_int_causes

Enumerator
IWM_MSIX_HW_INT_CAUSES_REG_ALIVE
IWM_MSIX_HW_INT_CAUSES_REG_WAKEUP
IWM_MSIX_HW_INT_CAUSES_REG_IPC
IWM_MSIX_HW_INT_CAUSES_REG_IML
IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2
IWM_MSIX_HW_INT_CAUSES_REG_CT_KILL
IWM_MSIX_HW_INT_CAUSES_REG_RF_KILL
IWM_MSIX_HW_INT_CAUSES_REG_PERIODIC
IWM_MSIX_HW_INT_CAUSES_REG_SW_ERR
IWM_MSIX_HW_INT_CAUSES_REG_SCD
IWM_MSIX_HW_INT_CAUSES_REG_FH_TX
IWM_MSIX_HW_INT_CAUSES_REG_HW_ERR
IWM_MSIX_HW_INT_CAUSES_REG_HAP

Definition at line 729 of file if_iwmreg.h.

◆ msix_ivar_for_cause

enum msix_ivar_for_cause

Enumerator
IWM_MSIX_IVAR_CAUSE_D2S_CH0_NUM
IWM_MSIX_IVAR_CAUSE_D2S_CH1_NUM
IWM_MSIX_IVAR_CAUSE_S2D
IWM_MSIX_IVAR_CAUSE_FH_ERR
IWM_MSIX_IVAR_CAUSE_REG_ALIVE
IWM_MSIX_IVAR_CAUSE_REG_WAKEUP
IWM_MSIX_IVAR_CAUSE_REG_IML
IWM_MSIX_IVAR_CAUSE_REG_CT_KILL
IWM_MSIX_IVAR_CAUSE_REG_RF_KILL
IWM_MSIX_IVAR_CAUSE_REG_PERIODIC
IWM_MSIX_IVAR_CAUSE_REG_SW_ERR
IWM_MSIX_IVAR_CAUSE_REG_SCD
IWM_MSIX_IVAR_CAUSE_REG_FH_TX
IWM_MSIX_IVAR_CAUSE_REG_HW_ERR
IWM_MSIX_IVAR_CAUSE_REG_HAP

Definition at line 748 of file if_iwmreg.h.

Function Documentation

◆ iwm_cmd_groupid()

static uint8_t iwm_cmd_groupid ( uint32_t cmdid )

inlinestatic

Definition at line 6836 of file if_iwmreg.h.

Referenced by iwm_send_cmd().

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◆ iwm_cmd_id()

static uint32_t iwm_cmd_id	(	uint8_t	opcode,
		uint8_t	groupid,
		uint8_t	version
	)

inlinestatic

Definition at line 6848 of file if_iwmreg.h.

Referenced by iwm_config_umac_scan(), iwm_send_paging_cmd(), iwm_umac_scan(), and iwm_umac_scan_abort().

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◆ iwm_cmd_opcode()

static uint8_t iwm_cmd_opcode ( uint32_t cmdid )

inlinestatic

Definition at line 6830 of file if_iwmreg.h.

Referenced by iwm_send_cmd().

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◆ iwm_cmd_version()

static uint8_t iwm_cmd_version ( uint32_t cmdid )

inlinestatic

Definition at line 6842 of file if_iwmreg.h.

Referenced by iwm_send_cmd().

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◆ IWM_FH_MEM_CBBC_QUEUE()

static unsigned int IWM_FH_MEM_CBBC_QUEUE ( unsigned int chnl )

inlinestatic

Definition at line 1490 of file if_iwmreg.h.

References IWM_FH_MEM_CBBC_0_15_LOWER_BOUND, IWM_FH_MEM_CBBC_16_19_LOWER_BOUND, and IWM_FH_MEM_CBBC_20_31_LOWER_BOUND.

Referenced by iwm_nic_tx_init().

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◆ iwm_get_dma_hi_addr()

static uint8_t iwm_get_dma_hi_addr ( bus_addr_t addr )

inlinestatic

Definition at line 1841 of file if_iwmreg.h.

Referenced by iwm_pcie_load_firmware_chunk(), iwm_send_cmd(), and iwm_tx().

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◆ iwm_get_scd_ssn()

static uint32_t iwm_get_scd_ssn ( struct iwm_tx_resp * tx_resp )

inlinestatic

iwm_get_scd_ssn - returns the SSN of the SCD @tx_resp: the Tx response from the fw (agg or non-agg)

When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since it can't know that everything will go well until the end of the AMPDU, it can't know in advance the number of MPDUs that will be sent in the current batch. This is why it writes the agg Tx response while it fetches the MPDUs. Hence, it can't know in advance what the SSN of the SCD will be at the end of the batch. This is why the SSN of the SCD is written at the end of the whole struct at a variable offset. This function knows how to cope with the variable offset and returns the SSN of the SCD.

Definition at line 5305 of file if_iwmreg.h.

References iwm_tx_resp::frame_count, le32_to_cpup, and iwm_tx_resp::status.

◆ iwm_reciprocal()

static uint32_t iwm_reciprocal ( uint32_t v )

inlinestatic

Definition at line 4104 of file if_iwmreg.h.

Referenced by iwm_mac_ctxt_cmd_fill_sta().

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◆ iwm_rx_packet_len()

static uint32_t iwm_rx_packet_len ( const struct iwm_rx_packet * pkt )

inlinestatic

Definition at line 6937 of file if_iwmreg.h.

References IWM_FH_RSCSR_FRAME_SIZE_MSK, and iwm_rx_packet::len_n_flags.

Referenced by iwm_handle_rxb(), and iwm_rx_packet_payload_len().

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◆ iwm_rx_packet_payload_len()

static uint32_t iwm_rx_packet_payload_len ( const struct iwm_rx_packet * pkt )

inlinestatic

Definition at line 6944 of file if_iwmreg.h.

References iwm_rx_packet::hdr, and iwm_rx_packet_len().

Referenced by iwm_alive_fn(), iwm_handle_rxb(), iwm_send_cmd_status(), iwm_te_notif(), and iwm_time_event_response().

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◆ IWM_SCD_QUEUE_RDPTR()

static unsigned int IWM_SCD_QUEUE_RDPTR ( unsigned int chnl )

inlinestatic

Definition at line 1409 of file if_iwmreg.h.

References IWM_SCD_BASE.

Referenced by iwm_enable_txq().

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◆ IWM_SCD_QUEUE_STATUS_BITS()

static unsigned int IWM_SCD_QUEUE_STATUS_BITS ( unsigned int chnl )

inlinestatic

Definition at line 1416 of file if_iwmreg.h.

References IWM_SCD_BASE.

Referenced by iwm_enable_txq().

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◆ IWM_SCD_QUEUE_WRPTR()

static unsigned int IWM_SCD_QUEUE_WRPTR ( unsigned int chnl )

inlinestatic

Definition at line 1402 of file if_iwmreg.h.

References IWM_SCD_BASE.

Variable Documentation

◆ __packed

struct iwm_rx_packet __packed

Data Structures

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ IWM_AC_BE

◆ IWM_AC_BK

◆ IWM_AC_NUM

◆ IWM_AC_VI

◆ IWM_AC_VO

◆ IWM_ADD_STA

◆ IWM_ADD_STA_BAID_MASK

◆ IWM_ADD_STA_BAID_SHIFT

◆ IWM_ADD_STA_BAID_VALID_MASK

◆ IWM_ADD_STA_IMMEDIATE_BA_FAILURE

◆ IWM_ADD_STA_KEY

◆ IWM_ADD_STA_MODIFY_NON_EXISTING_STA

◆ IWM_ADD_STA_STATIONS_OVERLOAD

◆ IWM_ADD_STA_STATUS_MASK

◆ IWM_ADD_STA_SUCCESS

◆ IWM_AGG_TX_STAT_FRAME_NOT_SENT

◆ IWM_AGG_TX_STATE_ABORT

◆ IWM_AGG_TX_STATE_BT_PRIO

◆ IWM_AGG_TX_STATE_DELAY_TX

◆ IWM_AGG_TX_STATE_DUMP_TX

◆ IWM_AGG_TX_STATE_FEW_BYTES

◆ IWM_AGG_TX_STATE_LAST_SENT_BT_KILL

◆ IWM_AGG_TX_STATE_LAST_SENT_MSK

◆ IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT

◆ IWM_AGG_TX_STATE_LAST_SENT_TTL

◆ IWM_AGG_TX_STATE_RESPONSE

◆ IWM_AGG_TX_STATE_SCD_QUERY

◆ IWM_AGG_TX_STATE_STATUS_MSK

◆ IWM_AGG_TX_STATE_TEST_BAD_CRC32

◆ IWM_AGG_TX_STATE_TRANSMITTED

◆ IWM_AGG_TX_STATE_TRY_CNT_MSK

◆ IWM_AGG_TX_STATE_TRY_CNT_POS

◆ IWM_AGG_TX_STATE_UNDERRUN

◆ IWM_ALIVE

◆ IWM_ALIVE_FLG_RFKILL

◆ IWM_ALIVE_RESP_RFKILL

◆ IWM_ALIVE_RESP_UCODE_OK

◆ IWM_ALIVE_STATUS_ERR

◆ IWM_ALIVE_STATUS_OK

◆ IWM_ALWAYS_LONG_GROUP

◆ IWM_ANT_A

◆ IWM_ANT_AB

◆ IWM_ANT_ABC

◆ IWM_ANT_B

◆ IWM_ANT_BC

◆ IWM_ANT_C

◆ IWM_APMG_ANALOG_SVR_REG

◆ IWM_APMG_BASE

◆ IWM_APMG_CLK_CTRL_REG

◆ IWM_APMG_CLK_DIS_REG

◆ IWM_APMG_CLK_EN_REG

◆ IWM_APMG_CLK_VAL_BSM_CLK_RQT

◆ IWM_APMG_CLK_VAL_DMA_CLK_RQT

◆ IWM_APMG_DIGITAL_SVR_REG

◆ IWM_APMG_PCIDEV_STT_REG

◆ IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS

◆ IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS

◆ IWM_APMG_PS_CTRL_MSK_PWR_SRC

◆ IWM_APMG_PS_CTRL_REG

◆ IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX

◆ IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN

◆ IWM_APMG_PS_CTRL_VAL_RESET_REQ

◆ IWM_APMG_RFKILL_REG

◆ IWM_APMG_RTC_INT_MSK_REG

◆ IWM_APMG_RTC_INT_STT_REG

◆ IWM_APMG_RTC_INT_STT_RFKILL

◆ IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32

◆ IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK

◆ IWM_APMS_CLK_VAL_MRB_FUNC_MODE

◆ IWM_AUX_BINDING_INDEX

◆ IWM_AUX_MISC_MASTER1_EN

◆ IWM_AUX_MISC_MASTER1_EN_SBE_MSK

◆ IWM_AUX_MISC_MASTER1_SMPHR_STATUS

◆ IWM_AUX_MISC_REG