31#define AXGE_ACCESS_MAC 0x01
32#define AXGE_ACCESS_PHY 0x02
33#define AXGE_ACCESS_WAKEUP 0x03
34#define AXGE_ACCESS_EEPROM 0x04
35#define AXGE_ACCESS_EFUSE 0x05
36#define AXGE_RELOAD_EEPROM_EFUSE 0x06
37#define AXGE_WRITE_EFUSE_EN 0x09
38#define AXGE_WRITE_EFUSE_DIS 0x0A
39#define AXGE_ACCESS_MFAB 0x10
43#define PLSR_USB_FS 0x01
44#define PLSR_USB_HS 0x02
45#define PLSR_USB_SS 0x04
61#define RCR_STOP 0x0000
62#define RCR_PROMISC 0x0001
63#define RCR_ACPT_ALL_MCAST 0x0002
64#define RCR_AUTOPAD_BNDRY 0x0004
65#define RCR_ACPT_BCAST 0x0008
66#define RCR_ACPT_MCAST 0x0010
67#define RCR_ACPT_PHY_MCAST 0x0020
68#define RCR_START 0x0080
69#define RCR_DROP_CRCERR 0x0100
71#define RCR_TX_CRC_PAD 0x0400
83#define MSR_EN_125MHZ 0x0008
94#define MMSR_RW_FLAG 0x10
95#define MMSR_PME_POL 0x20
96#define MMSR_PME_TYPE 0x40
97#define MMSR_PME_IND 0x80
100#define AXGE_GPIOCR 0x25
103#define AXGE_EPPRCR 0x26
104#define EPPRCR_BZ 0x0010
105#define EPPRCR_IPRL 0x0020
106#define EPPRCR_AUTODETACH 0x1000
108#define AXGE_RX_BULKIN_QCTRL 0x2e
110#define AXGE_CLK_SELECT 0x33
111#define AXGE_CLK_SELECT_BCS 0x01
112#define AXGE_CLK_SELECT_ACS 0x02
113#define AXGE_CLK_SELECT_ACSREQ 0x10
114#define AXGE_CLK_SELECT_ULR 0x08
117#define AXGE_CRCR 0x34
121#define CRCR_ICMP 0x08
122#define CRCR_IGMP 0x10
123#define CRCR_TCPV6 0x20
124#define CRCR_UDPV6 0x40
125#define CRCR_ICMPV6 0x80
128#define AXGE_CTCR 0x35
132#define CTCR_ICMP 0x08
133#define CTCR_IGMP 0x10
134#define CTCR_TCPV6 0x20
135#define CTCR_UDPV6 0x40
136#define CTCR_ICMPV6 0x80
139#define AXGE_PWLHR 0x54
142#define AXGE_PWLLR 0x55
144#define AXGE_CONFIG_IDX 0
145#define AXGE_IFACE_IDX 0
147#define GET_MII(sc) uether_getmii(&(sc)->sc_ue)
156#define AXGE_N_FRAMES 16
160#define AXGE_TXLEN_MASK 0x0001FFFF
161#define AXGE_VLAN_INSERT 0x20000000
162#define AXGE_CSUM_DISABLE 0x80000000
164#define AXGE_MSS_MASK 0x00003FFF
165#define AXGE_PADDING 0x80008000
166#define AXGE_VLAN_TAG_MASK 0xFFFF0000
169#define AXGE_TXBYTES(x) ((x) & AXGE_TXLEN_MASK)
171#define AXGE_PHY_ADDR 3
175#define AXGE_RX_L4_CSUM_ERR 0x00000001
176#define AXGE_RX_L3_CSUM_ERR 0x00000002
177#define AXGE_RX_L4_TYPE_UDP 0x00000004
178#define AXGE_RX_L4_TYPE_ICMP 0x00000008
179#define AXGE_RX_L4_TYPE_IGMP 0x0000000C
180#define AXGE_RX_L4_TYPE_TCP 0x00000010
181#define AXGE_RX_L4_TYPE_MASK 0x0000001C
182#define AXGE_RX_L3_TYPE_IPV4 0x00000020
183#define AXGE_RX_L3_TYPE_IPV6 0x00000040
184#define AXGE_RX_L3_TYPE_MASK 0x00000060
185#define AXGE_RX_VLAN_IND_MASK 0x00000700
186#define AXGE_RX_GOOD_PKT 0x00000800
187#define AXGE_RX_VLAN_PRI_MASK 0x00007000
188#define AXGE_RX_MBCAST 0x00008000
189#define AXGE_RX_LEN_MASK 0x1FFF0000
190#define AXGE_RX_CRC_ERR 0x20000000
191#define AXGE_RX_MII_ERR 0x40000000
192#define AXGE_RX_DROP_PKT 0x80000000
193#define AXGE_RX_LEN_SHIFT 16
196#define AXGE_RXBYTES(x) (((x) & AXGE_RX_LEN_MASK) >> AXGE_RX_LEN_SHIFT)
197#define AXGE_RX_ERR(x) \
198 ((x) & (AXGE_RX_CRC_ERR | AXGE_RX_MII_ERR | AXGE_RX_DROP_PKT))
206#define AXGE_FLAG_LINK 0x0001
209#define AXGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
210#define AXGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
211#define AXGE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t)
struct axge_frame_txhdr __packed
struct usb_xfer * sc_xfer[AXGE_N_TRANSFER]