FreeBSD kernel sound device code
hda_reg.h
Go to the documentation of this file.
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _HDA_REG_H_
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#define _HDA_REG_H_
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/****************************************************************************
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* HDA Device Verbs
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****************************************************************************/
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/* HDA Command */
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#define HDA_CMD_VERB_MASK 0x000fffff
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#define HDA_CMD_VERB_SHIFT 0
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#define HDA_CMD_NID_MASK 0x0ff00000
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#define HDA_CMD_NID_SHIFT 20
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#define HDA_CMD_CAD_MASK 0xf0000000
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#define HDA_CMD_CAD_SHIFT 28
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#define HDA_CMD_VERB_4BIT_SHIFT 16
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#define HDA_CMD_VERB_12BIT_SHIFT 8
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#define HDA_CMD_VERB_4BIT(verb, payload) \
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(((verb) << HDA_CMD_VERB_4BIT_SHIFT) | (payload))
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#define HDA_CMD_4BIT(cad, nid, verb, payload) \
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(((cad) << HDA_CMD_CAD_SHIFT) | \
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((nid) << HDA_CMD_NID_SHIFT) | \
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(HDA_CMD_VERB_4BIT((verb), (payload))))
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#define HDA_CMD_VERB_12BIT(verb, payload) \
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(((verb) << HDA_CMD_VERB_12BIT_SHIFT) | (payload))
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#define HDA_CMD_12BIT(cad, nid, verb, payload) \
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(((cad) << HDA_CMD_CAD_SHIFT) | \
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((nid) << HDA_CMD_NID_SHIFT) | \
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(HDA_CMD_VERB_12BIT((verb), (payload))))
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/* Get Parameter */
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#define HDA_CMD_VERB_GET_PARAMETER 0xf00
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#define HDA_CMD_GET_PARAMETER(cad, nid, payload) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_GET_PARAMETER, (payload)))
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/* Connection Select Control */
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#define HDA_CMD_VERB_GET_CONN_SELECT_CONTROL 0xf01
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#define HDA_CMD_VERB_SET_CONN_SELECT_CONTROL 0x701
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#define HDA_CMD_GET_CONN_SELECT_CONTROL(cad, nid) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_GET_CONN_SELECT_CONTROL, 0x0))
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#define HDA_CMD_SET_CONNECTION_SELECT_CONTROL(cad, nid, payload) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_SET_CONN_SELECT_CONTROL, (payload)))
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/* Connection List Entry */
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#define HDA_CMD_VERB_GET_CONN_LIST_ENTRY 0xf02
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#define HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, payload) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_GET_CONN_LIST_ENTRY, (payload)))
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#define HDA_CMD_GET_CONN_LIST_ENTRY_SIZE_SHORT 1
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#define HDA_CMD_GET_CONN_LIST_ENTRY_SIZE_LONG 2
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/* Processing State */
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#define HDA_CMD_VERB_GET_PROCESSING_STATE 0xf03
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#define HDA_CMD_VERB_SET_PROCESSING_STATE 0x703
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#define HDA_CMD_GET_PROCESSING_STATE(cad, nid) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_GET_PROCESSING_STATE, 0x0))
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#define HDA_CMD_SET_PROCESSING_STATE(cad, nid, payload) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_SET_PROCESSING_STATE, (payload)))
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#define HDA_CMD_GET_PROCESSING_STATE_STATE_OFF 0x00
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#define HDA_CMD_GET_PROCESSING_STATE_STATE_ON 0x01
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#define HDA_CMD_GET_PROCESSING_STATE_STATE_BENIGN 0x02
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/* Coefficient Index */
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#define HDA_CMD_VERB_GET_COEFF_INDEX 0xd
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#define HDA_CMD_VERB_SET_COEFF_INDEX 0x5
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#define HDA_CMD_GET_COEFF_INDEX(cad, nid) \
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(HDA_CMD_4BIT((cad), (nid), \
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HDA_CMD_VERB_GET_COEFF_INDEX, 0x0))
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#define HDA_CMD_SET_COEFF_INDEX(cad, nid, payload) \
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(HDA_CMD_4BIT((cad), (nid), \
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HDA_CMD_VERB_SET_COEFF_INDEX, (payload)))
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/* Processing Coefficient */
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#define HDA_CMD_VERB_GET_PROCESSING_COEFF 0xc
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#define HDA_CMD_VERB_SET_PROCESSING_COEFF 0x4
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#define HDA_CMD_GET_PROCESSING_COEFF(cad, nid) \
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(HDA_CMD_4BIT((cad), (nid), \
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HDA_CMD_VERB_GET_PROCESSING_COEFF, 0x0))
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#define HDA_CMD_SET_PROCESSING_COEFF(cad, nid, payload) \
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(HDA_CMD_4BIT((cad), (nid), \
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HDA_CMD_VERB_SET_PROCESSING_COEFF, (payload)))
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/* Amplifier Gain/Mute */
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#define HDA_CMD_VERB_GET_AMP_GAIN_MUTE 0xb
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#define HDA_CMD_VERB_SET_AMP_GAIN_MUTE 0x3
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#define HDA_CMD_GET_AMP_GAIN_MUTE(cad, nid, payload) \
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(HDA_CMD_4BIT((cad), (nid), \
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HDA_CMD_VERB_GET_AMP_GAIN_MUTE, (payload)))
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#define HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, payload) \
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(HDA_CMD_4BIT((cad), (nid), \
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HDA_CMD_VERB_SET_AMP_GAIN_MUTE, (payload)))
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#define HDA_CMD_GET_AMP_GAIN_MUTE_INPUT 0x0000
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#define HDA_CMD_GET_AMP_GAIN_MUTE_OUTPUT 0x8000
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#define HDA_CMD_GET_AMP_GAIN_MUTE_RIGHT 0x0000
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#define HDA_CMD_GET_AMP_GAIN_MUTE_LEFT 0x2000
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#define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK 0x00000008
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#define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_SHIFT 7
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#define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK 0x00000007
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#define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT 0
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#define HDA_CMD_GET_AMP_GAIN_MUTE_MUTE(rsp) \
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(((rsp) & HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_MASK) >> \
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HDA_CMD_GET_AMP_GAIN_MUTE_MUTE_SHIFT)
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#define HDA_CMD_GET_AMP_GAIN_MUTE_GAIN(rsp) \
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(((rsp) & HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_MASK) >> \
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HDA_CMD_GET_AMP_GAIN_MUTE_GAIN_SHIFT)
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#define HDA_CMD_SET_AMP_GAIN_MUTE_OUTPUT 0x8000
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#define HDA_CMD_SET_AMP_GAIN_MUTE_INPUT 0x4000
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#define HDA_CMD_SET_AMP_GAIN_MUTE_LEFT 0x2000
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#define HDA_CMD_SET_AMP_GAIN_MUTE_RIGHT 0x1000
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#define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK 0x0f00
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#define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_SHIFT 8
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#define HDA_CMD_SET_AMP_GAIN_MUTE_MUTE 0x0080
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#define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK 0x0007
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#define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT 0
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#define HDA_CMD_SET_AMP_GAIN_MUTE_INDEX(index) \
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(((index) << HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_SHIFT) & \
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HDA_CMD_SET_AMP_GAIN_MUTE_INDEX_MASK)
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#define HDA_CMD_SET_AMP_GAIN_MUTE_GAIN(index) \
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(((index) << HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_SHIFT) & \
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HDA_CMD_SET_AMP_GAIN_MUTE_GAIN_MASK)
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/* Converter format */
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#define HDA_CMD_VERB_GET_CONV_FMT 0xa
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#define HDA_CMD_VERB_SET_CONV_FMT 0x2
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#define HDA_CMD_GET_CONV_FMT(cad, nid) \
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(HDA_CMD_4BIT((cad), (nid), \
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HDA_CMD_VERB_GET_CONV_FMT, 0x0))
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#define HDA_CMD_SET_CONV_FMT(cad, nid, payload) \
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(HDA_CMD_4BIT((cad), (nid), \
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HDA_CMD_VERB_SET_CONV_FMT, (payload)))
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/* Digital Converter Control */
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#define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT1 0xf0d
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#define HDA_CMD_VERB_GET_DIGITAL_CONV_FMT2 0xf0e
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#define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1 0x70d
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#define HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2 0x70e
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#define HDA_CMD_GET_DIGITAL_CONV_FMT(cad, nid) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_GET_DIGITAL_CONV_FMT1, 0x0))
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#define HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, nid, payload) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_SET_DIGITAL_CONV_FMT1, (payload)))
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#define HDA_CMD_SET_DIGITAL_CONV_FMT2(cad, nid, payload) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_SET_DIGITAL_CONV_FMT2, (payload)))
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK 0x7f00
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_CC_SHIFT 8
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK 0x0080
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_L_SHIFT 7
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK 0x0040
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_SHIFT 6
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK 0x0020
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_SHIFT 5
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK 0x0010
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_SHIFT 4
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK 0x0008
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_SHIFT 3
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK 0x0004
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_SHIFT 2
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK 0x0002
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_V_SHIFT 1
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK 0x0001
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT 0
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_CC(rsp) \
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(((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_CC_MASK) >> \
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HDA_CMD_GET_DIGITAL_CONV_FMT_CC_SHIFT)
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_L(rsp) \
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(((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_L_MASK) >> \
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HDA_CMD_GET_DIGITAL_CONV_FMT_L_SHIFT)
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRO(rsp) \
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(((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_MASK) >> \
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HDA_CMD_GET_DIGITAL_CONV_FMT_PRO_SHIFT)
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO(rsp) \
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(((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_MASK) >> \
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HDA_CMD_GET_DIGITAL_CONV_FMT_NAUDIO_SHIFT)
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_COPY(rsp) \
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(((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_MASK) >> \
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HDA_CMD_GET_DIGITAL_CONV_FMT_COPY_SHIFT)
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_PRE(rsp) \
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(((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_MASK) >> \
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HDA_CMD_GET_DIGITAL_CONV_FMT_PRE_SHIFT)
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG(rsp) \
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(((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_MASK) >> \
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HDA_CMD_GET_DIGITAL_CONV_FMT_VCFG_SHIFT)
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_V(rsp) \
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(((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_V_MASK) >> \
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HDA_CMD_GET_DIGITAL_CONV_FMT_V_SHIFT)
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#define HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN(rsp) \
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(((rsp) & HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_MASK) >> \
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HDA_CMD_GET_DIGITAL_CONV_FMT_DIGEN_SHIFT)
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#define HDA_CMD_SET_DIGITAL_CONV_FMT1_L 0x80
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#define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRO 0x40
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#define HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO 0x20
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#define HDA_CMD_SET_DIGITAL_CONV_FMT1_COPY 0x10
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#define HDA_CMD_SET_DIGITAL_CONV_FMT1_PRE 0x08
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#define HDA_CMD_SET_DIGITAL_CONV_FMT1_VCFG 0x04
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#define HDA_CMD_SET_DIGITAL_CONV_FMT1_V 0x02
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#define HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN 0x01
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/* Power State */
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#define HDA_CMD_VERB_GET_POWER_STATE 0xf05
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#define HDA_CMD_VERB_SET_POWER_STATE 0x705
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#define HDA_CMD_GET_POWER_STATE(cad, nid) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_GET_POWER_STATE, 0x0))
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#define HDA_CMD_SET_POWER_STATE(cad, nid, payload) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_SET_POWER_STATE, (payload)))
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#define HDA_CMD_POWER_STATE_D0 0x00
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#define HDA_CMD_POWER_STATE_D1 0x01
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#define HDA_CMD_POWER_STATE_D2 0x02
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#define HDA_CMD_POWER_STATE_D3 0x03
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#define HDA_CMD_POWER_STATE_ACT_MASK 0x000000f0
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#define HDA_CMD_POWER_STATE_ACT_SHIFT 4
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#define HDA_CMD_POWER_STATE_SET_MASK 0x0000000f
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#define HDA_CMD_POWER_STATE_SET_SHIFT 0
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#define HDA_CMD_GET_POWER_STATE_ACT(rsp) \
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(((rsp) & HDA_CMD_POWER_STATE_ACT_MASK) >> \
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HDA_CMD_POWER_STATE_ACT_SHIFT)
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#define HDA_CMD_GET_POWER_STATE_SET(rsp) \
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(((rsp) & HDA_CMD_POWER_STATE_SET_MASK) >> \
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HDA_CMD_POWER_STATE_SET_SHIFT)
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#define HDA_CMD_SET_POWER_STATE_ACT(ps) \
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(((ps) << HDA_CMD_POWER_STATE_ACT_SHIFT) & \
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HDA_CMD_POWER_STATE_ACT_MASK)
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#define HDA_CMD_SET_POWER_STATE_SET(ps) \
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(((ps) << HDA_CMD_POWER_STATE_SET_SHIFT) & \
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HDA_CMD_POWER_STATE_ACT_MASK)
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/* Converter Stream, Channel */
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#define HDA_CMD_VERB_GET_CONV_STREAM_CHAN 0xf06
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#define HDA_CMD_VERB_SET_CONV_STREAM_CHAN 0x706
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#define HDA_CMD_GET_CONV_STREAM_CHAN(cad, nid) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_GET_CONV_STREAM_CHAN, 0x0))
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#define HDA_CMD_SET_CONV_STREAM_CHAN(cad, nid, payload) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_SET_CONV_STREAM_CHAN, (payload)))
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#define HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK 0x000000f0
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#define HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT 4
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#define HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK 0x0000000f
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#define HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT 0
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#define HDA_CMD_GET_CONV_STREAM_CHAN_STREAM(rsp) \
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(((rsp) & HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK) >> \
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HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT)
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#define HDA_CMD_GET_CONV_STREAM_CHAN_CHAN(rsp) \
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(((rsp) & HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK) >> \
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HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT)
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#define HDA_CMD_SET_CONV_STREAM_CHAN_STREAM(param) \
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(((param) << HDA_CMD_CONV_STREAM_CHAN_STREAM_SHIFT) & \
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HDA_CMD_CONV_STREAM_CHAN_STREAM_MASK)
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#define HDA_CMD_SET_CONV_STREAM_CHAN_CHAN(param) \
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(((param) << HDA_CMD_CONV_STREAM_CHAN_CHAN_SHIFT) & \
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HDA_CMD_CONV_STREAM_CHAN_CHAN_MASK)
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/* Input Converter SDI Select */
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#define HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT 0xf04
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#define HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT 0x704
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#define HDA_CMD_GET_INPUT_CONVERTER_SDI_SELECT(cad, nid) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_GET_INPUT_CONVERTER_SDI_SELECT, 0x0))
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#define HDA_CMD_SET_INPUT_CONVERTER_SDI_SELECT(cad, nid, payload) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_SET_INPUT_CONVERTER_SDI_SELECT, (payload)))
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/* Pin Widget Control */
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#define HDA_CMD_VERB_GET_PIN_WIDGET_CTRL 0xf07
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#define HDA_CMD_VERB_SET_PIN_WIDGET_CTRL 0x707
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#define HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_GET_PIN_WIDGET_CTRL, 0x0))
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#define HDA_CMD_SET_PIN_WIDGET_CTRL(cad, nid, payload) \
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(HDA_CMD_12BIT((cad), (nid), \
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HDA_CMD_VERB_SET_PIN_WIDGET_CTRL, (payload)))
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#define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK 0x00000080
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#define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_SHIFT 7
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#define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK 0x00000040
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#define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT 6
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#define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK 0x00000020
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#define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT 5
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#define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x00000007
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#define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0
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#define HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE(rsp) \
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(((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_MASK) >> \
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HDA_CMD_GET_PIN_WIDGET_CTRL_HPHN_ENABLE_SHIFT)
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#define HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE(rsp) \
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(((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_OUT_ENABLE_MASK) >> \
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HDA_GET_CMD_PIN_WIDGET_CTRL_OUT_ENABLE_SHIFT)
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#define HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE(rsp) \
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(((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_MASK) >> \
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HDA_CMD_GET_PIN_WIDGET_CTRL_IN_ENABLE_SHIFT)
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#define HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE(rsp) \
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(((rsp) & HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) >> \
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HDA_CMD_GET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT)
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#define HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE 0x80
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#define HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE 0x40
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#define HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE 0x20
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#define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK 0x07
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#define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT 0
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#define HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(param) \
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(((param) << HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_SHIFT) & \
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HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK)
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#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_HIZ 0
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#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50 1
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#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_GROUND 2
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#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80 4
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#define HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100 5
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/* Unsolicited Response */
382
#define HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE 0xf08
383
#define HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE 0x708
384
385
#define HDA_CMD_GET_UNSOLICITED_RESPONSE(cad, nid) \
386
(HDA_CMD_12BIT((cad), (nid), \
387
HDA_CMD_VERB_GET_UNSOLICITED_RESPONSE, 0x0))
388
#define HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, nid, payload) \
389
(HDA_CMD_12BIT((cad), (nid), \
390
HDA_CMD_VERB_SET_UNSOLICITED_RESPONSE, (payload)))
391
392
#define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK 0x00000080
393
#define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_SHIFT 7
394
#define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK 0x0000001f
395
#define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT 0
396
397
#define HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE(rsp) \
398
(((rsp) & HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_MASK) >> \
399
HDA_CMD_GET_UNSOLICITED_RESPONSE_ENABLE_SHIFT)
400
#define HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG(rsp) \
401
(((rsp) & HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_MASK) >> \
402
HDA_CMD_GET_UNSOLICITED_RESPONSE_TAG_SHIFT)
403
404
#define HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE 0x80
405
#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK 0x3f
406
#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT 0
407
408
#define HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG(param) \
409
(((param) << HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_SHIFT) & \
410
HDA_CMD_SET_UNSOLICITED_RESPONSE_TAG_MASK)
411
412
/* Pin Sense */
413
#define HDA_CMD_VERB_GET_PIN_SENSE 0xf09
414
#define HDA_CMD_VERB_SET_PIN_SENSE 0x709
415
416
#define HDA_CMD_GET_PIN_SENSE(cad, nid) \
417
(HDA_CMD_12BIT((cad), (nid), \
418
HDA_CMD_VERB_GET_PIN_SENSE, 0x0))
419
#define HDA_CMD_SET_PIN_SENSE(cad, nid, payload) \
420
(HDA_CMD_12BIT((cad), (nid), \
421
HDA_CMD_VERB_SET_PIN_SENSE, (payload)))
422
423
#define HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT 0x80000000
424
#define HDA_CMD_GET_PIN_SENSE_ELD_VALID 0x40000000
425
#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK 0x7fffffff
426
#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT 0
427
428
#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE(rsp) \
429
(((rsp) & HDA_CMD_GET_PIN_SENSE_IMP_SENSE_MASK) >> \
430
HDA_CMD_GET_PIN_SENSE_IMP_SENSE_SHIFT)
431
432
#define HDA_CMD_GET_PIN_SENSE_IMP_SENSE_INVALID 0x7fffffff
433
434
#define HDA_CMD_SET_PIN_SENSE_LEFT_CHANNEL 0x00
435
#define HDA_CMD_SET_PIN_SENSE_RIGHT_CHANNEL 0x01
436
437
/* EAPD/BTL Enable */
438
#define HDA_CMD_VERB_GET_EAPD_BTL_ENABLE 0xf0c
439
#define HDA_CMD_VERB_SET_EAPD_BTL_ENABLE 0x70c
440
441
#define HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid) \
442
(HDA_CMD_12BIT((cad), (nid), \
443
HDA_CMD_VERB_GET_EAPD_BTL_ENABLE, 0x0))
444
#define HDA_CMD_SET_EAPD_BTL_ENABLE(cad, nid, payload) \
445
(HDA_CMD_12BIT((cad), (nid), \
446
HDA_CMD_VERB_SET_EAPD_BTL_ENABLE, (payload)))
447
448
#define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK 0x00000004
449
#define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_SHIFT 2
450
#define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK 0x00000002
451
#define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_SHIFT 1
452
#define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK 0x00000001
453
#define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT 0
454
455
#define HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP(rsp) \
456
(((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_MASK) >> \
457
HDA_CMD_GET_EAPD_BTL_ENABLE_LR_SWAP_SHIFT)
458
#define HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD(rsp) \
459
(((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_MASK) >> \
460
HDA_CMD_GET_EAPD_BTL_ENABLE_EAPD_SHIFT)
461
#define HDA_CMD_GET_EAPD_BTL_ENABLE_BTL(rsp) \
462
(((rsp) & HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_MASK) >> \
463
HDA_CMD_GET_EAPD_BTL_ENABLE_BTL_SHIFT)
464
465
#define HDA_CMD_SET_EAPD_BTL_ENABLE_LR_SWAP 0x04
466
#define HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD 0x02
467
#define HDA_CMD_SET_EAPD_BTL_ENABLE_BTL 0x01
468
469
/* GPI Data */
470
#define HDA_CMD_VERB_GET_GPI_DATA 0xf10
471
#define HDA_CMD_VERB_SET_GPI_DATA 0x710
472
473
#define HDA_CMD_GET_GPI_DATA(cad, nid) \
474
(HDA_CMD_12BIT((cad), (nid), \
475
HDA_CMD_VERB_GET_GPI_DATA, 0x0))
476
#define HDA_CMD_SET_GPI_DATA(cad, nid) \
477
(HDA_CMD_12BIT((cad), (nid), \
478
HDA_CMD_VERB_SET_GPI_DATA, (payload)))
479
480
/* GPI Wake Enable Mask */
481
#define HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK 0xf11
482
#define HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK 0x711
483
484
#define HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, nid) \
485
(HDA_CMD_12BIT((cad), (nid), \
486
HDA_CMD_VERB_GET_GPI_WAKE_ENABLE_MASK, 0x0))
487
#define HDA_CMD_SET_GPI_WAKE_ENABLE_MASK(cad, nid, payload) \
488
(HDA_CMD_12BIT((cad), (nid), \
489
HDA_CMD_VERB_SET_GPI_WAKE_ENABLE_MASK, (payload)))
490
491
/* GPI Unsolicited Enable Mask */
492
#define HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK 0xf12
493
#define HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK 0x712
494
495
#define HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid) \
496
(HDA_CMD_12BIT((cad), (nid), \
497
HDA_CMD_VERB_GET_GPI_UNSOLICITED_ENABLE_MASK, 0x0))
498
#define HDA_CMD_SET_GPI_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \
499
(HDA_CMD_12BIT((cad), (nid), \
500
HDA_CMD_VERB_SET_GPI_UNSOLICITED_ENABLE_MASK, (payload)))
501
502
/* GPI Sticky Mask */
503
#define HDA_CMD_VERB_GET_GPI_STICKY_MASK 0xf13
504
#define HDA_CMD_VERB_SET_GPI_STICKY_MASK 0x713
505
506
#define HDA_CMD_GET_GPI_STICKY_MASK(cad, nid) \
507
(HDA_CMD_12BIT((cad), (nid), \
508
HDA_CMD_VERB_GET_GPI_STICKY_MASK, 0x0))
509
#define HDA_CMD_SET_GPI_STICKY_MASK(cad, nid, payload) \
510
(HDA_CMD_12BIT((cad), (nid), \
511
HDA_CMD_VERB_SET_GPI_STICKY_MASK, (payload)))
512
513
/* GPO Data */
514
#define HDA_CMD_VERB_GET_GPO_DATA 0xf14
515
#define HDA_CMD_VERB_SET_GPO_DATA 0x714
516
517
#define HDA_CMD_GET_GPO_DATA(cad, nid) \
518
(HDA_CMD_12BIT((cad), (nid), \
519
HDA_CMD_VERB_GET_GPO_DATA, 0x0))
520
#define HDA_CMD_SET_GPO_DATA(cad, nid, payload) \
521
(HDA_CMD_12BIT((cad), (nid), \
522
HDA_CMD_VERB_SET_GPO_DATA, (payload)))
523
524
/* GPIO Data */
525
#define HDA_CMD_VERB_GET_GPIO_DATA 0xf15
526
#define HDA_CMD_VERB_SET_GPIO_DATA 0x715
527
528
#define HDA_CMD_GET_GPIO_DATA(cad, nid) \
529
(HDA_CMD_12BIT((cad), (nid), \
530
HDA_CMD_VERB_GET_GPIO_DATA, 0x0))
531
#define HDA_CMD_SET_GPIO_DATA(cad, nid, payload) \
532
(HDA_CMD_12BIT((cad), (nid), \
533
HDA_CMD_VERB_SET_GPIO_DATA, (payload)))
534
535
/* GPIO Enable Mask */
536
#define HDA_CMD_VERB_GET_GPIO_ENABLE_MASK 0xf16
537
#define HDA_CMD_VERB_SET_GPIO_ENABLE_MASK 0x716
538
539
#define HDA_CMD_GET_GPIO_ENABLE_MASK(cad, nid) \
540
(HDA_CMD_12BIT((cad), (nid), \
541
HDA_CMD_VERB_GET_GPIO_ENABLE_MASK, 0x0))
542
#define HDA_CMD_SET_GPIO_ENABLE_MASK(cad, nid, payload) \
543
(HDA_CMD_12BIT((cad), (nid), \
544
HDA_CMD_VERB_SET_GPIO_ENABLE_MASK, (payload)))
545
546
/* GPIO Direction */
547
#define HDA_CMD_VERB_GET_GPIO_DIRECTION 0xf17
548
#define HDA_CMD_VERB_SET_GPIO_DIRECTION 0x717
549
550
#define HDA_CMD_GET_GPIO_DIRECTION(cad, nid) \
551
(HDA_CMD_12BIT((cad), (nid), \
552
HDA_CMD_VERB_GET_GPIO_DIRECTION, 0x0))
553
#define HDA_CMD_SET_GPIO_DIRECTION(cad, nid, payload) \
554
(HDA_CMD_12BIT((cad), (nid), \
555
HDA_CMD_VERB_SET_GPIO_DIRECTION, (payload)))
556
557
/* GPIO Wake Enable Mask */
558
#define HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK 0xf18
559
#define HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK 0x718
560
561
#define HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, nid) \
562
(HDA_CMD_12BIT((cad), (nid), \
563
HDA_CMD_VERB_GET_GPIO_WAKE_ENABLE_MASK, 0x0))
564
#define HDA_CMD_SET_GPIO_WAKE_ENABLE_MASK(cad, nid, payload) \
565
(HDA_CMD_12BIT((cad), (nid), \
566
HDA_CMD_VERB_SET_GPIO_WAKE_ENABLE_MASK, (payload)))
567
568
/* GPIO Unsolicited Enable Mask */
569
#define HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK 0xf19
570
#define HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK 0x719
571
572
#define HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid) \
573
(HDA_CMD_12BIT((cad), (nid), \
574
HDA_CMD_VERB_GET_GPIO_UNSOLICITED_ENABLE_MASK, 0x0))
575
#define HDA_CMD_SET_GPIO_UNSOLICITED_ENABLE_MASK(cad, nid, payload) \
576
(HDA_CMD_12BIT((cad), (nid), \
577
HDA_CMD_VERB_SET_GPIO_UNSOLICITED_ENABLE_MASK, (payload)))
578
579
/* GPIO_STICKY_MASK */
580
#define HDA_CMD_VERB_GET_GPIO_STICKY_MASK 0xf1a
581
#define HDA_CMD_VERB_SET_GPIO_STICKY_MASK 0x71a
582
583
#define HDA_CMD_GET_GPIO_STICKY_MASK(cad, nid) \
584
(HDA_CMD_12BIT((cad), (nid), \
585
HDA_CMD_VERB_GET_GPIO_STICKY_MASK, 0x0))
586
#define HDA_CMD_SET_GPIO_STICKY_MASK(cad, nid, payload) \
587
(HDA_CMD_12BIT((cad), (nid), \
588
HDA_CMD_VERB_SET_GPIO_STICKY_MASK, (payload)))
589
590
/* Beep Generation */
591
#define HDA_CMD_VERB_GET_BEEP_GENERATION 0xf0a
592
#define HDA_CMD_VERB_SET_BEEP_GENERATION 0x70a
593
594
#define HDA_CMD_GET_BEEP_GENERATION(cad, nid) \
595
(HDA_CMD_12BIT((cad), (nid), \
596
HDA_CMD_VERB_GET_BEEP_GENERATION, 0x0))
597
#define HDA_CMD_SET_BEEP_GENERATION(cad, nid, payload) \
598
(HDA_CMD_12BIT((cad), (nid), \
599
HDA_CMD_VERB_SET_BEEP_GENERATION, (payload)))
600
601
/* Volume Knob */
602
#define HDA_CMD_VERB_GET_VOLUME_KNOB 0xf0f
603
#define HDA_CMD_VERB_SET_VOLUME_KNOB 0x70f
604
605
#define HDA_CMD_GET_VOLUME_KNOB(cad, nid) \
606
(HDA_CMD_12BIT((cad), (nid), \
607
HDA_CMD_VERB_GET_VOLUME_KNOB, 0x0))
608
#define HDA_CMD_SET_VOLUME_KNOB(cad, nid, payload) \
609
(HDA_CMD_12BIT((cad), (nid), \
610
HDA_CMD_VERB_SET_VOLUME_KNOB, (payload)))
611
612
/* Subsystem ID */
613
#define HDA_CMD_VERB_GET_SUBSYSTEM_ID 0xf20
614
#define HDA_CMD_VERB_SET_SUSBYSTEM_ID1 0x720
615
#define HDA_CMD_VERB_SET_SUBSYSTEM_ID2 0x721
616
#define HDA_CMD_VERB_SET_SUBSYSTEM_ID3 0x722
617
#define HDA_CMD_VERB_SET_SUBSYSTEM_ID4 0x723
618
619
#define HDA_CMD_GET_SUBSYSTEM_ID(cad, nid) \
620
(HDA_CMD_12BIT((cad), (nid), \
621
HDA_CMD_VERB_GET_SUBSYSTEM_ID, 0x0))
622
#define HDA_CMD_SET_SUBSYSTEM_ID1(cad, nid, payload) \
623
(HDA_CMD_12BIT((cad), (nid), \
624
HDA_CMD_VERB_SET_SUSBYSTEM_ID1, (payload)))
625
#define HDA_CMD_SET_SUBSYSTEM_ID2(cad, nid, payload) \
626
(HDA_CMD_12BIT((cad), (nid), \
627
HDA_CMD_VERB_SET_SUSBYSTEM_ID2, (payload)))
628
#define HDA_CMD_SET_SUBSYSTEM_ID3(cad, nid, payload) \
629
(HDA_CMD_12BIT((cad), (nid), \
630
HDA_CMD_VERB_SET_SUSBYSTEM_ID3, (payload)))
631
#define HDA_CMD_SET_SUBSYSTEM_ID4(cad, nid, payload) \
632
(HDA_CMD_12BIT((cad), (nid), \
633
HDA_CMD_VERB_SET_SUSBYSTEM_ID4, (payload)))
634
635
/* Configuration Default */
636
#define HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT 0xf1c
637
#define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1 0x71c
638
#define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2 0x71d
639
#define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3 0x71e
640
#define HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4 0x71f
641
642
#define HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid) \
643
(HDA_CMD_12BIT((cad), (nid), \
644
HDA_CMD_VERB_GET_CONFIGURATION_DEFAULT, 0x0))
645
#define HDA_CMD_SET_CONFIGURATION_DEFAULT1(cad, nid, payload) \
646
(HDA_CMD_12BIT((cad), (nid), \
647
HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT1, (payload)))
648
#define HDA_CMD_SET_CONFIGURATION_DEFAULT2(cad, nid, payload) \
649
(HDA_CMD_12BIT((cad), (nid), \
650
HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT2, (payload)))
651
#define HDA_CMD_SET_CONFIGURATION_DEFAULT3(cad, nid, payload) \
652
(HDA_CMD_12BIT((cad), (nid), \
653
HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT3, (payload)))
654
#define HDA_CMD_SET_CONFIGURATION_DEFAULT4(cad, nid, payload) \
655
(HDA_CMD_12BIT((cad), (nid), \
656
HDA_CMD_VERB_SET_CONFIGURATION_DEFAULT4, (payload)))
657
658
/* Stripe Control */
659
#define HDA_CMD_VERB_GET_STRIPE_CONTROL 0xf24
660
#define HDA_CMD_VERB_SET_STRIPE_CONTROL 0x724
661
662
#define HDA_CMD_GET_STRIPE_CONTROL(cad, nid) \
663
(HDA_CMD_12BIT((cad), (nid), \
664
HDA_CMD_VERB_GET_STRIPE_CONTROL, 0x0))
665
#define HDA_CMD_SET_STRIPE_CONTROL(cad, nid, payload) \
666
(HDA_CMD_12BIT((cad), (nid), \
667
HDA_CMD_VERB_SET_STRIPE_CONTROL, (payload)))
668
669
/* Channel Count Control */
670
#define HDA_CMD_VERB_GET_CONV_CHAN_COUNT 0xf2d
671
#define HDA_CMD_VERB_SET_CONV_CHAN_COUNT 0x72d
672
673
#define HDA_CMD_GET_CONV_CHAN_COUNT(cad, nid) \
674
(HDA_CMD_12BIT((cad), (nid), \
675
HDA_CMD_VERB_GET_CONV_CHAN_COUNT, 0x0))
676
#define HDA_CMD_SET_CONV_CHAN_COUNT(cad, nid, payload) \
677
(HDA_CMD_12BIT((cad), (nid), \
678
HDA_CMD_VERB_SET_CONV_CHAN_COUNT, (payload)))
679
680
#define HDA_CMD_VERB_GET_HDMI_DIP_SIZE 0xf2e
681
682
#define HDA_CMD_GET_HDMI_DIP_SIZE(cad, nid, arg) \
683
(HDA_CMD_12BIT((cad), (nid), \
684
HDA_CMD_VERB_GET_HDMI_DIP_SIZE, (arg)))
685
686
#define HDA_CMD_VERB_GET_HDMI_ELDD 0xf2f
687
688
#define HDA_CMD_GET_HDMI_ELDD(cad, nid, off) \
689
(HDA_CMD_12BIT((cad), (nid), \
690
HDA_CMD_VERB_GET_HDMI_ELDD, (off)))
691
692
#define HDA_CMD_VERB_GET_HDMI_DIP_INDEX 0xf30
693
#define HDA_CMD_VERB_SET_HDMI_DIP_INDEX 0x730
694
695
#define HDA_CMD_GET_HDMI_DIP_INDEX(cad, nid) \
696
(HDA_CMD_12BIT((cad), (nid), \
697
HDA_CMD_VERB_GET_HDMI_DIP_INDEX, 0x0))
698
#define HDA_CMD_SET_HDMI_DIP_INDEX(cad, nid, payload) \
699
(HDA_CMD_12BIT((cad), (nid), \
700
HDA_CMD_VERB_SET_HDMI_DIP_INDEX, (payload)))
701
702
#define HDA_CMD_VERB_GET_HDMI_DIP_DATA 0xf31
703
#define HDA_CMD_VERB_SET_HDMI_DIP_DATA 0x731
704
705
#define HDA_CMD_GET_HDMI_DIP_DATA(cad, nid) \
706
(HDA_CMD_12BIT((cad), (nid), \
707
HDA_CMD_VERB_GET_HDMI_DIP_DATA, 0x0))
708
#define HDA_CMD_SET_HDMI_DIP_DATA(cad, nid, payload) \
709
(HDA_CMD_12BIT((cad), (nid), \
710
HDA_CMD_VERB_SET_HDMI_DIP_DATA, (payload)))
711
712
#define HDA_CMD_VERB_GET_HDMI_DIP_XMIT 0xf32
713
#define HDA_CMD_VERB_SET_HDMI_DIP_XMIT 0x732
714
715
#define HDA_CMD_GET_HDMI_DIP_XMIT(cad, nid) \
716
(HDA_CMD_12BIT((cad), (nid), \
717
HDA_CMD_VERB_GET_HDMI_DIP_XMIT, 0x0))
718
#define HDA_CMD_SET_HDMI_DIP_XMIT(cad, nid, payload) \
719
(HDA_CMD_12BIT((cad), (nid), \
720
HDA_CMD_VERB_SET_HDMI_DIP_XMIT, (payload)))
721
722
#define HDA_CMD_VERB_GET_HDMI_CP_CTRL 0xf33
723
#define HDA_CMD_VERB_SET_HDMI_CP_CTRL 0x733
724
725
#define HDA_CMD_VERB_GET_HDMI_CHAN_SLOT 0xf34
726
#define HDA_CMD_VERB_SET_HDMI_CHAN_SLOT 0x734
727
728
#define HDA_CMD_GET_HDMI_CHAN_SLOT(cad, nid) \
729
(HDA_CMD_12BIT((cad), (nid), \
730
HDA_CMD_VERB_GET_HDMI_CHAN_SLOT, 0x0))
731
#define HDA_CMD_SET_HDMI_CHAN_SLOT(cad, nid, payload) \
732
(HDA_CMD_12BIT((cad), (nid), \
733
HDA_CMD_VERB_SET_HDMI_CHAN_SLOT, (payload)))
734
735
#define HDA_HDMI_CODING_TYPE_REF_STREAM_HEADER 0
736
#define HDA_HDMI_CODING_TYPE_LPCM 1
737
#define HDA_HDMI_CODING_TYPE_AC3 2
738
#define HDA_HDMI_CODING_TYPE_MPEG1 3
739
#define HDA_HDMI_CODING_TYPE_MP3 4
740
#define HDA_HDMI_CODING_TYPE_MPEG2 5
741
#define HDA_HDMI_CODING_TYPE_AACLC 6
742
#define HDA_HDMI_CODING_TYPE_DTS 7
743
#define HDA_HDMI_CODING_TYPE_ATRAC 8
744
#define HDA_HDMI_CODING_TYPE_SACD 9
745
#define HDA_HDMI_CODING_TYPE_EAC3 10
746
#define HDA_HDMI_CODING_TYPE_DTS_HD 11
747
#define HDA_HDMI_CODING_TYPE_MLP 12
748
#define HDA_HDMI_CODING_TYPE_DST 13
749
#define HDA_HDMI_CODING_TYPE_WMAPRO 14
750
#define HDA_HDMI_CODING_TYPE_REF_CTX 15
751
752
/* Function Reset */
753
#define HDA_CMD_VERB_FUNCTION_RESET 0x7ff
754
755
#define HDA_CMD_FUNCTION_RESET(cad, nid) \
756
(HDA_CMD_12BIT((cad), (nid), \
757
HDA_CMD_VERB_FUNCTION_RESET, 0x0))
758
759
/****************************************************************************
760
* HDA Device Parameters
761
****************************************************************************/
762
763
/* Vendor ID */
764
#define HDA_PARAM_VENDOR_ID 0x00
765
766
#define HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK 0xffff0000
767
#define HDA_PARAM_VENDOR_ID_VENDOR_ID_SHIFT 16
768
#define HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK 0x0000ffff
769
#define HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT 0
770
771
#define HDA_PARAM_VENDOR_ID_VENDOR_ID(param) \
772
(((param) & HDA_PARAM_VENDOR_ID_VENDOR_ID_MASK) >> \
773
HDA_PARAM_VENDOR_ID_VENDOR_ID_SHIFT)
774
#define HDA_PARAM_VENDOR_ID_DEVICE_ID(param) \
775
(((param) & HDA_PARAM_VENDOR_ID_DEVICE_ID_MASK) >> \
776
HDA_PARAM_VENDOR_ID_DEVICE_ID_SHIFT)
777
778
/* Revision ID */
779
#define HDA_PARAM_REVISION_ID 0x02
780
781
#define HDA_PARAM_REVISION_ID_MAJREV_MASK 0x00f00000
782
#define HDA_PARAM_REVISION_ID_MAJREV_SHIFT 20
783
#define HDA_PARAM_REVISION_ID_MINREV_MASK 0x000f0000
784
#define HDA_PARAM_REVISION_ID_MINREV_SHIFT 16
785
#define HDA_PARAM_REVISION_ID_REVISION_ID_MASK 0x0000ff00
786
#define HDA_PARAM_REVISION_ID_REVISION_ID_SHIFT 8
787
#define HDA_PARAM_REVISION_ID_STEPPING_ID_MASK 0x000000ff
788
#define HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT 0
789
790
#define HDA_PARAM_REVISION_ID_MAJREV(param) \
791
(((param) & HDA_PARAM_REVISION_ID_MAJREV_MASK) >> \
792
HDA_PARAM_REVISION_ID_MAJREV_SHIFT)
793
#define HDA_PARAM_REVISION_ID_MINREV(param) \
794
(((param) & HDA_PARAM_REVISION_ID_MINREV_MASK) >> \
795
HDA_PARAM_REVISION_ID_MINREV_SHIFT)
796
#define HDA_PARAM_REVISION_ID_REVISION_ID(param) \
797
(((param) & HDA_PARAM_REVISION_ID_REVISION_ID_MASK) >> \
798
HDA_PARAM_REVISION_ID_REVISION_ID_SHIFT)
799
#define HDA_PARAM_REVISION_ID_STEPPING_ID(param) \
800
(((param) & HDA_PARAM_REVISION_ID_STEPPING_ID_MASK) >> \
801
HDA_PARAM_REVISION_ID_STEPPING_ID_SHIFT)
802
803
/* Subordinate Node Cound */
804
#define HDA_PARAM_SUB_NODE_COUNT 0x04
805
806
#define HDA_PARAM_SUB_NODE_COUNT_START_MASK 0x00ff0000
807
#define HDA_PARAM_SUB_NODE_COUNT_START_SHIFT 16
808
#define HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK 0x000000ff
809
#define HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT 0
810
811
#define HDA_PARAM_SUB_NODE_COUNT_START(param) \
812
(((param) & HDA_PARAM_SUB_NODE_COUNT_START_MASK) >> \
813
HDA_PARAM_SUB_NODE_COUNT_START_SHIFT)
814
#define HDA_PARAM_SUB_NODE_COUNT_TOTAL(param) \
815
(((param) & HDA_PARAM_SUB_NODE_COUNT_TOTAL_MASK) >> \
816
HDA_PARAM_SUB_NODE_COUNT_TOTAL_SHIFT)
817
818
/* Function Group Type */
819
#define HDA_PARAM_FCT_GRP_TYPE 0x05
820
821
#define HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK 0x00000100
822
#define HDA_PARAM_FCT_GRP_TYPE_UNSOL_SHIFT 8
823
#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK 0x000000ff
824
#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT 0
825
826
#define HDA_PARAM_FCT_GRP_TYPE_UNSOL(param) \
827
(((param) & HDA_PARAM_FCT_GRP_TYPE_UNSOL_MASK) >> \
828
HDA_PARAM_FCT_GROUP_TYPE_UNSOL_SHIFT)
829
#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(param) \
830
(((param) & HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MASK) >> \
831
HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_SHIFT)
832
833
#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO 0x01
834
#define HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM 0x02
835
836
/* Audio Function Group Capabilities */
837
#define HDA_PARAM_AUDIO_FCT_GRP_CAP 0x08
838
839
#define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK 0x00010000
840
#define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_SHIFT 16
841
#define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK 0x00000f00
842
#define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_SHIFT 8
843
#define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK 0x0000000f
844
#define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT 0
845
846
#define HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN(param) \
847
(((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_MASK) >> \
848
HDA_PARAM_AUDIO_FCT_GRP_CAP_BEEP_GEN_SHIFT)
849
#define HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY(param) \
850
(((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_MASK) >> \
851
HDA_PARAM_AUDIO_FCT_GRP_CAP_INPUT_DELAY_SHIFT)
852
#define HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY(param) \
853
(((param) & HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_MASK) >> \
854
HDA_PARAM_AUDIO_FCT_GRP_CAP_OUTPUT_DELAY_SHIFT)
855
856
/* Audio Widget Capabilities */
857
#define HDA_PARAM_AUDIO_WIDGET_CAP 0x09
858
859
#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK 0x00f00000
860
#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT 20
861
#define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK 0x000f0000
862
#define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_SHIFT 16
863
#define HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_MASK 0x0000e000
864
#define HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_SHIFT 13
865
#define HDA_PARAM_AUDIO_WIDGET_CAP_CP_MASK 0x00001000
866
#define HDA_PARAM_AUDIO_WIDGET_CAP_CP_SHIFT 12
867
#define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK 0x00000800
868
#define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_SHIFT 11
869
#define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK 0x00000400
870
#define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_SHIFT 10
871
#define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK 0x00000200
872
#define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_SHIFT 9
873
#define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK 0x00000100
874
#define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT 8
875
#define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK 0x00000080
876
#define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_SHIFT 7
877
#define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK 0x00000040
878
#define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_SHIFT 6
879
#define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK 0x00000020
880
#define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_SHIFT 5
881
#define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK 0x00000010
882
#define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT 4
883
#define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK 0x00000008
884
#define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT 3
885
#define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK 0x00000004
886
#define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT 2
887
#define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK 0x00000002
888
#define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT 1
889
#define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK 0x00000001
890
#define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT 0
891
892
#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(param) \
893
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK) >> \
894
HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT)
895
#define HDA_PARAM_AUDIO_WIDGET_CAP_DELAY(param) \
896
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_MASK) >> \
897
HDA_PARAM_AUDIO_WIDGET_CAP_DELAY_SHIFT)
898
#define HDA_PARAM_AUDIO_WIDGET_CAP_CC(param) \
899
((((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_MASK) >> \
900
(HDA_PARAM_AUDIO_WIDGET_CAP_CC_EXT_SHIFT - 1)) | \
901
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK) >> \
902
HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT))
903
#define HDA_PARAM_AUDIO_WIDGET_CAP_CP(param) \
904
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CP_MASK) >> \
905
HDA_PARAM_AUDIO_WIDGET_CAP_CP_SHIFT)
906
#define HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(param) \
907
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_MASK) >> \
908
HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP_SHIFT)
909
#define HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(param) \
910
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_MASK) >> \
911
HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL_SHIFT)
912
#define HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(param) \
913
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_MASK) >> \
914
HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL_SHIFT)
915
#define HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST(param) \
916
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_MASK) >> \
917
HDA_PARAM_AUDIO_WIDGET_CAP_CONN_LIST_SHIFT)
918
#define HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(param) \
919
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_MASK) >> \
920
HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP_SHIFT)
921
#define HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(param) \
922
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_MASK) >> \
923
HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET_SHIFT)
924
#define HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(param) \
925
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_MASK) >> \
926
HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE_SHIFT)
927
#define HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(param) \
928
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_MASK) >> \
929
HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR_SHIFT)
930
#define HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(param) \
931
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_MASK) >> \
932
HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR_SHIFT)
933
#define HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(param) \
934
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_MASK) >> \
935
HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP_SHIFT)
936
#define HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(param) \
937
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_MASK) >> \
938
HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP_SHIFT)
939
#define HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(param) \
940
(((param) & HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_MASK) >> \
941
HDA_PARAM_AUDIO_WIDGET_CAP_STEREO_SHIFT)
942
943
#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT 0x0
944
#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT 0x1
945
#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER 0x2
946
#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR 0x3
947
#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX 0x4
948
#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET 0x5
949
#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET 0x6
950
#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET 0x7
951
#define HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET 0xf
952
953
/* Supported PCM Size, Rates */
954
955
#define HDA_PARAM_SUPP_PCM_SIZE_RATE 0x0a
956
957
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK 0x00100000
958
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_SHIFT 20
959
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK 0x00080000
960
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_SHIFT 19
961
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK 0x00040000
962
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_SHIFT 18
963
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK 0x00020000
964
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_SHIFT 17
965
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK 0x00010000
966
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_SHIFT 16
967
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK 0x00000001
968
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT 0
969
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK 0x00000002
970
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_SHIFT 1
971
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK 0x00000004
972
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_SHIFT 2
973
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK 0x00000008
974
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_SHIFT 3
975
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK 0x00000010
976
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_SHIFT 4
977
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK 0x00000020
978
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_SHIFT 5
979
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK 0x00000040
980
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_SHIFT 6
981
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK 0x00000080
982
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_SHIFT 7
983
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK 0x00000100
984
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_SHIFT 8
985
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK 0x00000200
986
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_SHIFT 9
987
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK 0x00000400
988
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_SHIFT 10
989
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK 0x00000800
990
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_SHIFT 11
991
992
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(param) \
993
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_MASK) >> \
994
HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT_SHIFT)
995
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(param) \
996
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_MASK) >> \
997
HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT_SHIFT)
998
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(param) \
999
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_MASK) >> \
1000
HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT_SHIFT)
1001
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(param) \
1002
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_MASK) >> \
1003
HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT_SHIFT)
1004
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(param) \
1005
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_MASK) >> \
1006
HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT_SHIFT)
1007
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(param) \
1008
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_MASK) >> \
1009
HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ_SHIFT)
1010
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(param) \
1011
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_MASK) >> \
1012
HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ_SHIFT)
1013
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(param) \
1014
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_MASK) >> \
1015
HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ_SHIFT)
1016
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(param) \
1017
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_MASK) >> \
1018
HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ_SHIFT)
1019
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(param) \
1020
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_MASK) >> \
1021
HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ_SHIFT)
1022
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(param) \
1023
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_MASK) >> \
1024
HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ_SHIFT)
1025
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(param) \
1026
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_MASK) >> \
1027
HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ_SHIFT)
1028
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(param) \
1029
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_MASK) >> \
1030
HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ_SHIFT)
1031
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(param) \
1032
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_MASK) >> \
1033
HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ_SHIFT)
1034
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(param) \
1035
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_MASK) >> \
1036
HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ_SHIFT)
1037
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(param) \
1038
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_MASK) >> \
1039
HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ_SHIFT)
1040
#define HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(param) \
1041
(((param) & HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_MASK) >> \
1042
HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ_SHIFT)
1043
1044
/* Supported Stream Formats */
1045
#define HDA_PARAM_SUPP_STREAM_FORMATS 0x0b
1046
1047
#define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK 0x00000004
1048
#define HDA_PARAM_SUPP_STREAM_FORMATS_AC3_SHIFT 2
1049
#define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK 0x00000002
1050
#define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_SHIFT 1
1051
#define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK 0x00000001
1052
#define HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT 0
1053
1054
#define HDA_PARAM_SUPP_STREAM_FORMATS_AC3(param) \
1055
(((param) & HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK) >> \
1056
HDA_PARAM_SUPP_STREAM_FORMATS_AC3_SHIFT)
1057
#define HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(param) \
1058
(((param) & HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_MASK) >> \
1059
HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32_SHIFT)
1060
#define HDA_PARAM_SUPP_STREAM_FORMATS_PCM(param) \
1061
(((param) & HDA_PARAM_SUPP_STREAM_FORMATS_PCM_MASK) >> \
1062
HDA_PARAM_SUPP_STREAM_FORMATS_PCM_SHIFT)
1063
1064
/* Pin Capabilities */
1065
#define HDA_PARAM_PIN_CAP 0x0c
1066
1067
#define HDA_PARAM_PIN_CAP_HBR_MASK 0x08000000
1068
#define HDA_PARAM_PIN_CAP_HBR_SHIFT 27
1069
#define HDA_PARAM_PIN_CAP_DP_MASK 0x01000000
1070
#define HDA_PARAM_PIN_CAP_DP_SHIFT 24
1071
#define HDA_PARAM_PIN_CAP_EAPD_CAP_MASK 0x00010000
1072
#define HDA_PARAM_PIN_CAP_EAPD_CAP_SHIFT 16
1073
#define HDA_PARAM_PIN_CAP_VREF_CTRL_MASK 0x0000ff00
1074
#define HDA_PARAM_PIN_CAP_VREF_CTRL_SHIFT 8
1075
#define HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK 0x00002000
1076
#define HDA_PARAM_PIN_CAP_VREF_CTRL_100_SHIFT 13
1077
#define HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK 0x00001000
1078
#define HDA_PARAM_PIN_CAP_VREF_CTRL_80_SHIFT 12
1079
#define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK 0x00000400
1080
#define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_SHIFT 10
1081
#define HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK 0x00000200
1082
#define HDA_PARAM_PIN_CAP_VREF_CTRL_50_SHIFT 9
1083
#define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK 0x00000100
1084
#define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_SHIFT 8
1085
#define HDA_PARAM_PIN_CAP_HDMI_MASK 0x00000080
1086
#define HDA_PARAM_PIN_CAP_HDMI_SHIFT 7
1087
#define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK 0x00000040
1088
#define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_SHIFT 6
1089
#define HDA_PARAM_PIN_CAP_INPUT_CAP_MASK 0x00000020
1090
#define HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT 5
1091
#define HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK 0x00000010
1092
#define HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT 4
1093
#define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK 0x00000008
1094
#define HDA_PARAM_PIN_CAP_HEADPHONE_CAP_SHIFT 3
1095
#define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK 0x00000004
1096
#define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_SHIFT 2
1097
#define HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK 0x00000002
1098
#define HDA_PARAM_PIN_CAP_TRIGGER_REQD_SHIFT 1
1099
#define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK 0x00000001
1100
#define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT 0
1101
1102
#define HDA_PARAM_PIN_CAP_HBR(param) \
1103
(((param) & HDA_PARAM_PIN_CAP_HBR_MASK) >> \
1104
HDA_PARAM_PIN_CAP_HBR_SHIFT)
1105
#define HDA_PARAM_PIN_CAP_DP(param) \
1106
(((param) & HDA_PARAM_PIN_CAP_DP_MASK) >> \
1107
HDA_PARAM_PIN_CAP_DP_SHIFT)
1108
#define HDA_PARAM_PIN_CAP_EAPD_CAP(param) \
1109
(((param) & HDA_PARAM_PIN_CAP_EAPD_CAP_MASK) >> \
1110
HDA_PARAM_PIN_CAP_EAPD_CAP_SHIFT)
1111
#define HDA_PARAM_PIN_CAP_VREF_CTRL(param) \
1112
(((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_MASK) >> \
1113
HDA_PARAM_PIN_CAP_VREF_CTRL_SHIFT)
1114
#define HDA_PARAM_PIN_CAP_VREF_CTRL_100(param) \
1115
(((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK) >> \
1116
HDA_PARAM_PIN_CAP_VREF_CTRL_100_SHIFT)
1117
#define HDA_PARAM_PIN_CAP_VREF_CTRL_80(param) \
1118
(((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK) >> \
1119
HDA_PARAM_PIN_CAP_VREF_CTRL_80_SHIFT)
1120
#define HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(param) \
1121
(((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_MASK) >> \
1122
HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND_SHIFT)
1123
#define HDA_PARAM_PIN_CAP_VREF_CTRL_50(param) \
1124
(((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK) >> \
1125
HDA_PARAM_PIN_CAP_VREF_CTRL_50_SHIFT)
1126
#define HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(param) \
1127
(((param) & HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_MASK) >> \
1128
HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ_SHIFT)
1129
#define HDA_PARAM_PIN_CAP_HDMI(param) \
1130
(((param) & HDA_PARAM_PIN_CAP_HDMI_MASK) >> \
1131
HDA_PARAM_PIN_CAP_HDMI_SHIFT)
1132
#define HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(param) \
1133
(((param) & HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_MASK) >> \
1134
HDA_PARAM_PIN_CAP_BALANCED_IO_PINS_SHIFT)
1135
#define HDA_PARAM_PIN_CAP_INPUT_CAP(param) \
1136
(((param) & HDA_PARAM_PIN_CAP_INPUT_CAP_MASK) >> \
1137
HDA_PARAM_PIN_CAP_INPUT_CAP_SHIFT)
1138
#define HDA_PARAM_PIN_CAP_OUTPUT_CAP(param) \
1139
(((param) & HDA_PARAM_PIN_CAP_OUTPUT_CAP_MASK) >> \
1140
HDA_PARAM_PIN_CAP_OUTPUT_CAP_SHIFT)
1141
#define HDA_PARAM_PIN_CAP_HEADPHONE_CAP(param) \
1142
(((param) & HDA_PARAM_PIN_CAP_HEADPHONE_CAP_MASK) >> \
1143
HDA_PARAM_PIN_CAP_HEADPHONE_CAP_SHIFT)
1144
#define HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(param) \
1145
(((param) & HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_MASK) >> \
1146
HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP_SHIFT)
1147
#define HDA_PARAM_PIN_CAP_TRIGGER_REQD(param) \
1148
(((param) & HDA_PARAM_PIN_CAP_TRIGGER_REQD_MASK) >> \
1149
HDA_PARAM_PIN_CAP_TRIGGER_REQD_SHIFT)
1150
#define HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(param) \
1151
(((param) & HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_MASK) >> \
1152
HDA_PARAM_PIN_CAP_IMP_SENSE_CAP_SHIFT)
1153
1154
/* Input Amplifier Capabilities */
1155
#define HDA_PARAM_INPUT_AMP_CAP 0x0d
1156
1157
#define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000
1158
#define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_SHIFT 31
1159
#define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000
1160
#define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_SHIFT 16
1161
#define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00
1162
#define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_SHIFT 8
1163
#define HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK 0x0000007f
1164
#define HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT 0
1165
1166
#define HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP(param) \
1167
(((param) & HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_MASK) >> \
1168
HDA_PARAM_INPUT_AMP_CAP_MUTE_CAP_SHIFT)
1169
#define HDA_PARAM_INPUT_AMP_CAP_STEPSIZE(param) \
1170
(((param) & HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_MASK) >> \
1171
HDA_PARAM_INPUT_AMP_CAP_STEPSIZE_SHIFT)
1172
#define HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS(param) \
1173
(((param) & HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_MASK) >> \
1174
HDA_PARAM_INPUT_AMP_CAP_NUMSTEPS_SHIFT)
1175
#define HDA_PARAM_INPUT_AMP_CAP_OFFSET(param) \
1176
(((param) & HDA_PARAM_INPUT_AMP_CAP_OFFSET_MASK) >> \
1177
HDA_PARAM_INPUT_AMP_CAP_OFFSET_SHIFT)
1178
1179
/* Output Amplifier Capabilities */
1180
#define HDA_PARAM_OUTPUT_AMP_CAP 0x12
1181
1182
#define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK 0x80000000
1183
#define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT 31
1184
#define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK 0x007f0000
1185
#define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT 16
1186
#define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK 0x00007f00
1187
#define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT 8
1188
#define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK 0x0000007f
1189
#define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT 0
1190
1191
#define HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(param) \
1192
(((param) & HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_MASK) >> \
1193
HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP_SHIFT)
1194
#define HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(param) \
1195
(((param) & HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_MASK) >> \
1196
HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE_SHIFT)
1197
#define HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(param) \
1198
(((param) & HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_MASK) >> \
1199
HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS_SHIFT)
1200
#define HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(param) \
1201
(((param) & HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_MASK) >> \
1202
HDA_PARAM_OUTPUT_AMP_CAP_OFFSET_SHIFT)
1203
1204
/* Connection List Length */
1205
#define HDA_PARAM_CONN_LIST_LENGTH 0x0e
1206
1207
#define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK 0x00000080
1208
#define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_SHIFT 7
1209
#define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK 0x0000007f
1210
#define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT 0
1211
1212
#define HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(param) \
1213
(((param) & HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_MASK) >> \
1214
HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM_SHIFT)
1215
#define HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(param) \
1216
(((param) & HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_MASK) >> \
1217
HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH_SHIFT)
1218
1219
/* Supported Power States */
1220
#define HDA_PARAM_SUPP_POWER_STATES 0x0f
1221
1222
#define HDA_PARAM_SUPP_POWER_STATES_D3_MASK 0x00000008
1223
#define HDA_PARAM_SUPP_POWER_STATES_D3_SHIFT 3
1224
#define HDA_PARAM_SUPP_POWER_STATES_D2_MASK 0x00000004
1225
#define HDA_PARAM_SUPP_POWER_STATES_D2_SHIFT 2
1226
#define HDA_PARAM_SUPP_POWER_STATES_D1_MASK 0x00000002
1227
#define HDA_PARAM_SUPP_POWER_STATES_D1_SHIFT 1
1228
#define HDA_PARAM_SUPP_POWER_STATES_D0_MASK 0x00000001
1229
#define HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT 0
1230
1231
#define HDA_PARAM_SUPP_POWER_STATES_D3(param) \
1232
(((param) & HDA_PARAM_SUPP_POWER_STATES_D3_MASK) >> \
1233
HDA_PARAM_SUPP_POWER_STATES_D3_SHIFT)
1234
#define HDA_PARAM_SUPP_POWER_STATES_D2(param) \
1235
(((param) & HDA_PARAM_SUPP_POWER_STATES_D2_MASK) >> \
1236
HDA_PARAM_SUPP_POWER_STATES_D2_SHIFT)
1237
#define HDA_PARAM_SUPP_POWER_STATES_D1(param) \
1238
(((param) & HDA_PARAM_SUPP_POWER_STATES_D1_MASK) >> \
1239
HDA_PARAM_SUPP_POWER_STATES_D1_SHIFT)
1240
#define HDA_PARAM_SUPP_POWER_STATES_D0(param) \
1241
(((param) & HDA_PARAM_SUPP_POWER_STATES_D0_MASK) >> \
1242
HDA_PARAM_SUPP_POWER_STATES_D0_SHIFT)
1243
1244
/* Processing Capabilities */
1245
#define HDA_PARAM_PROCESSING_CAP 0x10
1246
1247
#define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK 0x0000ff00
1248
#define HDA_PARAM_PROCESSING_CAP_NUMCOEFF_SHIFT 8
1249
#define HDA_PARAM_PROCESSING_CAP_BENIGN_MASK 0x00000001
1250
#define HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT 0
1251
1252
#define HDA_PARAM_PROCESSING_CAP_NUMCOEFF(param) \
1253
(((param) & HDA_PARAM_PROCESSING_CAP_NUMCOEFF_MASK) >> \
1254
HDA_PARAM_PROCESSING_CAP_NUMCOEFF_SHIFT)
1255
#define HDA_PARAM_PROCESSING_CAP_BENIGN(param) \
1256
(((param) & HDA_PARAM_PROCESSING_CAP_BENIGN_MASK) >> \
1257
HDA_PARAM_PROCESSING_CAP_BENIGN_SHIFT)
1258
1259
/* GPIO Count */
1260
#define HDA_PARAM_GPIO_COUNT 0x11
1261
1262
#define HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK 0x80000000
1263
#define HDA_PARAM_GPIO_COUNT_GPI_WAKE_SHIFT 31
1264
#define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK 0x40000000
1265
#define HDA_PARAM_GPIO_COUNT_GPI_UNSOL_SHIFT 30
1266
#define HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK 0x00ff0000
1267
#define HDA_PARAM_GPIO_COUNT_NUM_GPI_SHIFT 16
1268
#define HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK 0x0000ff00
1269
#define HDA_PARAM_GPIO_COUNT_NUM_GPO_SHIFT 8
1270
#define HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK 0x000000ff
1271
#define HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT 0
1272
1273
#define HDA_PARAM_GPIO_COUNT_GPI_WAKE(param) \
1274
(((param) & HDA_PARAM_GPIO_COUNT_GPI_WAKE_MASK) >> \
1275
HDA_PARAM_GPIO_COUNT_GPI_WAKE_SHIFT)
1276
#define HDA_PARAM_GPIO_COUNT_GPI_UNSOL(param) \
1277
(((param) & HDA_PARAM_GPIO_COUNT_GPI_UNSOL_MASK) >> \
1278
HDA_PARAM_GPIO_COUNT_GPI_UNSOL_SHIFT)
1279
#define HDA_PARAM_GPIO_COUNT_NUM_GPI(param) \
1280
(((param) & HDA_PARAM_GPIO_COUNT_NUM_GPI_MASK) >> \
1281
HDA_PARAM_GPIO_COUNT_NUM_GPI_SHIFT)
1282
#define HDA_PARAM_GPIO_COUNT_NUM_GPO(param) \
1283
(((param) & HDA_PARAM_GPIO_COUNT_NUM_GPO_MASK) >> \
1284
HDA_PARAM_GPIO_COUNT_NUM_GPO_SHIFT)
1285
#define HDA_PARAM_GPIO_COUNT_NUM_GPIO(param) \
1286
(((param) & HDA_PARAM_GPIO_COUNT_NUM_GPIO_MASK) >> \
1287
HDA_PARAM_GPIO_COUNT_NUM_GPIO_SHIFT)
1288
1289
/* Volume Knob Capabilities */
1290
#define HDA_PARAM_VOLUME_KNOB_CAP 0x13
1291
1292
#define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK 0x00000080
1293
#define HDA_PARAM_VOLUME_KNOB_CAP_DELTA_SHIFT 7
1294
#define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK 0x0000007f
1295
#define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT 0
1296
1297
#define HDA_PARAM_VOLUME_KNOB_CAP_DELTA(param) \
1298
(((param) & HDA_PARAM_VOLUME_KNOB_CAP_DELTA_MASK) >> \
1299
HDA_PARAM_VOLUME_KNOB_CAP_DELTA_SHIFT)
1300
#define HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS(param) \
1301
(((param) & HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_MASK) >> \
1302
HDA_PARAM_VOLUME_KNOB_CAP_NUM_STEPS_SHIFT)
1303
1304
#define HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK 0x0000000f
1305
#define HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT 0
1306
#define HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK 0x000000f0
1307
#define HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT 4
1308
#define HDA_CONFIG_DEFAULTCONF_MISC_MASK 0x00000f00
1309
#define HDA_CONFIG_DEFAULTCONF_MISC_SHIFT 8
1310
#define HDA_CONFIG_DEFAULTCONF_COLOR_MASK 0x0000f000
1311
#define HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT 12
1312
#define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK 0x000f0000
1313
#define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT 16
1314
#define HDA_CONFIG_DEFAULTCONF_DEVICE_MASK 0x00f00000
1315
#define HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT 20
1316
#define HDA_CONFIG_DEFAULTCONF_LOCATION_MASK 0x3f000000
1317
#define HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT 24
1318
#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK 0xc0000000
1319
#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT 30
1320
1321
#define HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf) \
1322
(((conf) & HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK) >> \
1323
HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT)
1324
#define HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf) \
1325
(((conf) & HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) >> \
1326
HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT)
1327
#define HDA_CONFIG_DEFAULTCONF_MISC(conf) \
1328
(((conf) & HDA_CONFIG_DEFAULTCONF_MISC_MASK) >> \
1329
HDA_CONFIG_DEFAULTCONF_MISC_SHIFT)
1330
#define HDA_CONFIG_DEFAULTCONF_COLOR(conf) \
1331
(((conf) & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> \
1332
HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT)
1333
#define HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf) \
1334
(((conf) & HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK) >> \
1335
HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT)
1336
#define HDA_CONFIG_DEFAULTCONF_DEVICE(conf) \
1337
(((conf) & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> \
1338
HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT)
1339
#define HDA_CONFIG_DEFAULTCONF_LOCATION(conf) \
1340
(((conf) & HDA_CONFIG_DEFAULTCONF_LOCATION_MASK) >> \
1341
HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT)
1342
#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf) \
1343
(((conf) & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> \
1344
HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT)
1345
1346
#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK (0<<30)
1347
#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE (1<<30)
1348
#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED (2<<30)
1349
#define HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_BOTH (3<<30)
1350
1351
#define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT (0<<20)
1352
#define HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER (1<<20)
1353
#define HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT (2<<20)
1354
#define HDA_CONFIG_DEFAULTCONF_DEVICE_CD (3<<20)
1355
#define HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT (4<<20)
1356
#define HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT (5<<20)
1357
#define HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_LINE (6<<20)
1358
#define HDA_CONFIG_DEFAULTCONF_DEVICE_MODEM_HANDSET (7<<20)
1359
#define HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN (8<<20)
1360
#define HDA_CONFIG_DEFAULTCONF_DEVICE_AUX (9<<20)
1361
#define HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN (10<<20)
1362
#define HDA_CONFIG_DEFAULTCONF_DEVICE_TELEPHONY (11<<20)
1363
#define HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN (12<<20)
1364
#define HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN (13<<20)
1365
#define HDA_CONFIG_DEFAULTCONF_DEVICE_OTHER (15<<20)
1366
1367
#endif
dev
sound
pci
hda
hda_reg.h
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