31#define PCI_VENDOR_XILINX 0x10ee
32#define PCI_DEVICE_XILINX_HDSPE 0x3fc6
33#define PCI_CLASS_REVISION 0x08
34#define PCI_REVISION_AIO 212
35#define PCI_REVISION_RAYDAT 211
41#define HDSPE_OUT_ENABLE_BASE 512
42#define HDSPE_IN_ENABLE_BASE 768
43#define HDSPE_MIXER_BASE 32768
44#define HDSPE_MAX_GAIN 32768
47#define HDSPE_PAGE_ADDR_BUF_OUT 8192
48#define HDSPE_PAGE_ADDR_BUF_IN (HDSPE_PAGE_ADDR_BUF_OUT + 64 * 16 * 4)
49#define HDSPE_BUF_POSITION_MASK 0x000FFC0
52#define HDSPE_FREQ_0 (1 << 6)
53#define HDSPE_FREQ_1 (1 << 7)
54#define HDSPE_FREQ_DOUBLE (1 << 8)
55#define HDSPE_FREQ_QUAD (1 << 31)
57#define HDSPE_FREQ_32000 HDSPE_FREQ_0
58#define HDSPE_FREQ_44100 HDSPE_FREQ_1
59#define HDSPE_FREQ_48000 (HDSPE_FREQ_0 | HDSPE_FREQ_1)
60#define HDSPE_FREQ_MASK (HDSPE_FREQ_0 | HDSPE_FREQ_1 | \
61 HDSPE_FREQ_DOUBLE | HDSPE_FREQ_QUAD)
62#define HDSPE_FREQ_MASK_DEFAULT HDSPE_FREQ_48000
63#define HDSPE_FREQ_REG 256
64#define HDSPE_FREQ_AIO 104857600000000ULL
66#define HDSPE_SPEED_DEFAULT 48000
69#define HDSPE_LAT_0 (1 << 1)
70#define HDSPE_LAT_1 (1 << 2)
71#define HDSPE_LAT_2 (1 << 3)
72#define HDSPE_LAT_MASK (HDSPE_LAT_0 | HDSPE_LAT_1 | HDSPE_LAT_2)
73#define HDSPE_LAT_BYTES_MAX (4096 * 4)
74#define HDSPE_LAT_BYTES_MIN (32 * 4)
75#define hdspe_encode_latency(x) (((x)<<1) & HDSPE_LAT_MASK)
78#define HDSP_ADGain0 (1 << 25)
79#define HDSP_ADGain1 (1 << 26)
80#define HDSP_DAGain0 (1 << 27)
81#define HDSP_DAGain1 (1 << 28)
82#define HDSP_PhoneGain0 (1 << 29)
83#define HDSP_PhoneGain1 (1 << 30)
85#define HDSP_ADGainMask (HDSP_ADGain0 | HDSP_ADGain1)
86#define HDSP_ADGainMinus10dBV (HDSP_ADGainMask)
87#define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
88#define HDSP_ADGainLowGain 0
90#define HDSP_DAGainMask (HDSP_DAGain0 | HDSP_DAGain1)
91#define HDSP_DAGainHighGain (HDSP_DAGainMask)
92#define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
93#define HDSP_DAGainMinus10dBV 0
95#define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
96#define HDSP_PhoneGain0dB HDSP_PhoneGainMask
97#define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
98#define HDSP_PhoneGainMinus12dB 0
100#define HDSPM_statusRegister 0
101#define HDSPM_statusRegister2 192
104#define HDSPE_SETTINGS_REG 0
105#define HDSPE_CONTROL_REG 64
106#define HDSPE_STATUS_REG 0
107#define HDSPE_ENABLE (1 << 0)
108#define HDSPM_CLOCK_MODE_MASTER (1 << 4)
111#define HDSPE_AUDIO_IRQ_PENDING (1 << 0)
112#define HDSPE_AUDIO_INT_ENABLE (1 << 5)
113#define HDSPE_INTERRUPT_ACK 96
116#define HDSPE_MAX_SLOTS 64
117#define HDSPE_MAX_CHANS (HDSPE_MAX_SLOTS / 2)
119#define HDSPE_CHANBUF_SAMPLES (16 * 1024)
120#define HDSPE_CHANBUF_SIZE (4 * HDSPE_CHANBUF_SAMPLES)
121#define HDSPE_DMASEGSIZE (HDSPE_CHANBUF_SIZE * HDSPE_MAX_SLOTS)
178 bus_space_handle_t
csh;
180 struct resource *
irq;
195#define hdspe_read_1(sc, regno) \
196 bus_space_read_1((sc)->cst, (sc)->csh, (regno))
197#define hdspe_read_2(sc, regno) \
198 bus_space_read_2((sc)->cst, (sc)->csh, (regno))
199#define hdspe_read_4(sc, regno) \
200 bus_space_read_4((sc)->cst, (sc)->csh, (regno))
202#define hdspe_write_1(sc, regno, data) \
203 bus_space_write_1((sc)->cst, (sc)->csh, (regno), (data))
204#define hdspe_write_2(sc, regno, data) \
205 bus_space_write_2((sc)->cst, (sc)->csh, (regno), (data))
206#define hdspe_write_4(sc, regno, data) \
207 bus_space_write_4((sc)->cst, (sc)->csh, (regno), (data))
static MALLOC_DEFINE(M_HDSPE, "hdspe", "hdspe audio")
struct pcm_channel * channel
struct sc_pcminfo * parent
uint32_t settings_register
struct hdspe_channel * hc
uint32_t(* ih)(struct sc_pcminfo *scp)
struct sc_chinfo chan[HDSPE_MAX_CHANS]