#include "pci_dw_if.h"

Include dependency graph for pci_dw.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	pci_dw_softc

Macros
#define	DW_PORT_LINK_CTRL 0x710

#define	PORT_LINK_CAPABLE(n) (((n) & 0x3F) << 16)

#define	PORT_LINK_CAPABLE_1 0x01

#define	PORT_LINK_CAPABLE_2 0x03

#define	PORT_LINK_CAPABLE_4 0x07

#define	PORT_LINK_CAPABLE_8 0x0F

#define	PORT_LINK_CAPABLE_16 0x1F

#define	PORT_LINK_CAPABLE_32 0x3F

#define	DW_GEN2_CTRL 0x80C

#define	DIRECT_SPEED_CHANGE (1 << 17)

#define	GEN2_CTRL_NUM_OF_LANES(n) (((n) & 0x3F) << 8)

#define	GEN2_CTRL_NUM_OF_LANES_1 0x01

#define	GEN2_CTRL_NUM_OF_LANES_2 0x03

#define	GEN2_CTRL_NUM_OF_LANES_4 0x07

#define	GEN2_CTRL_NUM_OF_LANES_8 0x0F

#define	GEN2_CTRL_NUM_OF_LANES_16 0x1F

#define	GEN2_CTRL_NUM_OF_LANES_32 0x3F

#define	DW_MSI_ADDR_LO 0x820

#define	DW_MSI_ADDR_HI 0x824

#define	DW_MSI_INTR0_ENABLE 0x828

#define	DW_MSI_INTR0_MASK 0x82C

#define	DW_MSI_INTR0_STATUS 0x830

#define	DW_MISC_CONTROL_1 0x8BC

#define	DBI_RO_WR_EN (1 << 0)

#define	DW_IATU_VIEWPORT 0x900

#define	IATU_REGION_INBOUND (1U << 31)

#define	IATU_REGION_INDEX(x) ((x) & 0x7)

#define	DW_IATU_CTRL1 0x904

#define	IATU_CTRL1_TYPE(x) ((x) & 0x1F)

#define	IATU_CTRL1_TYPE_MEM 0x0

#define	IATU_CTRL1_TYPE_IO 0x2

#define	IATU_CTRL1_TYPE_CFG0 0x4

#define	IATU_CTRL1_TYPE_CFG1 0x5

#define	DW_IATU_CTRL2 0x908

#define	IATU_CTRL2_REGION_EN (1U << 31)

#define	DW_IATU_LWR_BASE_ADDR 0x90C

#define	DW_IATU_UPPER_BASE_ADDR 0x910

#define	DW_IATU_LIMIT_ADDR 0x914

#define	DW_IATU_LWR_TARGET_ADDR 0x918

#define	DW_IATU_UPPER_TARGET_ADDR 0x91C

#define	DW_IATU_UR_STEP 0x200

#define	DW_IATU_UR_REG(r, n) (r) * DW_IATU_UR_STEP + IATU_UR_##n

#define	IATU_UR_CTRL1 0x00

#define	IATU_UR_CTRL2 0x04

#define	IATU_UR_LWR_BASE_ADDR 0x08

#define	IATU_UR_UPPER_BASE_ADDR 0x0C

#define	IATU_UR_LIMIT_ADDR 0x10

#define	IATU_UR_LWR_TARGET_ADDR 0x14

#define	IATU_UR_UPPER_TARGET_ADDR 0x18

#define	DW_DEFAULT_IATU_UR_DBI_OFFSET 0x300000

#define	DW_DEFAULT_IATU_UR_DBI_SIZE 0x1000

Functions
	DECLARE_CLASS (pci_dw_driver)

static void	pci_dw_dbi_wr4 (device_t dev, u_int reg, uint32_t val)

static void	pci_dw_dbi_wr2 (device_t dev, u_int reg, uint16_t val)

static void	pci_dw_dbi_wr1 (device_t dev, u_int reg, uint8_t val)

static uint32_t	pci_dw_dbi_rd4 (device_t dev, u_int reg)

static uint16_t	pci_dw_dbi_rd2 (device_t dev, u_int reg)

static uint8_t	pci_dw_dbi_rd1 (device_t dev, u_int reg)

int	pci_dw_init (device_t)

Macro Definition Documentation

◆ DBI_RO_WR_EN

#define DBI_RO_WR_EN (1 << 0)

Definition at line 64 of file pci_dw.h.

◆ DIRECT_SPEED_CHANGE

#define DIRECT_SPEED_CHANGE (1 << 17)

Definition at line 48 of file pci_dw.h.

◆ DW_DEFAULT_IATU_UR_DBI_OFFSET

#define DW_DEFAULT_IATU_UR_DBI_OFFSET 0x300000

Definition at line 95 of file pci_dw.h.

◆ DW_DEFAULT_IATU_UR_DBI_SIZE

#define DW_DEFAULT_IATU_UR_DBI_SIZE 0x1000

Definition at line 96 of file pci_dw.h.

◆ DW_GEN2_CTRL

#define DW_GEN2_CTRL 0x80C

Definition at line 47 of file pci_dw.h.

◆ DW_IATU_CTRL1

#define DW_IATU_CTRL1 0x904

Definition at line 70 of file pci_dw.h.

◆ DW_IATU_CTRL2

#define DW_IATU_CTRL2 0x908

Definition at line 76 of file pci_dw.h.

◆ DW_IATU_LIMIT_ADDR

#define DW_IATU_LIMIT_ADDR 0x914

Definition at line 80 of file pci_dw.h.

◆ DW_IATU_LWR_BASE_ADDR

#define DW_IATU_LWR_BASE_ADDR 0x90C

Definition at line 78 of file pci_dw.h.

◆ DW_IATU_LWR_TARGET_ADDR

#define DW_IATU_LWR_TARGET_ADDR 0x918

Definition at line 81 of file pci_dw.h.

◆ DW_IATU_UPPER_BASE_ADDR

#define DW_IATU_UPPER_BASE_ADDR 0x910

Definition at line 79 of file pci_dw.h.

◆ DW_IATU_UPPER_TARGET_ADDR

#define DW_IATU_UPPER_TARGET_ADDR 0x91C

Definition at line 82 of file pci_dw.h.

◆ DW_IATU_UR_REG

#define DW_IATU_UR_REG	(	r,
		n
	)	(r) * DW_IATU_UR_STEP + IATU_UR_##n

Definition at line 86 of file pci_dw.h.

◆ DW_IATU_UR_STEP

#define DW_IATU_UR_STEP 0x200

Definition at line 85 of file pci_dw.h.

◆ DW_IATU_VIEWPORT

#define DW_IATU_VIEWPORT 0x900

Definition at line 67 of file pci_dw.h.

◆ DW_MISC_CONTROL_1

#define DW_MISC_CONTROL_1 0x8BC

Definition at line 63 of file pci_dw.h.

◆ DW_MSI_ADDR_HI

#define DW_MSI_ADDR_HI 0x824

Definition at line 58 of file pci_dw.h.

◆ DW_MSI_ADDR_LO

#define DW_MSI_ADDR_LO 0x820

Definition at line 57 of file pci_dw.h.

◆ DW_MSI_INTR0_ENABLE

#define DW_MSI_INTR0_ENABLE 0x828

Definition at line 59 of file pci_dw.h.

◆ DW_MSI_INTR0_MASK

#define DW_MSI_INTR0_MASK 0x82C

Definition at line 60 of file pci_dw.h.

◆ DW_MSI_INTR0_STATUS

#define DW_MSI_INTR0_STATUS 0x830

Definition at line 61 of file pci_dw.h.

◆ DW_PORT_LINK_CTRL

#define DW_PORT_LINK_CTRL 0x710

Definition at line 38 of file pci_dw.h.

◆ GEN2_CTRL_NUM_OF_LANES

#define GEN2_CTRL_NUM_OF_LANES ( n ) (((n) & 0x3F) << 8)

Definition at line 49 of file pci_dw.h.

◆ GEN2_CTRL_NUM_OF_LANES_1

#define GEN2_CTRL_NUM_OF_LANES_1 0x01

Definition at line 50 of file pci_dw.h.

◆ GEN2_CTRL_NUM_OF_LANES_16

#define GEN2_CTRL_NUM_OF_LANES_16 0x1F

Definition at line 54 of file pci_dw.h.

◆ GEN2_CTRL_NUM_OF_LANES_2

#define GEN2_CTRL_NUM_OF_LANES_2 0x03

Definition at line 51 of file pci_dw.h.

◆ GEN2_CTRL_NUM_OF_LANES_32

#define GEN2_CTRL_NUM_OF_LANES_32 0x3F

Definition at line 55 of file pci_dw.h.

◆ GEN2_CTRL_NUM_OF_LANES_4

#define GEN2_CTRL_NUM_OF_LANES_4 0x07

Definition at line 52 of file pci_dw.h.

◆ GEN2_CTRL_NUM_OF_LANES_8

#define GEN2_CTRL_NUM_OF_LANES_8 0x0F

Definition at line 53 of file pci_dw.h.

◆ IATU_CTRL1_TYPE

#define IATU_CTRL1_TYPE ( x ) ((x) & 0x1F)

Definition at line 71 of file pci_dw.h.

◆ IATU_CTRL1_TYPE_CFG0

#define IATU_CTRL1_TYPE_CFG0 0x4

Definition at line 74 of file pci_dw.h.

◆ IATU_CTRL1_TYPE_CFG1

#define IATU_CTRL1_TYPE_CFG1 0x5

Definition at line 75 of file pci_dw.h.

◆ IATU_CTRL1_TYPE_IO

#define IATU_CTRL1_TYPE_IO 0x2

Definition at line 73 of file pci_dw.h.

◆ IATU_CTRL1_TYPE_MEM

#define IATU_CTRL1_TYPE_MEM 0x0

Definition at line 72 of file pci_dw.h.

◆ IATU_CTRL2_REGION_EN

#define IATU_CTRL2_REGION_EN (1U << 31)

Definition at line 77 of file pci_dw.h.

◆ IATU_REGION_INBOUND

#define IATU_REGION_INBOUND (1U << 31)

Definition at line 68 of file pci_dw.h.

◆ IATU_REGION_INDEX

#define IATU_REGION_INDEX ( x ) ((x) & 0x7)

Definition at line 69 of file pci_dw.h.

◆ IATU_UR_CTRL1

#define IATU_UR_CTRL1 0x00

Definition at line 87 of file pci_dw.h.

◆ IATU_UR_CTRL2

#define IATU_UR_CTRL2 0x04

Definition at line 88 of file pci_dw.h.

◆ IATU_UR_LIMIT_ADDR

#define IATU_UR_LIMIT_ADDR 0x10

Definition at line 91 of file pci_dw.h.

◆ IATU_UR_LWR_BASE_ADDR

#define IATU_UR_LWR_BASE_ADDR 0x08

Definition at line 89 of file pci_dw.h.

◆ IATU_UR_LWR_TARGET_ADDR

#define IATU_UR_LWR_TARGET_ADDR 0x14

Definition at line 92 of file pci_dw.h.

◆ IATU_UR_UPPER_BASE_ADDR

#define IATU_UR_UPPER_BASE_ADDR 0x0C

Definition at line 90 of file pci_dw.h.

◆ IATU_UR_UPPER_TARGET_ADDR

#define IATU_UR_UPPER_TARGET_ADDR 0x18

Definition at line 93 of file pci_dw.h.

◆ PORT_LINK_CAPABLE

#define PORT_LINK_CAPABLE ( n ) (((n) & 0x3F) << 16)

Definition at line 39 of file pci_dw.h.

◆ PORT_LINK_CAPABLE_1

#define PORT_LINK_CAPABLE_1 0x01

Definition at line 40 of file pci_dw.h.

◆ PORT_LINK_CAPABLE_16

#define PORT_LINK_CAPABLE_16 0x1F

Definition at line 44 of file pci_dw.h.

◆ PORT_LINK_CAPABLE_2

#define PORT_LINK_CAPABLE_2 0x03

Definition at line 41 of file pci_dw.h.

◆ PORT_LINK_CAPABLE_32

#define PORT_LINK_CAPABLE_32 0x3F

Definition at line 45 of file pci_dw.h.

◆ PORT_LINK_CAPABLE_4

#define PORT_LINK_CAPABLE_4 0x07

Definition at line 42 of file pci_dw.h.

◆ PORT_LINK_CAPABLE_8

#define PORT_LINK_CAPABLE_8 0x0F

Definition at line 43 of file pci_dw.h.

Function Documentation

◆ DECLARE_CLASS()

DECLARE_CLASS ( pci_dw_driver )

◆ pci_dw_dbi_rd1()

static uint8_t pci_dw_dbi_rd1	(	device_t	dev,
		u_int	reg
	)

inlinestatic

Definition at line 164 of file pci_dw.h.

References dev, and reg.

◆ pci_dw_dbi_rd2()

static uint16_t pci_dw_dbi_rd2	(	device_t	dev,
		u_int	reg
	)

inlinestatic

Definition at line 158 of file pci_dw.h.

References dev, and reg.

◆ pci_dw_dbi_rd4()

static uint32_t pci_dw_dbi_rd4	(	device_t	dev,
		u_int	reg
	)

inlinestatic

Definition at line 152 of file pci_dw.h.

References dev, and reg.

Referenced by pci_mv_get_link(), pci_mv_init(), and pci_mv_intr().

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◆ pci_dw_dbi_wr1()

static void pci_dw_dbi_wr1	(	device_t	dev,
		u_int	reg,
		uint8_t	val
	)

inlinestatic

Definition at line 146 of file pci_dw.h.

References dev, reg, and val.

◆ pci_dw_dbi_wr2()

static void pci_dw_dbi_wr2	(	device_t	dev,
		u_int	reg,
		uint16_t	val
	)

inlinestatic

Definition at line 140 of file pci_dw.h.

References dev, reg, and val.

◆ pci_dw_dbi_wr4()

static void pci_dw_dbi_wr4	(	device_t	dev,
		u_int	reg,
		uint32_t	val
	)

inlinestatic

Definition at line 134 of file pci_dw.h.

References dev, reg, and val.

Referenced by pci_mv_init(), and pci_mv_intr().

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◆ pci_dw_init()

int pci_dw_init ( device_t dev )

Definition at line 705 of file pci_dw.c.

References pci_dw_softc::bus_end, pci_dw_softc::bus_start, pci_dw_softc::cfg_pa, pci_dw_softc::cfg_res, pci_dw_softc::cfg_size, pci_dw_softc::coherent, pci_dw_softc::dbi_res, pci_dw_softc::dev, dev, pci_dw_softc::dmat, DW_DEFAULT_IATU_UR_DBI_OFFSET, DW_DEFAULT_IATU_UR_DBI_SIZE, pci_dw_softc::iatu_ur_offset, pci_dw_softc::iatu_ur_res, pci_dw_softc::iatu_ur_size, pci_dw_softc::mtx, pci_dw_softc::node, pci_dw_softc::num_lanes, pci_dw_softc::num_out_regions, pci_dw_softc::ofw_pci, pci_dw_decode_ranges(), pci_dw_detect_atu_unroll(), pci_dw_detect_out_atu_regions(), pci_dw_setup_hw(), rid, pci_dw_softc::root_bus, and pci_dw_softc::sub_bus.

Referenced by pci_mv_attach().

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Data Structures

Macros

Functions

Macro Definition Documentation

◆ DBI_RO_WR_EN

◆ DIRECT_SPEED_CHANGE

◆ DW_DEFAULT_IATU_UR_DBI_OFFSET

◆ DW_DEFAULT_IATU_UR_DBI_SIZE

◆ DW_GEN2_CTRL

◆ DW_IATU_CTRL1

◆ DW_IATU_CTRL2

◆ DW_IATU_LIMIT_ADDR

◆ DW_IATU_LWR_BASE_ADDR

◆ DW_IATU_LWR_TARGET_ADDR

◆ DW_IATU_UPPER_BASE_ADDR

◆ DW_IATU_UPPER_TARGET_ADDR

◆ DW_IATU_UR_REG

◆ DW_IATU_UR_STEP

◆ DW_IATU_VIEWPORT

◆ DW_MISC_CONTROL_1

◆ DW_MSI_ADDR_HI

◆ DW_MSI_ADDR_LO

◆ DW_MSI_INTR0_ENABLE

◆ DW_MSI_INTR0_MASK

◆ DW_MSI_INTR0_STATUS

◆ DW_PORT_LINK_CTRL

◆ GEN2_CTRL_NUM_OF_LANES

◆ GEN2_CTRL_NUM_OF_LANES_1

◆ GEN2_CTRL_NUM_OF_LANES_16

◆ GEN2_CTRL_NUM_OF_LANES_2

◆ GEN2_CTRL_NUM_OF_LANES_32

◆ GEN2_CTRL_NUM_OF_LANES_4

◆ GEN2_CTRL_NUM_OF_LANES_8

◆ IATU_CTRL1_TYPE

◆ IATU_CTRL1_TYPE_CFG0

◆ IATU_CTRL1_TYPE_CFG1

◆ IATU_CTRL1_TYPE_IO

◆ IATU_CTRL1_TYPE_MEM

◆ IATU_CTRL2_REGION_EN

◆ IATU_REGION_INBOUND

◆ IATU_REGION_INDEX

◆ IATU_UR_CTRL1

◆ IATU_UR_CTRL2

◆ IATU_UR_LIMIT_ADDR

◆ IATU_UR_LWR_BASE_ADDR

◆ IATU_UR_LWR_TARGET_ADDR

◆ IATU_UR_UPPER_BASE_ADDR

◆ IATU_UR_UPPER_TARGET_ADDR

◆ PORT_LINK_CAPABLE

◆ PORT_LINK_CAPABLE_1

◆ PORT_LINK_CAPABLE_16

◆ PORT_LINK_CAPABLE_2

◆ PORT_LINK_CAPABLE_32

◆ PORT_LINK_CAPABLE_4

◆ PORT_LINK_CAPABLE_8

Function Documentation

◆ DECLARE_CLASS()

◆ pci_dw_dbi_rd1()

◆ pci_dw_dbi_rd2()

◆ pci_dw_dbi_rd4()

◆ pci_dw_dbi_wr1()

◆ pci_dw_dbi_wr2()

◆ pci_dw_dbi_wr4()

◆ pci_dw_init()