FreeBSD kernel CXGBE device code
t4_l2t.h
Go to the documentation of this file.
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 *
30 */
31
32#ifndef __T4_L2T_H
33#define __T4_L2T_H
34
35/* identifies sync vs async L2T_WRITE_REQs */
36#define S_SYNC_WR 12
37#define V_SYNC_WR(x) ((x) << S_SYNC_WR)
38#define F_SYNC_WR V_SYNC_WR(1)
39
40enum { L2T_SIZE = 4096 }; /* # of L2T entries */
41
42enum {
43 L2T_STATE_VALID, /* entry is up to date */
44 L2T_STATE_STALE, /* entry may be used but needs revalidation */
45 L2T_STATE_RESOLVING, /* entry needs address resolution */
46 L2T_STATE_FAILED, /* failed to resolve */
47 L2T_STATE_SYNC_WRITE, /* synchronous write of entry underway */
48
49 /* when state is one of the below the entry is not hashed */
50 L2T_STATE_SWITCHING, /* entry is being used by a switching filter */
51 L2T_STATE_TLS, /* entry is being used by TLS sessions */
52 L2T_STATE_UNUSED /* entry not in use */
53};
54
55/*
56 * Each L2T entry plays multiple roles. First of all, it keeps state for the
57 * corresponding entry of the HW L2 table and maintains a queue of offload
58 * packets awaiting address resolution. Second, it is a node of a hash table
59 * chain, where the nodes of the chain are linked together through their next
60 * pointer. Finally, each node is a bucket of a hash table, pointing to the
61 * first element in its chain through its first pointer.
62 */
63struct l2t_entry {
64 uint16_t state; /* entry state */
65 uint16_t idx; /* entry index */
66 uint32_t addr[4]; /* next hop IP or IPv6 address */
67 uint32_t iqid; /* iqid for reply to write_l2e */
68 struct sge_wrq *wrq; /* queue to use for write_l2e */
69 struct ifnet *ifp; /* outgoing interface */
70 uint16_t smt_idx; /* SMT index */
71 uint16_t vlan; /* VLAN TCI (id: 0-11, prio: 13-15) */
72 struct l2t_entry *first; /* start of hash chain */
73 struct l2t_entry *next; /* next l2t_entry on chain */
74 STAILQ_HEAD(, wrqe) wr_list; /* list of WRs awaiting resolution */
75 struct mtx lock;
76 volatile int refcnt; /* entry reference count */
77 uint16_t hash; /* hash bucket the entry is on */
78 uint8_t ipv6; /* entry is for an IPv6 address */
79 uint8_t lport; /* associated offload logical port */
80 uint8_t dmac[ETHER_ADDR_LEN]; /* next hop's MAC address */
81};
82
83struct l2t_data {
84 struct rwlock lock;
85 u_int l2t_size;
86 volatile int nfree; /* number of free entries */
87 struct l2t_entry *rover;/* starting point for next allocation */
88 struct l2t_entry l2tab[];
89};
90
91
92int t4_init_l2t(struct adapter *, int);
93int t4_free_l2t(struct l2t_data *);
94struct l2t_entry *t4_alloc_l2e(struct l2t_data *);
95struct l2t_entry *t4_l2t_alloc_switching(struct adapter *, uint16_t, uint8_t,
96 uint8_t *);
97struct l2t_entry *t4_l2t_alloc_tls(struct adapter *, struct sge_txq *,
98 void *, int *, uint16_t, uint8_t, uint8_t *);
99int t4_l2t_set_switching(struct adapter *, struct l2t_entry *, uint16_t,
100 uint8_t, uint8_t *);
101int t4_write_l2e(struct l2t_entry *, int);
102int do_l2t_write_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
103
104static inline void
106{
107 struct l2t_data *d = __containerof(e, struct l2t_data, l2tab[e->idx]);
108
109 if (atomic_fetchadd_int(&e->refcnt, -1) == 1)
110 atomic_add_int(&d->nfree, 1);
111}
112
113int sysctl_l2t(SYSCTL_HANDLER_ARGS);
114
115#endif /* __T4_L2T_H */
volatile int nfree
Definition: t4_l2t.h:86
u_int l2t_size
Definition: t4_l2t.h:85
struct l2t_entry * rover
Definition: t4_l2t.h:87
struct l2t_entry l2tab[]
Definition: t4_l2t.h:88
struct rwlock lock
Definition: t4_l2t.h:84
Definition: t4_l2t.h:63
struct ifnet * ifp
Definition: t4_l2t.h:69
uint32_t addr[4]
Definition: t4_l2t.h:66
struct l2t_entry * first
Definition: t4_l2t.h:72
uint16_t smt_idx
Definition: t4_l2t.h:70
uint16_t state
Definition: t4_l2t.h:64
uint32_t iqid
Definition: t4_l2t.h:67
uint8_t ipv6
Definition: t4_l2t.h:78
uint16_t hash
Definition: t4_l2t.h:77
struct mtx lock
Definition: t4_l2t.h:75
STAILQ_HEAD(, wrqe) wr_list
uint8_t lport
Definition: t4_l2t.h:79
uint8_t dmac[ETHER_ADDR_LEN]
Definition: t4_l2t.h:80
uint16_t idx
Definition: t4_l2t.h:65
uint16_t vlan
Definition: t4_l2t.h:71
struct l2t_entry * next
Definition: t4_l2t.h:73
struct sge_wrq * wrq
Definition: t4_l2t.h:68
volatile int refcnt
Definition: t4_l2t.h:76
Definition: adapter.h:696
int do_l2t_write_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *)
Definition: t4_l2t.c:371
int t4_write_l2e(struct l2t_entry *, int)
Definition: t4_l2t.c:171
int t4_init_l2t(struct adapter *, int)
Definition: t4_l2t.c:323
int sysctl_l2t(SYSCTL_HANDLER_ARGS)
Definition: t4_l2t.c:409
static void t4_l2t_release(struct l2t_entry *e)
Definition: t4_l2t.h:105
@ L2T_STATE_TLS
Definition: t4_l2t.h:51
@ L2T_STATE_RESOLVING
Definition: t4_l2t.h:45
@ L2T_STATE_FAILED
Definition: t4_l2t.h:46
@ L2T_STATE_STALE
Definition: t4_l2t.h:44
@ L2T_STATE_SWITCHING
Definition: t4_l2t.h:50
@ L2T_STATE_SYNC_WRITE
Definition: t4_l2t.h:47
@ L2T_STATE_UNUSED
Definition: t4_l2t.h:52
@ L2T_STATE_VALID
Definition: t4_l2t.h:43
int t4_free_l2t(struct l2t_data *)
Definition: t4_l2t.c:358
@ L2T_SIZE
Definition: t4_l2t.h:40
struct l2t_entry * t4_l2t_alloc_switching(struct adapter *, uint16_t, uint8_t, uint8_t *)
Definition: t4_l2t.c:288
struct l2t_entry * t4_l2t_alloc_tls(struct adapter *, struct sge_txq *, void *, int *, uint16_t, uint8_t, uint8_t *)
Definition: t4_l2t.c:212
int t4_l2t_set_switching(struct adapter *, struct l2t_entry *, uint16_t, uint8_t, uint8_t *)
struct l2t_entry * t4_alloc_l2e(struct l2t_data *)
Definition: t4_l2t.c:73