37#define msleep t3_os_sleep
63#define AQBIT(x) (1 << (0x##x))
64#define ADV_1G_FULL AQBIT(f)
65#define ADV_1G_HALF AQBIT(e)
66#define ADV_10G_FULL AQBIT(c)
68#define AQ_WRITE_REGS(phy, regs) do { \
70 for (i = 0; i < ARRAY_SIZE(regs); i++) { \
71 (void) mdio_write(phy, regs[i].mmd, regs[i].reg, regs[i].val); \
74#define AQ_READ_REGS(phy, regs) do { \
76 for (i = 0; i < ARRAY_SIZE(regs); i++) { \
77 (void) mdio_read(phy, regs[i].mmd, regs[i].reg, &v); \
90 v == 0xffff || (v & 1) != 1)
96 return ((
int)((
signed char)(v >> 8)));
171 unsigned int cause, v;
177 if (cause &
AQBIT(2)) {
197 " (0x%x)\n",
phy->
addr, cause);
213 if (cause &
AQBIT(0)) {
234 off ? BMCR_PDOWN : 0);
246 }
while (v && --wait);
358 unsigned int v, link = 0;
363 if (v == 0xffff || !(v & 1))
400 unsigned int lpa, adv;
469 unsigned int v, v2, gpio, wait;
493 if (err || v == 0xffff) {
505 }
while (v && --wait);
521 if ((v & BMCR_PDOWN) == 0)
531 if (v != 0x1b || v2 != 0x1b)
533 "(0x%x, 0x%x).\n", phy_addr, v, v2);
536 if ((v & 0xf) != 0xf)
538 "(0x%x).\n", phy_addr, v);
static int aq100x_autoneg_enable(struct cphy *phy)
static struct cphy_ops aq100x_ops
int t3_aq100x_phy_prep(pinfo_t *pinfo, int phy_addr, const struct mdio_ops *mdio_ops)
#define AQ_WRITE_REGS(phy, regs)
static int aq100x_intr_clear(struct cphy *phy)
static int aq100x_vendor_intr(struct cphy *phy, int *rc)
static int aq100x_power_down(struct cphy *phy, int off)
#define AQ_READ_REGS(phy, regs)
static int aq100x_temperature(struct cphy *phy)
static int aq100x_set_loopback(struct cphy *phy, int mmd, int dir, int enable)
static int aq100x_autoneg_restart(struct cphy *phy)
static int aq100x_set_speed_duplex(struct cphy *phy, int speed, int duplex)
static int aq100x_intr_disable(struct cphy *phy)
static int aq100x_intr_enable(struct cphy *phy)
static int aq100x_get_link_status(struct cphy *phy, int *link_state, int *speed, int *duplex, int *fc)
static int aq100x_intr_handler(struct cphy *phy)
static int aq100x_advertise(struct cphy *phy, unsigned int advertise_map)
static int aq100x_set_defaults(struct cphy *phy)
static int aq100x_reset(struct cphy *phy, int wait)
static int mdio_read(struct cphy *phy, int mmd, int reg, unsigned int *valp)
void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val)
int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, unsigned int set)
int t3_phy_reset(struct cphy *phy, int mmd, int wait)
static int mdio_write(struct cphy *phy, int mmd, int reg, unsigned int val)
static void cphy_init(struct cphy *phy, adapter_t *adapter, pinfo_t *pinfo, int phy_addr, struct cphy_ops *phy_ops, const struct mdio_ops *mdio_ops, unsigned int caps, const char *desc)
#define ADVERTISED_1000baseT_Full
#define ADVERTISED_10000baseT_Full
#define ADVERTISE_PAUSE_ASYM
#define ADVERTISE_100FULL
#define SUPPORTED_10000baseT_Full
#define SUPPORTED_Autoneg
#define ADVERTISED_100baseT_Half
#define ADVERTISED_100baseT_Full
#define SUPPORTED_1000baseT_Full
#define ADVERTISED_1000baseT_Half
#define ADVERTISE_100HALF
#define CH_WARN(adap, fmt,...)
#define ADVERTISED_Asym_Pause
#define ADVERTISE_PAUSE_CAP
int(* reset)(struct cphy *phy, int wait)