190#define V_OPCODE(x) ((x) << S_OPCODE)
191#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
192#define G_TID(x) ((x) & 0xFFFFFF)
195#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
197#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
200#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
205#if defined(__LITTLE_ENDIAN_BITFIELD)
220#if defined(__LITTLE_ENDIAN_BITFIELD)
232#define M_HASHTYPE 0x3
233#define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
237#define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
252#define wrh_hi u.ilp32.wr_hi
253#define wrh_lo u.ilp32.wr_lo
254#define wrh_hilo u.lp64.wr_hilo
257#define S_WR_SGE_CREDITS 0
258#define M_WR_SGE_CREDITS 0xFF
259#define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
260#define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)
262#define S_WR_SGLSFLT 8
263#define M_WR_SGLSFLT 0xFF
264#define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
265#define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)
267#define S_WR_BCNTLFLT 16
268#define M_WR_BCNTLFLT 0xF
269#define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
270#define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
276#define S_WR_ATOMIC 16
277#define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC)
278#define F_WR_ATOMIC V_WR_ATOMIC(1U)
285#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH)
286#define F_WR_FLUSH V_WR_FLUSH(1U)
289#define V_WR_CHN(x) ((x) << S_WR_CHN)
290#define F_WR_CHN V_WR_CHN(1U)
292#define S_WR_CHN_VLD 19
293#define V_WR_CHN_VLD(x) ((x) << S_WR_CHN_VLD)
294#define F_WR_CHN_VLD V_WR_CHN_VLD(1U)
296#define S_WR_DATATYPE 20
297#define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
298#define F_WR_DATATYPE V_WR_DATATYPE(1U)
301#define V_WR_COMPL(x) ((x) << S_WR_COMPL)
302#define F_WR_COMPL V_WR_COMPL(1U)
305#define V_WR_EOP(x) ((x) << S_WR_EOP)
306#define F_WR_EOP V_WR_EOP(1U)
309#define V_WR_SOP(x) ((x) << S_WR_SOP)
310#define F_WR_SOP V_WR_SOP(1U)
314#define V_WR_OP(x) ((x) << S_WR_OP)
315#define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
320#define V_WR_LEN(x) ((x) << S_WR_LEN)
321#define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)
324#define M_WR_TID 0xFFFFF
325#define V_WR_TID(x) ((x) << S_WR_TID)
326#define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)
328#define S_WR_CR_FLUSH 30
329#define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
330#define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U)
333#define V_WR_GEN(x) ((x) << S_WR_GEN)
334#define F_WR_GEN V_WR_GEN(1U)
335#define G_WR_GEN(x) ((x) >> S_WR_GEN)
337# define WR_HDR struct work_request_hdr wr
341# define RSS_HDR struct rss_header rss_hdr;
345#define S_CPL_STATUS 0
346#define M_CPL_STATUS 0xFF
347#define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
348#define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)
350#define S_INJECT_TIMER 6
351#define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
352#define F_INJECT_TIMER V_INJECT_TIMER(1U)
354#define S_NO_OFFLOAD 7
355#define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
356#define F_NO_OFFLOAD V_NO_OFFLOAD(1U)
359#define M_ULP_MODE 0xF
360#define V_ULP_MODE(x) ((x) << S_ULP_MODE)
361#define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
363#define S_RCV_BUFSIZ 12
364#define M_RCV_BUFSIZ 0x3FFF
365#define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
366#define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
370#define V_TOS(x) ((x) << S_TOS)
371#define G_TOS(x) (((x) >> S_TOS) & M_TOS)
375#define V_DELACK(x) ((x) << S_DELACK)
376#define F_DELACK V_DELACK(1U)
379#define V_NO_CONG(x) ((x) << S_NO_CONG)
380#define F_NO_CONG V_NO_CONG(1U)
382#define S_SRC_MAC_SEL 2
383#define M_SRC_MAC_SEL 0x3
384#define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
385#define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)
388#define M_L2T_IDX 0x7FF
389#define V_L2T_IDX(x) ((x) << S_L2T_IDX)
390#define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
392#define S_TX_CHANNEL 15
393#define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
394#define F_TX_CHANNEL V_TX_CHANNEL(1U)
396#define S_TCAM_BYPASS 16
397#define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
398#define F_TCAM_BYPASS V_TCAM_BYPASS(1U)
401#define V_NAGLE(x) ((x) << S_NAGLE)
402#define F_NAGLE V_NAGLE(1U)
404#define S_WND_SCALE 18
405#define M_WND_SCALE 0xF
406#define V_WND_SCALE(x) ((x) << S_WND_SCALE)
407#define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
409#define S_KEEP_ALIVE 22
410#define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
411#define F_KEEP_ALIVE V_KEEP_ALIVE(1U)
413#define S_MAX_RETRANS 23
414#define M_MAX_RETRANS 0xF
415#define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
416#define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)
418#define S_MAX_RETRANS_OVERRIDE 27
419#define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
420#define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U)
424#define V_MSS_IDX(x) ((x) << S_MSS_IDX)
425#define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
428#define S_RSS_ENABLE 0
429#define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
430#define F_RSS_ENABLE V_RSS_ENABLE(1U)
432#define S_RSS_MASK_LEN 1
433#define M_RSS_MASK_LEN 0x7
434#define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
435#define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
438#define M_CPU_IDX 0x3F
439#define V_CPU_IDX(x) ((x) << S_CPU_IDX)
440#define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
443#define M_OPT1_VLAN 0xFFF
444#define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN)
445#define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN)
447#define S_MAC_MATCH_VALID 18
448#define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
449#define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U)
451#define S_CONN_POLICY 19
452#define M_CONN_POLICY 0x3
453#define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
454#define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
456#define S_SYN_DEFENSE 21
457#define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
458#define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
461#define M_VLAN_PRI 0x3
462#define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
463#define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)
465#define S_VLAN_PRI_VALID 24
466#define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
467#define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U)
470#define M_PKT_TYPE 0x3
471#define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
472#define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)
474#define S_MAC_MATCH 27
475#define M_MAC_MATCH 0x1F
476#define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
477#define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)
481#define M_CPU_INDEX 0x7F
482#define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
483#define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)
485#define S_CPU_INDEX_VALID 7
486#define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
487#define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U)
489#define S_RX_COALESCE 8
490#define M_RX_COALESCE 0x3
491#define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
492#define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
494#define S_RX_COALESCE_VALID 10
495#define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
496#define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
498#define S_CONG_CONTROL_FLAVOR 11
499#define M_CONG_CONTROL_FLAVOR 0x3
500#define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
501#define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)
503#define S_PACING_FLAVOR 13
504#define M_PACING_FLAVOR 0x3
505#define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
506#define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)
508#define S_FLAVORS_VALID 15
509#define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
510#define F_FLAVORS_VALID V_FLAVORS_VALID(1U)
512#define S_RX_FC_DISABLE 16
513#define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
514#define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
516#define S_RX_FC_VALID 17
517#define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
518#define F_RX_FC_VALID V_RX_FC_VALID(1U)
559#define S_PASS_OPEN_TID 0
560#define M_PASS_OPEN_TID 0xFFFFFF
561#define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
562#define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
564#define S_PASS_OPEN_TOS 24
565#define M_PASS_OPEN_TOS 0xFF
566#define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
567#define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
571#define M_L2T_IDX16 0x7FF
572#define V_L2T_IDX16(x) ((x) << S_L2T_IDX16)
573#define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16)
576#define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
577#define G_TCPOPT_SACK(x) (((x) >> 6) & 1)
578#define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
579#define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
580#define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
594#if defined(__LITTLE_ENDIAN_BITFIELD)
634#define S_AOPEN_VLAN_PRI 9
635#define M_AOPEN_VLAN_PRI 0x3
636#define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
637#define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
639#define S_AOPEN_VLAN_PRI_VALID 11
640#define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
641#define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U)
643#define S_AOPEN_PKT_TYPE 12
644#define M_AOPEN_PKT_TYPE 0x3
645#define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
646#define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
648#define S_AOPEN_MAC_MATCH 14
649#define M_AOPEN_MAC_MATCH 0x1F
650#define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
651#define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
653#define S_AOPEN_MAC_MATCH_VALID 19
654#define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
655#define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U)
657#define S_AOPEN_IFF_VLAN 20
658#define M_AOPEN_IFF_VLAN 0xFFF
659#define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
660#define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
713#define V_NO_REPLY(x) ((x) << S_NO_REPLY)
714#define F_NO_REPLY V_NO_REPLY(1U)
737#if defined(__LITTLE_ENDIAN_BITFIELD)
840#define S_TX_ACK_PAGES 21
841#define M_TX_ACK_PAGES 0x7
842#define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
843#define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
848#define V_TX_PORT(x) ((x) << S_TX_PORT)
849#define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
853#define V_TX_MSS(x) ((x) << S_TX_MSS)
854#define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
858#define V_TX_QOS(x) ((x) << S_TX_QOS)
859#define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
861#define S_TX_SNDBUF 16
862#define M_TX_SNDBUF 0xFFFF
863#define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
864#define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
875#define S_TX_ULP_SUBMODE 6
876#define M_TX_ULP_SUBMODE 0xF
877#define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
878#define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
880#define S_TX_ULP_MODE 10
881#define M_TX_ULP_MODE 0xF
882#define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
883#define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
886#define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
887#define F_TX_SHOVE V_TX_SHOVE(1U)
890#define V_TX_MORE(x) ((x) << S_TX_MORE)
891#define F_TX_MORE V_TX_MORE(1U)
894#define S_TX_CPU_IDX 0
895#define M_TX_CPU_IDX 0x3F
896#define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
897#define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
900#define V_TX_URG(x) ((x) << S_TX_URG)
901#define F_TX_URG V_TX_URG(1U)
904#define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
905#define F_TX_CLOSE V_TX_CLOSE(1U)
908#define V_TX_INIT(x) ((x) << S_TX_INIT)
909#define F_TX_INIT V_TX_INIT(1U)
911#define S_TX_IMM_ACK 19
912#define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
913#define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
915#define S_TX_IMM_DMA 20
916#define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
917#define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
973#define S_ISCSI_PDU_LEN 0
974#define M_ISCSI_PDU_LEN 0x7FFF
975#define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
976#define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
978#define S_ISCSI_DDP 15
979#define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
980#define F_ISCSI_DDP V_ISCSI_DDP(1U)
989#if defined(__LITTLE_ENDIAN_BITFIELD)
1012#define S_RX_CREDITS 0
1013#define M_RX_CREDITS 0x7FFFFFF
1014#define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
1015#define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
1017#define S_RX_MODULATE 27
1018#define V_RX_MODULATE(x) ((x) << S_RX_MODULATE)
1019#define F_RX_MODULATE V_RX_MODULATE(1U)
1021#define S_RX_FORCE_ACK 28
1022#define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
1023#define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
1025#define S_RX_DACK_MODE 29
1026#define M_RX_DACK_MODE 0x3
1027#define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
1028#define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
1030#define S_RX_DACK_CHANGE 31
1031#define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
1032#define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
1061#define S_DDP_STATUS 0
1062#define M_DDP_STATUS 0xFF
1063#define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
1064#define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS)
1066#define S_DDP_VALID 15
1067#define M_DDP_VALID 0x1FFFF
1068#define V_DDP_VALID(x) ((x) << S_DDP_VALID)
1069#define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
1071#define S_DDP_PPOD_MISMATCH 15
1072#define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1073#define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
1076#define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1077#define F_DDP_PDU V_DDP_PDU(1U)
1079#define S_DDP_LLIMIT_ERR 17
1080#define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1081#define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
1083#define S_DDP_PPOD_PARITY_ERR 18
1084#define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1085#define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
1087#define S_DDP_PADDING_ERR 19
1088#define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1089#define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
1091#define S_DDP_HDRCRC_ERR 20
1092#define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1093#define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
1095#define S_DDP_DATACRC_ERR 21
1096#define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1097#define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
1099#define S_DDP_INVALID_TAG 22
1100#define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1101#define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
1103#define S_DDP_ULIMIT_ERR 23
1104#define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1105#define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
1107#define S_DDP_OFFSET_ERR 24
1108#define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1109#define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
1111#define S_DDP_COLOR_ERR 25
1112#define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1113#define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
1115#define S_DDP_TID_MISMATCH 26
1116#define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1117#define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
1119#define S_DDP_INVALID_PPOD 27
1120#define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1121#define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
1123#define S_DDP_ULP_MODE 28
1124#define M_DDP_ULP_MODE 0xF
1125#define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1126#define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1129#define S_DDP_OFFSET 0
1130#define M_DDP_OFFSET 0x3FFFFF
1131#define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1132#define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1134#define S_DDP_DACK_MODE 22
1135#define M_DDP_DACK_MODE 0x3
1136#define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
1137#define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE)
1140#define V_DDP_URG(x) ((x) << S_DDP_URG)
1141#define F_DDP_URG V_DDP_URG(1U)
1144#define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1145#define F_DDP_PSH V_DDP_PSH(1U)
1147#define S_DDP_BUF_COMPLETE 26
1148#define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1149#define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
1151#define S_DDP_BUF_TIMED_OUT 27
1152#define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1153#define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
1155#define S_DDP_BUF_IDX 28
1156#define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1157#define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1198#define S_TXPKT_VLAN 0
1199#define M_TXPKT_VLAN 0xFFFF
1200#define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN)
1201#define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1203#define S_TXPKT_INTF 16
1204#define M_TXPKT_INTF 0xF
1205#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1206#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1208#define S_TXPKT_IPCSUM_DIS 20
1209#define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS)
1210#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U)
1212#define S_TXPKT_L4CSUM_DIS 21
1213#define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS)
1214#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U)
1216#define S_TXPKT_VLAN_VLD 22
1217#define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD)
1218#define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U)
1220#define S_TXPKT_LOOPBACK 23
1221#define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1222#define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1224#define S_TXPKT_OPCODE 24
1225#define M_TXPKT_OPCODE 0xFF
1226#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1227#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1231#define M_LSO_MSS 0x3FFF
1232#define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1233#define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1235#define S_LSO_ETH_TYPE 14
1236#define M_LSO_ETH_TYPE 0x3
1237#define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE)
1238#define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE)
1240#define S_LSO_TCPHDR_WORDS 16
1241#define M_LSO_TCPHDR_WORDS 0xF
1242#define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS)
1243#define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS)
1245#define S_LSO_IPHDR_WORDS 20
1246#define M_LSO_IPHDR_WORDS 0xF
1247#define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS)
1248#define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS)
1250#define S_LSO_IPV6 24
1251#define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1252#define F_LSO_IPV6 V_LSO_IPV6(1U)
1257#if defined(__LITTLE_ENDIAN_BITFIELD)
1265#if defined(__LITTLE_ENDIAN_BITFIELD)
1276#if defined(__LITTLE_ENDIAN_BITFIELD)
1290#if defined(__LITTLE_ENDIAN_BITFIELD)
1318#define S_L2T_W_IDX 0
1319#define M_L2T_W_IDX 0x7FF
1320#define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1321#define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)
1323#define S_L2T_W_VLAN 11
1324#define M_L2T_W_VLAN 0xFFF
1325#define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN)
1326#define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN)
1328#define S_L2T_W_IFF 23
1329#define M_L2T_W_IFF 0xF
1330#define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF)
1331#define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF)
1333#define S_L2T_W_PRIO 27
1334#define M_L2T_W_PRIO 0x7
1335#define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO)
1336#define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO)
1361#define S_L2T_R_PRIO 0
1362#define M_L2T_R_PRIO 0x7
1363#define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO)
1364#define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO)
1366#define S_L2T_R_VLAN 8
1367#define M_L2T_R_VLAN 0xFFF
1368#define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN)
1369#define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN)
1371#define S_L2T_R_IFF 20
1372#define M_L2T_R_IFF 0xF
1373#define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF)
1374#define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF)
1376#define S_L2T_STATUS 24
1377#define M_L2T_STATUS 0xFF
1378#define V_L2T_STATUS(x) ((x) << S_L2T_STATUS)
1379#define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS)
1385#if defined(__LITTLE_ENDIAN_BITFIELD)
1410#if defined(__LITTLE_ENDIAN_BITFIELD)
1424#if defined(__LITTLE_ENDIAN_BITFIELD)
1445#define S_RTE_REQ_LUT_IX 8
1446#define M_RTE_REQ_LUT_IX 0x7FF
1447#define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1448#define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1450#define S_RTE_REQ_LUT_BASE 19
1451#define M_RTE_REQ_LUT_BASE 0x7FF
1452#define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1453#define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1455#define S_RTE_READ_REQ_SELECT 31
1456#define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1457#define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
1469#if defined(__LITTLE_ENDIAN_BITFIELD)
1487#define S_RTE_WRITE_REQ_LUT_IX 10
1488#define M_RTE_WRITE_REQ_LUT_IX 0x7FF
1489#define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX)
1490#define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX)
1492#define S_RTE_WRITE_REQ_LUT_BASE 21
1493#define M_RTE_WRITE_REQ_LUT_BASE 0x7FF
1494#define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE)
1495#define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE)
1516#if defined(__LITTLE_ENDIAN_BITFIELD)
1548#if defined(__LITTLE_ENDIAN_BITFIELD)
1564#define M_FLIT_CNT 0xFF
1565#define V_FLIT_CNT(x) ((x) << S_FLIT_CNT)
1566#define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT)
1569#define M_TERM_TID 0xFFFFF
1570#define V_TERM_TID(x) ((x) << S_TERM_TID)
1571#define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1576#define S_ULPTX_CMD 28
1577#define M_ULPTX_CMD 0xF
1578#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
1580#define S_ULPTX_NFLITS 0
1581#define M_ULPTX_NFLITS 0xFF
1582#define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1591#define S_ULP_MEMIO_ADDR 0
1592#define M_ULP_MEMIO_ADDR 0x7FFFFFF
1593#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1595#define S_ULP_MEMIO_LOCK 27
1596#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1597#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
1600#define S_ULP_MEMIO_DATA_LEN 28
1601#define M_ULP_MEMIO_DATA_LEN 0xF
1602#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1610#define S_ULP_TXPKT_DEST 24
1611#define M_ULP_TXPKT_DEST 0xF
1612#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
@ CPL_ERR_FINWAIT2_TIMEDOUT
@ CPL_ERR_KEEPALIVE_TIMEDOUT
@ CPL_ERR_PERSIST_NEG_ADVICE
@ CPL_ERR_PERSIST_TIMEDOUT
@ CPL_ABORT_POST_CLOSE_REQ
@ CPL_PASS_OPEN_ACCEPT_TNL
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
union cpl_rx_data_ddp::@44 u
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
RSS_HDR union opcode_tid ot
struct cpl_tx_pkt_batch_entry pkt_entry[7]
RSS_HDR union opcode_tid ot
struct cpl_tx_pkt_coalesce cpl[0]
struct work_request_hdr::@41::@43 lp64
union work_request_hdr::@41 u
struct work_request_hdr::@41::@42 ilp32