FreeBSD kernel ATH device code
amrr.h
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1/*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2004 INRIA
5 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer,
13 without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
16 * redistribution must be conditioned upon including a substantially
17 * similar Disclaimer requirement for further binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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39 * $FreeBSD$
40 */
41
42#ifndef _DEV_ATH_RATE_AMRR_H
43#define _DEV_ATH_RATE_AMRR_H
44
45/* per-device state */
46struct amrr_softc {
47 struct ath_ratectrl arc; /* base state */
48};
49
50/* per-node state */
51struct amrr_node {
52 int amn_rix; /* current rate index */
53 int amn_ticks; /* time of last update */
54 int amn_interval; /* update interval (ticks) */
55 /* AMRR statistics for this node */
61 /* AMRR algorithm state for this node */
65 /* rate index et al. */
66 u_int8_t amn_tx_rix0; /* series 0 rate index */
67 u_int8_t amn_tx_rate0; /* series 0 h/w rate */
68 u_int8_t amn_tx_rate1; /* series 1 h/w rate */
69 u_int8_t amn_tx_rate2; /* series 2 h/w rate */
70 u_int8_t amn_tx_rate3; /* series 3 h/w rate */
71 u_int8_t amn_tx_rate0sp; /* series 0 short preamble h/w rate */
72 u_int8_t amn_tx_rate1sp; /* series 1 short preamble h/w rate */
73 u_int8_t amn_tx_rate2sp; /* series 2 short preamble h/w rate */
74 u_int8_t amn_tx_rate3sp; /* series 3 short preamble h/w rate */
75 u_int8_t amn_tx_try0; /* series 0 try count */
76 u_int amn_tx_try1; /* series 1 try count */
77 u_int amn_tx_try2; /* series 2 try count */
78 u_int amn_tx_try3; /* series 3 try count */
79};
80#define ATH_NODE_AMRR(an) ((struct amrr_node *)&an[1])
81#endif /* _DEV_ATH_RATE_AMRR_H */
Definition: amrr.h:51
u_int8_t amn_tx_try0
Definition: amrr.h:75
u_int amn_tx_try2
Definition: amrr.h:77
u_int amn_success
Definition: amrr.h:63
u_int8_t amn_tx_rate0sp
Definition: amrr.h:71
u_int8_t amn_tx_rate3
Definition: amrr.h:70
u_int amn_recovery
Definition: amrr.h:64
u_int8_t amn_tx_rate2
Definition: amrr.h:69
u_int amn_tx_try1
Definition: amrr.h:76
u_int amn_tx_try2_cnt
Definition: amrr.h:58
u_int8_t amn_tx_rate1
Definition: amrr.h:68
u_int amn_tx_try3_cnt
Definition: amrr.h:59
u_int8_t amn_tx_rate1sp
Definition: amrr.h:72
int amn_ticks
Definition: amrr.h:53
u_int amn_tx_try0_cnt
Definition: amrr.h:56
u_int amn_tx_failure_cnt
Definition: amrr.h:60
u_int8_t amn_tx_rix0
Definition: amrr.h:66
int amn_rix
Definition: amrr.h:52
u_int amn_success_threshold
Definition: amrr.h:62
u_int amn_tx_try3
Definition: amrr.h:78
int amn_interval
Definition: amrr.h:54
u_int8_t amn_tx_rate3sp
Definition: amrr.h:74
u_int8_t amn_tx_rate2sp
Definition: amrr.h:73
u_int8_t amn_tx_rate0
Definition: amrr.h:67
u_int amn_tx_try1_cnt
Definition: amrr.h:57
struct ath_ratectrl arc
Definition: amrr.h:47