FreeBSD kernel sound device code
cs4281.c
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1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * The order of pokes in the initiation sequence is based on Linux
31 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom
32 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org)
33 * contributed towards power management.
34 */
35
36#ifdef HAVE_KERNEL_OPTION_HEADERS
37#include "opt_snd.h"
38#endif
39
40#include <dev/sound/pcm/sound.h>
41#include <dev/sound/pcm/ac97.h>
42
43#include <dev/pci/pcireg.h>
44#include <dev/pci/pcivar.h>
45
47
48SND_DECLARE_FILE("$FreeBSD$");
49
50#define CS4281_DEFAULT_BUFSZ 16384
51
52/* Max fifo size for full duplex is 64 */
53#define CS4281_FIFO_SIZE 15
54
55/* DMA Engine Indices */
56#define CS4281_DMA_PLAY 0
57#define CS4281_DMA_REC 1
58
59/* Misc */
60
61#define inline __inline
62
63#ifndef DEB
64#define DEB(x) /* x */
65#endif /* DEB */
66
67/* ------------------------------------------------------------------------- */
68/* Structures */
69
70struct sc_info;
71
72/* channel registers */
73struct sc_chinfo {
74 struct sc_info *parent;
75
76 struct snd_dbuf *buffer;
77 struct pcm_channel *channel;
78
79 u_int32_t spd, fmt, bps, blksz;
80
82};
83
84/* device private data */
85struct sc_info {
86 device_t dev;
87 u_int32_t type;
88
89 bus_space_tag_t st;
90 bus_space_handle_t sh;
91 bus_dma_tag_t parent_dmat;
92
93 struct resource *reg, *irq, *mem;
95 void *ih;
96
97 int power;
98 unsigned long bufsz;
99 struct sc_chinfo pch;
101};
102
103/* -------------------------------------------------------------------- */
104/* prototypes */
105
106/* ADC/DAC control */
107static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go);
108static void adcdac_prog(struct sc_chinfo *ch);
109
110/* power management and interrupt control */
111static void cs4281_intr(void *);
112static int cs4281_power(struct sc_info *, int);
113static int cs4281_init(struct sc_info *);
114
115/* talk to the card */
116static u_int32_t cs4281_rd(struct sc_info *, int);
117static void cs4281_wr(struct sc_info *, int, u_int32_t);
118
119/* misc */
120static u_int8_t cs4281_rate_to_rv(u_int32_t);
121static u_int32_t cs4281_format_to_dmr(u_int32_t);
122static u_int32_t cs4281_format_to_bps(u_int32_t);
123
124/* -------------------------------------------------------------------- */
125/* formats (do not add formats without editing cs_fmt_tab) */
126
127static u_int32_t cs4281_fmts[] = {
128 SND_FORMAT(AFMT_U8, 1, 0),
129 SND_FORMAT(AFMT_U8, 2, 0),
130 SND_FORMAT(AFMT_S8, 1, 0),
131 SND_FORMAT(AFMT_S8, 2, 0),
132 SND_FORMAT(AFMT_S16_LE, 1, 0),
133 SND_FORMAT(AFMT_S16_LE, 2, 0),
134 SND_FORMAT(AFMT_U16_LE, 1, 0),
135 SND_FORMAT(AFMT_U16_LE, 2, 0),
136 SND_FORMAT(AFMT_S16_BE, 1, 0),
137 SND_FORMAT(AFMT_S16_BE, 2, 0),
138 SND_FORMAT(AFMT_U16_BE, 1, 0),
139 SND_FORMAT(AFMT_U16_BE, 2, 0),
140 0
141};
142
143static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0};
144
145/* -------------------------------------------------------------------- */
146/* Hardware */
147
148static inline u_int32_t
149cs4281_rd(struct sc_info *sc, int regno)
150{
151 return bus_space_read_4(sc->st, sc->sh, regno);
152}
153
154static inline void
155cs4281_wr(struct sc_info *sc, int regno, u_int32_t data)
156{
157 bus_space_write_4(sc->st, sc->sh, regno, data);
158 DELAY(100);
159}
160
161static inline void
162cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask)
163{
164 u_int32_t r;
165 r = cs4281_rd(sc, regno);
166 cs4281_wr(sc, regno, r & ~mask);
167}
168
169static inline void
170cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask)
171{
172 u_int32_t v;
173 v = cs4281_rd(sc, regno);
174 cs4281_wr(sc, regno, v | mask);
175}
176
177static int
178cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries)
179{
180 u_int32_t v;
181
182 while (tries > 0) {
183 DELAY(100);
184 v = cs4281_rd(sc, regno);
185 if ((v & mask) == mask) break;
186 tries --;
187 }
188 return tries;
189}
190
191static int
192cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries)
193{
194 u_int32_t v;
195
196 while (tries > 0) {
197 DELAY(100);
198 v = ~ cs4281_rd(sc, regno);
199 if (v & mask) break;
200 tries --;
201 }
202 return tries;
203}
204
205/* ------------------------------------------------------------------------- */
206/* Register value mapping functions */
207
208static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000};
209#define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0])
210
211static u_int8_t
213{
214 u_int32_t v;
215
216 for (v = 0; v < CS4281_NUM_RATES; v++) {
217 if (rate == cs4281_rates[v]) return v;
218 }
219
220 v = 1536000 / rate;
221 if (v > 255 || v < 32) v = 5; /* default to 8k */
222 return v;
223}
224
225static u_int32_t
227{
228 u_int32_t r;
229
230 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv];
231 r = 1536000 / rv;
232 return r;
233}
234
235static inline u_int32_t
237{
238 u_int32_t dmr = 0;
240 if (AFMT_CHANNEL(format) < 2) dmr |= CS4281PCI_DMR_MONO;
242 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN;
243 return dmr;
244}
245
246static inline u_int32_t
248{
249 return ((AFMT_8BIT & format) ? 1 : 2) *
250 ((AFMT_CHANNEL(format) > 1) ? 2 : 1);
251}
252
253/* -------------------------------------------------------------------- */
254/* ac97 codec */
255
256static int
257cs4281_rdcd(kobj_t obj, void *devinfo, int regno)
258{
259 struct sc_info *sc = (struct sc_info *)devinfo;
260 int codecno;
261
262 codecno = regno >> 8;
263 regno &= 0xff;
264
265 /* Remove old state */
267
268 /* Fill in AC97 register value request form */
274
275 /* Wait for read to complete */
277 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n");
278 return -1;
279 }
280
281 /* Wait for valid status */
283 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n");
284 return -1;
285 }
286
287 return cs4281_rd(sc, CS4281PCI_ACSDA);
288}
289
290static int
291cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
292{
293 struct sc_info *sc = (struct sc_info *)devinfo;
294 int codecno;
295
296 codecno = regno >> 8;
297 regno &= 0xff;
298
303
305 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n");
306 }
307
308 return 0;
309}
310
311static kobj_method_t cs4281_ac97_methods[] = {
312 KOBJMETHOD(ac97_read, cs4281_rdcd),
313 KOBJMETHOD(ac97_write, cs4281_wrcd),
315};
316AC97_DECLARE(cs4281_ac97);
317
318/* ------------------------------------------------------------------------- */
319/* shared rec/play channel interface */
320
321static void *
322cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
323{
324 struct sc_info *sc = devinfo;
325 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
326
327 ch->buffer = b;
328 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
329 return NULL;
330 }
331 ch->parent = sc;
332 ch->channel = c;
333
334 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
336 ch->bps = 1;
337 ch->blksz = sndbuf_getsize(ch->buffer);
338
340 ch->dma_setup = 0;
341
342 adcdac_go(ch, 0);
343 adcdac_prog(ch);
344
345 return ch;
346}
347
348static u_int32_t
349cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
350{
351 struct sc_chinfo *ch = data;
352 struct sc_info *sc = ch->parent;
353 u_int32_t go;
354
355 go = adcdac_go(ch, 0);
356
357 /* 2 interrupts are possible and used in buffer (half-empty,empty),
358 * hence factor of 2. */
359 ch->blksz = MIN(blocksize, sc->bufsz / 2);
361 ch->dma_setup = 0;
363 adcdac_go(ch, go);
364
365 DEB(printf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz));
366
367 return ch->blksz;
368}
369
370static u_int32_t
371cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
372{
373 struct sc_chinfo *ch = data;
374 struct sc_info *sc = ch->parent;
375 u_int32_t go, v, r;
376
377 go = adcdac_go(ch, 0); /* pause */
380 cs4281_wr(sc, r, v);
381 adcdac_go(ch, go); /* unpause */
382
384 return ch->spd;
385}
386
387static int
388cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format)
389{
390 struct sc_chinfo *ch = data;
391 struct sc_info *sc = ch->parent;
392 u_int32_t v, go;
393
394 go = adcdac_go(ch, 0); /* pause */
395
398 else
403
404 adcdac_go(ch, go); /* unpause */
405
406 ch->fmt = format;
408 ch->dma_setup = 0;
409
410 return 0;
411}
412
413static u_int32_t
414cs4281chan_getptr(kobj_t obj, void *data)
415{
416 struct sc_chinfo *ch = data;
417 struct sc_info *sc = ch->parent;
418 u_int32_t dba, dca, ptr;
419 int sz;
420
421 sz = sndbuf_getsize(ch->buffer);
422 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan));
423 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan));
424 ptr = (dca - dba + sz) % sz;
425
426 return ptr;
427}
428
429static int
430cs4281chan_trigger(kobj_t obj, void *data, int go)
431{
432 struct sc_chinfo *ch = data;
433
434 switch(go) {
435 case PCMTRIG_START:
436 adcdac_prog(ch);
437 adcdac_go(ch, 1);
438 break;
439 case PCMTRIG_STOP:
440 case PCMTRIG_ABORT:
441 adcdac_go(ch, 0);
442 break;
443 default:
444 break;
445 }
446
447 /* return 0 if ok */
448 return 0;
449}
450
451static struct pcmchan_caps *
452cs4281chan_getcaps(kobj_t obj, void *data)
453{
454 return &cs4281_caps;
455}
456
457static kobj_method_t cs4281chan_methods[] = {
458 KOBJMETHOD(channel_init, cs4281chan_init),
459 KOBJMETHOD(channel_setformat, cs4281chan_setformat),
460 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed),
461 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize),
462 KOBJMETHOD(channel_trigger, cs4281chan_trigger),
463 KOBJMETHOD(channel_getptr, cs4281chan_getptr),
464 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps),
466};
467CHANNEL_DECLARE(cs4281chan);
468
469/* -------------------------------------------------------------------- */
470/* ADC/DAC control */
471
472/* adcdac_go enables/disable DMA channel, returns non-zero if DMA was
473 * active before call */
474
475static u_int32_t
476adcdac_go(struct sc_chinfo *ch, u_int32_t go)
477{
478 struct sc_info *sc = ch->parent;
479 u_int32_t going;
480
482
483 if (go)
485 else
487
489
490 return going;
491}
492
493static void
495{
496 struct sc_info *sc = ch->parent;
497 u_int32_t go;
498
499 if (!ch->dma_setup) {
500 go = adcdac_go(ch, 0);
504 sndbuf_getsize(ch->buffer) / ch->bps - 1);
505 ch->dma_setup = 1;
506 adcdac_go(ch, go);
507 }
508}
509
510/* -------------------------------------------------------------------- */
511/* The interrupt handler */
512
513static void
515{
516 struct sc_info *sc = (struct sc_info *)p;
517 u_int32_t hisr;
518
519 hisr = cs4281_rd(sc, CS4281PCI_HISR);
520
521 if (hisr == 0) return;
522
524 chn_intr(sc->pch.channel);
525 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */
526 }
527
529 chn_intr(sc->rch.channel);
530 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */
531 }
532
533 /* Signal End-of-Interrupt */
535}
536
537/* -------------------------------------------------------------------- */
538/* power management related */
539
540static int
541cs4281_power(struct sc_info *sc, int state)
542{
543
544 switch (state) {
545 case 0:
546 /* Permit r/w access to all BA0 registers */
548 /* Power on */
550 break;
551 case 3:
552 /* Power off card and codec */
555 break;
556 }
557
558 DEB(printf("cs4281_power %d -> %d\n", sc->power, state));
559 sc->power = state;
560
561 return 0;
562}
563
564static int
566{
567 u_int32_t i, v;
568
569 /* (0) Blast clock register and serial port */
572
573 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */
575 DELAY(50);
576
577 /* (2) Effect Reset */
579 DELAY(100);
581 /* Wait 50ms for ABITCLK to become stable */
582 DELAY(50000);
583
584 /* (3) Enable Sound System Clocks */
586 DELAY(50000); /* Wait for PLL to stabilize */
589
590 /* (4) Power Up - this combination is essential. */
594
595 /* (5) Wait for clock stabilization */
596 if (cs4281_waitset(sc,
599 250) == 0) {
600 device_printf(sc->dev, "Clock stabilization failed\n");
601 return -1;
602 }
603
604 /* (6) Enable ASYNC generation. */
606
607 /* Wait to allow AC97 to start generating clock bit */
608 DELAY(50000);
609
610 /* Set AC97 timing */
612
613 /* (7) Wait for AC97 ready signal */
615 device_printf(sc->dev, "codec did not avail\n");
616 return -1;
617 }
618
619 /* (8) Assert valid frame signal to begin sending commands to
620 * AC97 codec */
621 cs4281_wr(sc,
624
625 /* (9) Wait for codec calibration */
626 for(i = 0 ; i < 1000; i++) {
627 DELAY(10000);
628 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
629 if ((v & 0x0f) == 0x0f) {
630 break;
631 }
632 }
633 if (i == 1000) {
634 device_printf(sc->dev, "codec failed to calibrate\n");
635 return -1;
636 }
637
638 /* (10) Set AC97 timing */
640
641 /* (11) Wait for valid data to arrive */
642 if (cs4281_waitset(sc,
645 10000) == 0) {
646 device_printf(sc->dev, "cs4281 never got valid data\n");
647 return -1;
648 }
649
650 /* (12) Start digital data transfer of audio data to codec */
651 cs4281_wr(sc,
654
655 /* Set Master and headphone to max */
656 cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0);
657 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0);
658
659 /* Power on the DAC */
660 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff;
661 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
662
663 /* Wait until DAC state ready */
664 for(i = 0; i < 320; i++) {
665 DELAY(100);
666 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
667 if (v & 0x02) break;
668 }
669
670 /* Power on the ADC */
671 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff;
672 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
673
674 /* Wait until ADC state ready */
675 for(i = 0; i < 320; i++) {
676 DELAY(100);
677 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
678 if (v & 0x01) break;
679 }
680
681 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */
682 /* Play FIFO */
683
689
691
692 /* Record FIFO */
699
700 /* Match AC97 slots to FIFOs */
706
707 /* Set Auto-Initialize and set directions */
708 cs4281_wr(sc,
713 cs4281_wr(sc,
718
719 /* Enable half and empty buffer interrupts keeping DMA paused */
720 cs4281_wr(sc,
723 cs4281_wr(sc,
726
727 /* Enable Interrupts */
728 cs4281_clr4(sc,
733
734 /* Set playback volume */
737
738 return 0;
739}
740
741/* -------------------------------------------------------------------- */
742/* Probe and attach the card */
743
744static int
746{
747 char *s = NULL;
748
749 switch (pci_get_devid(dev)) {
750 case CS4281_PCI_ID:
751 s = "Crystal Semiconductor CS4281";
752 break;
753 }
754
755 if (s)
756 device_set_desc(dev, s);
757 return s ? BUS_PROBE_DEFAULT : ENXIO;
758}
759
760static int
762{
763 struct sc_info *sc;
764 struct ac97_info *codec = NULL;
765 char status[SND_STATUSLEN];
766
767 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
768 sc->dev = dev;
769 sc->type = pci_get_devid(dev);
770
771 pci_enable_busmaster(dev);
772
773 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
774 /* Reset the power state. */
775 device_printf(dev, "chip is in D%d power mode "
776 "-- setting to D0\n", pci_get_powerstate(dev));
777
778 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
779 }
780
781 sc->regid = PCIR_BAR(0);
782 sc->regtype = SYS_RES_MEMORY;
783 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid, RF_ACTIVE);
784 if (!sc->reg) {
785 sc->regtype = SYS_RES_IOPORT;
786 sc->reg = bus_alloc_resource_any(dev, sc->regtype, &sc->regid,
787 RF_ACTIVE);
788 if (!sc->reg) {
789 device_printf(dev, "unable to allocate register space\n");
790 goto bad;
791 }
792 }
793 sc->st = rman_get_bustag(sc->reg);
794 sc->sh = rman_get_bushandle(sc->reg);
795
796 sc->memid = PCIR_BAR(1);
797 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->memid,
798 RF_ACTIVE);
799 if (sc->mem == NULL) {
800 device_printf(dev, "unable to allocate fifo space\n");
801 goto bad;
802 }
803
804 sc->irqid = 0;
805 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
806 RF_ACTIVE | RF_SHAREABLE);
807 if (!sc->irq) {
808 device_printf(dev, "unable to allocate interrupt\n");
809 goto bad;
810 }
811
812 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) {
813 device_printf(dev, "unable to setup interrupt\n");
814 goto bad;
815 }
816
817 sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536);
818
819 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
820 /*boundary*/0,
821 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
822 /*highaddr*/BUS_SPACE_MAXADDR,
823 /*filter*/NULL, /*filterarg*/NULL,
824 /*maxsize*/sc->bufsz, /*nsegments*/1,
825 /*maxsegz*/0x3ffff,
826 /*flags*/0, /*lockfunc*/NULL, /*lockarg*/NULL,
827 &sc->parent_dmat) != 0) {
828 device_printf(dev, "unable to create dma tag\n");
829 goto bad;
830 }
831
832 /* power up */
833 cs4281_power(sc, 0);
834
835 /* init chip */
836 if (cs4281_init(sc) == -1) {
837 device_printf(dev, "unable to initialize the card\n");
838 goto bad;
839 }
840
841 /* create/init mixer */
842 codec = AC97_CREATE(dev, sc, cs4281_ac97);
843 if (codec == NULL)
844 goto bad;
845
847
848 if (pcm_register(dev, sc, 1, 1))
849 goto bad;
850
851 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc);
852 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc);
853
854 snprintf(status, SND_STATUSLEN, "at %s 0x%jx irq %jd %s",
855 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
856 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281));
858
859 return 0;
860
861 bad:
862 if (codec)
863 ac97_destroy(codec);
864 if (sc->reg)
865 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
866 if (sc->mem)
867 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
868 if (sc->ih)
869 bus_teardown_intr(dev, sc->irq, sc->ih);
870 if (sc->irq)
871 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
872 if (sc->parent_dmat)
873 bus_dma_tag_destroy(sc->parent_dmat);
874 free(sc, M_DEVBUF);
875
876 return ENXIO;
877}
878
879static int
881{
882 int r;
883 struct sc_info *sc;
884
886 if (r)
887 return r;
888
889 sc = pcm_getdevinfo(dev);
890
891 /* power off */
892 cs4281_power(sc, 3);
893
894 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
895 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
896 bus_teardown_intr(dev, sc->irq, sc->ih);
897 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
898 bus_dma_tag_destroy(sc->parent_dmat);
899 free(sc, M_DEVBUF);
900
901 return 0;
902}
903
904static int
906{
907 struct sc_info *sc;
908
909 sc = pcm_getdevinfo(dev);
910
911 sc->rch.dma_active = adcdac_go(&sc->rch, 0);
912 sc->pch.dma_active = adcdac_go(&sc->pch, 0);
913
914 cs4281_power(sc, 3);
915
916 return 0;
917}
918
919static int
921{
922 struct sc_info *sc;
923
924 sc = pcm_getdevinfo(dev);
925
926 /* power up */
927 cs4281_power(sc, 0);
928
929 /* initialize chip */
930 if (cs4281_init(sc) == -1) {
931 device_printf(dev, "unable to reinitialize the card\n");
932 return ENXIO;
933 }
934
935 /* restore mixer state */
936 if (mixer_reinit(dev) == -1) {
937 device_printf(dev, "unable to reinitialize the mixer\n");
938 return ENXIO;
939 }
940
941 /* restore chip state */
942 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd);
943 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz);
944 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt);
945 adcdac_go(&sc->rch, sc->rch.dma_active);
946
947 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd);
948 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz);
949 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt);
950 adcdac_go(&sc->pch, sc->pch.dma_active);
951
952 return 0;
953}
954
955static device_method_t cs4281_methods[] = {
956 /* Device interface */
957 DEVMETHOD(device_probe, cs4281_pci_probe),
958 DEVMETHOD(device_attach, cs4281_pci_attach),
959 DEVMETHOD(device_detach, cs4281_pci_detach),
960 DEVMETHOD(device_suspend, cs4281_pci_suspend),
961 DEVMETHOD(device_resume, cs4281_pci_resume),
962 { 0, 0 }
963};
964
965static driver_t cs4281_driver = {
966 "pcm",
969};
970
971DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0);
973MODULE_VERSION(snd_cs4281, 1);
kobj_class_t ac97_getmixerclass(void)
Definition: ac97.c:1097
void ac97_destroy(struct ac97_info *codec)
Definition: ac97.c:860
#define AC97_CREATE(dev, devinfo, cls)
Definition: ac97.h:89
#define AC97_MIX_MASTER
Definition: ac97.h:43
#define AC97_MIX_AUXOUT
Definition: ac97.h:44
#define AC97_REG_POWER
Definition: ac97.h:60
u_int32_t data
Definition: ac97_if.m:60
int regno
Definition: ac97_if.m:53
void * devinfo
Definition: ac97_if.m:47
uint32_t format
Definition: audio_dai_if.m:39
uint32_t speed
Definition: audio_dai_if.m:86
uint32_t rate
Definition: audio_dai_if.m:58
int go
Definition: audio_dai_if.m:64
int sndbuf_alloc(struct snd_dbuf *b, bus_dma_tag_t dmatag, int dmaflags, unsigned int size)
Definition: buffer.c:93
bus_addr_t sndbuf_getbufaddr(struct snd_dbuf *buf)
Definition: buffer.c:66
unsigned int sndbuf_getsize(struct snd_dbuf *b)
Definition: buffer.c:435
int sndbuf_resize(struct snd_dbuf *b, unsigned int blkcnt, unsigned int blksz)
Definition: buffer.c:164
void chn_intr(struct pcm_channel *c)
Definition: channel.c:660
#define PCMDIR_PLAY
Definition: channel.h:339
#define PCMTRIG_START
Definition: channel.h:344
#define PCMTRIG_STOP
Definition: channel.h:347
#define PCMDIR_REC
Definition: channel.h:341
#define PCMTRIG_ABORT
Definition: channel.h:348
struct pcm_channel * c
Definition: channel_if.m:106
METHOD int free
Definition: channel_if.m:110
u_int32_t blocksize
Definition: channel_if.m:140
struct snd_dbuf * b
Definition: channel_if.m:105
#define CS4281_DMA_REC
Definition: cs4281.c:57
static int cs4281_pci_resume(device_t dev)
Definition: cs4281.c:920
static struct pcmchan_caps * cs4281chan_getcaps(kobj_t obj, void *data)
Definition: cs4281.c:452
static void cs4281_intr(void *)
Definition: cs4281.c:514
static struct pcmchan_caps cs4281_caps
Definition: cs4281.c:143
static u_int32_t cs4281_rates[]
Definition: cs4281.c:208
MODULE_DEPEND(snd_cs4281, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER)
static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go)
Definition: cs4281.c:476
static int cs4281_init(struct sc_info *)
Definition: cs4281.c:565
static driver_t cs4281_driver
Definition: cs4281.c:965
static int cs4281_pci_attach(device_t dev)
Definition: cs4281.c:761
#define CS4281_FIFO_SIZE
Definition: cs4281.c:53
static u_int32_t cs4281_format_to_bps(u_int32_t)
Definition: cs4281.c:247
#define CS4281_DMA_PLAY
Definition: cs4281.c:56
static void cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask)
Definition: cs4281.c:170
static int cs4281_pci_detach(device_t dev)
Definition: cs4281.c:880
static int cs4281_pci_suspend(device_t dev)
Definition: cs4281.c:905
static u_int32_t cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
Definition: cs4281.c:349
static u_int32_t cs4281_fmts[]
Definition: cs4281.c:127
SND_DECLARE_FILE("$FreeBSD$")
static device_method_t cs4281_methods[]
Definition: cs4281.c:955
static u_int32_t cs4281chan_getptr(kobj_t obj, void *data)
Definition: cs4281.c:414
static u_int32_t cs4281_format_to_dmr(u_int32_t)
Definition: cs4281.c:236
static int cs4281chan_trigger(kobj_t obj, void *data, int go)
Definition: cs4281.c:430
static void adcdac_prog(struct sc_chinfo *ch)
Definition: cs4281.c:494
static int cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries)
Definition: cs4281.c:192
static int cs4281_power(struct sc_info *, int)
Definition: cs4281.c:541
#define CS4281_NUM_RATES
Definition: cs4281.c:209
static u_int32_t cs4281_rv_to_rate(u_int8_t rv)
Definition: cs4281.c:226
#define CS4281_DEFAULT_BUFSZ
Definition: cs4281.c:50
static void * cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
Definition: cs4281.c:322
static int cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries)
Definition: cs4281.c:178
static void cs4281_wr(struct sc_info *, int, u_int32_t)
Definition: cs4281.c:155
static int cs4281_rdcd(kobj_t obj, void *devinfo, int regno)
Definition: cs4281.c:257
static kobj_method_t cs4281chan_methods[]
Definition: cs4281.c:457
static int cs4281_pci_probe(device_t dev)
Definition: cs4281.c:745
static u_int32_t cs4281_rd(struct sc_info *, int)
Definition: cs4281.c:149
DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0)
static int cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format)
Definition: cs4281.c:388
static int cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
Definition: cs4281.c:291
static u_int8_t cs4281_rate_to_rv(u_int32_t)
Definition: cs4281.c:212
CHANNEL_DECLARE(cs4281chan)
AC97_DECLARE(cs4281_ac97)
MODULE_VERSION(snd_cs4281, 1)
static u_int32_t cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
Definition: cs4281.c:371
static kobj_method_t cs4281_ac97_methods[]
Definition: cs4281.c:311
#define DEB(x)
Definition: cs4281.c:64
static void cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask)
Definition: cs4281.c:162
#define CS4281PCI_SRCSA_PRSS(x)
Definition: cs4281.h:191
#define CS4281PCI_SERMC
Definition: cs4281.h:146
#define CS4281PCI_DMR(x)
Definition: cs4281.h:67
#define CS4281PCI_PPLVC
Definition: cs4281.h:195
#define CS4281PCI_ACOSV
Definition: cs4281.h:166
#define CS4281PCI_DCR_TCIE
Definition: cs4281.h:89
#define CS4281PCI_DBA(x)
Definition: cs4281.h:64
#define CS4281PCI_HIMR_DMAI
Definition: cs4281.h:49
#define CS4281PCI_DMR_MONO
Definition: cs4281.h:76
#define CS4281PCI_FCR(x)
Definition: cs4281.h:92
#define CS4281PCI_LPCM_PLAY_SLOT
Definition: cs4281.h:199
#define CS4281PCI_SSPM_ACLEN
Definition: cs4281.h:182
#define CS4281PCI_HISR
Definition: cs4281.h:41
#define CS4281PCI_RPCM_REC_SLOT
Definition: cs4281.h:203
#define CS4281PCI_FCR_SZ(x)
Definition: cs4281.h:98
#define CS4281PCI_SSPM_MIXEN
Definition: cs4281.h:178
#define CS4281PCI_DCR(x)
Definition: cs4281.h:87
#define CS4281PCI_ACCTL_ESYN
Definition: cs4281.h:156
#define CS4281PCI_CLKCR1_SWCE
Definition: cs4281.h:137
#define CS4281PCI_FCR_OF(x)
Definition: cs4281.h:99
#define CS4281PCI_PPRVC
Definition: cs4281.h:196
#define CS4281PCI_FCR_LS(x)
Definition: cs4281.h:97
#define CS4281PCI_RPCM_PLAY_SLOT
Definition: cs4281.h:200
#define CS4281PCI_HISR_DMA(x)
Definition: cs4281.h:43
#define CS4281PCI_ACISV
Definition: cs4281.h:170
#define CS4281PCI_HICR
Definition: cs4281.h:45
#define CS4281PCI_DMR_USIGN
Definition: cs4281.h:74
#define CS4281PCI_EPPMC
Definition: cs4281.h:113
#define CS4281PCI_DACSR
Definition: cs4281.h:185
#define CS4281PCI_SSPM
Definition: cs4281.h:177
#define CS4281PCI_SRCSA_PLSS(x)
Definition: cs4281.h:190
#define CS4281PCI_ACOSV_SLV(x)
Definition: cs4281.h:167
#define CS4281PCI_ACSTS
Definition: cs4281.h:162
#define CS4281PCI_DMR_TR_REC
Definition: cs4281.h:85
#define CS4281PCI_SPMC_RSTN
Definition: cs4281.h:118
#define CS4281PCI_DMR_DMA
Definition: cs4281.h:68
#define CS4281PCI_DCA(x)
Definition: cs4281.h:62
#define CS4281PCI_DCR_HTCIE
Definition: cs4281.h:88
#define CS4281PCI_DMR_AUTO
Definition: cs4281.h:83
#define CS4281PCI_ACCDA
Definition: cs4281.h:169
#define CS4281PCI_SERMC_PTC_AC97
Definition: cs4281.h:147
#define CS4281PCI_ADCSR
Definition: cs4281.h:186
#define CS4281PCI_HIMR_DMA(x)
Definition: cs4281.h:50
#define CS4281PCI_FCR_PSH
Definition: cs4281.h:95
#define CS4281PCI_CLKCR1
Definition: cs4281.h:133
#define CS4281PCI_ACSTS_CRDY
Definition: cs4281.h:163
#define CS4281PCI_CLKCR1_DLLRDY
Definition: cs4281.h:140
#define CS4281PCI_FCR_RS(x)
Definition: cs4281.h:96
#define CS4281PCI_DMR_TR_PLAY
Definition: cs4281.h:84
#define CS4281PCI_CWPR_MAGIC
Definition: cs4281.h:111
#define CS4281PCI_FCR_FEN
Definition: cs4281.h:93
#define CS4281PCI_ACCTL_DCV
Definition: cs4281.h:158
#define CS4281PCI_ACCAD
Definition: cs4281.h:168
#define CS4281PCI_HICR_EOI
Definition: cs4281.h:46
#define CS4281PCI_DBC(x)
Definition: cs4281.h:65
#define CS4281PCI_CWPR
Definition: cs4281.h:110
#define CS4281PCI_SRCSA
Definition: cs4281.h:189
#define CS4281PCI_HDSR(x)
Definition: cs4281.h:54
#define CS4281PCI_ACSTS_VSTS
Definition: cs4281.h:164
#define CS4281PCI_ACSDA
Definition: cs4281.h:173
#define CS4281PCI_ACISV_ISV(x)
Definition: cs4281.h:171
#define CS4281PCI_DMR_BEND
Definition: cs4281.h:75
#define CS4281PCI_CLKCR1_DLLP
Definition: cs4281.h:136
#define CS4281PCI_HIMR
Definition: cs4281.h:48
#define CS4281PCI_DMR_SIZE8
Definition: cs4281.h:77
#define CS4281PCI_SRCSA_CLSS(x)
Definition: cs4281.h:192
#define CS4281PCI_SSPM_CSRCEN
Definition: cs4281.h:179
#define CS4281PCI_SSPM_PSRCEN
Definition: cs4281.h:180
#define CS4281PCI_LPCM_REC_SLOT
Definition: cs4281.h:202
#define CS4281_PCI_ID
Definition: cs4281.h:34
#define CS4281PCI_ACCTL
Definition: cs4281.h:155
#define CS4281PCI_DCR_MSK
Definition: cs4281.h:90
#define CS4281PCI_SPMC
Definition: cs4281.h:117
#define CS4281PCI_ACCTL_CRW
Definition: cs4281.h:159
#define CS4281PCI_SRCSA_CRSS(x)
Definition: cs4281.h:193
#define CS4281PCI_ACCTL_VFRM
Definition: cs4281.h:157
#define CS4281PCI_EPPMC_FPDN
Definition: cs4281.h:114
uint8_t mask
Definition: hdac.c:212
int dir
Definition: hdac_if.m:45
uint8_t r
#define KOBJMETHOD_END
Definition: midi.c:76
int mixer_init(device_t dev, kobj_class_t cls, void *devinfo)
Definition: mixer.c:725
int mixer_reinit(device_t dev)
Definition: mixer.c:860
unsigned dev
Definition: mixer_if.m:59
bool * status
int state
#define PCIR_BAR(x)
void * pcm_getdevinfo(device_t dev)
Definition: sound.c:832
int pcm_setstatus(device_t dev, char *str)
Definition: sound.c:766
devclass_t pcm_devclass
Definition: sound.c:49
int pcm_addchan(device_t dev, int dir, kobj_class_t cls, void *devinfo)
Definition: sound.c:692
int pcm_unregister(device_t dev)
Definition: sound.c:1170
int pcm_register(device_t dev, void *devinfo, int numplay, int numrec)
Definition: sound.c:1080
int snd_setup_intr(device_t dev, struct resource *res, int flags, driver_intr_t hand, void *param, void **cookiep)
Definition: sound.c:117
unsigned int pcm_getbuffersize(device_t dev, unsigned int minbufsz, unsigned int deflt, unsigned int maxbufsz)
Definition: sound.c:840
#define PCM_KLDSTRING(a)
Definition: sound.h:619
#define SND_FORMAT(f, c, e)
Definition: sound.h:238
#define SOUND_PREFVER
Definition: sound.h:103
#define SOUND_MAXVER
Definition: sound.h:104
#define DSP_DEFAULT_SPEED
Definition: sound.h:295
#define AFMT_BIGENDIAN
Definition: sound.h:196
#define AFMT_CHANNEL(v)
Definition: sound.h:227
#define AFMT_8BIT
Definition: sound.h:193
#define SOUND_MINVER
Definition: sound.h:102
#define PCM_SOFTC_SIZE
Definition: sound.h:96
#define AFMT_SIGNED
Definition: sound.h:194
#define SND_STATUSLEN
Definition: sound.h:98
Definition: ac97.c:59
u_int32_t fmt
Definition: cmi.c:107
u_int32_t spd
Definition: cmi.c:107
struct pcm_channel * channel
Definition: als4000.c:68
int dma_setup
Definition: cs4281.c:81
u_int32_t bps
Definition: als4000.c:70
struct sc_info * parent
Definition: als4000.c:67
int dma_active
Definition: cs4281.c:81
struct snd_dbuf * buffer
Definition: als4000.c:69
int dma_chan
Definition: cs4281.c:81
u_int32_t blksz
Definition: cs4281.c:79
u_int32_t type
Definition: cs4281.c:87
bus_space_tag_t st
Definition: als4000.c:78
unsigned int bufsz
Definition: als4000.c:86
int memid
Definition: cs4281.c:94
struct resource * irq
Definition: als4000.c:81
device_t dev
Definition: als4000.c:77
struct resource * mem
Definition: cs4281.c:93
unsigned long bufsz
Definition: cs4281.c:98
int irqid
Definition: als4000.c:82
struct resource * reg
Definition: als4000.c:81
struct sc_chinfo pch rch
Definition: als4000.c:87
void * ih
Definition: als4000.c:83
int regid
Definition: als4000.c:82
bus_dma_tag_t parent_dmat
Definition: als4000.c:80
struct sc_chinfo pch
Definition: cs4281.c:99
int regtype
Definition: cs4281.c:94
struct sc_chinfo ch[3]
Definition: ich.c:192
int power
Definition: cs4281.c:97
bus_space_handle_t sh
Definition: als4000.c:79