\doxysection{Data Structures}
Here are the data structures with brief descriptions\+:\begin{DoxyCompactList}
\item\contentsline{section}{\mbox{\hyperlink{struct__pcsid}{\+\_\+pcsid}} }{\pageref{struct__pcsid}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct__SCIC__SDS__REMOTE__NODE__CONTEXT__HANDLERS}{\+\_\+\+SCIC\+\_\+\+SDS\+\_\+\+REMOTE\+\_\+\+NODE\+\_\+\+CONTEXT\+\_\+\+HANDLERS}} }{\pageref{struct__SCIC__SDS__REMOTE__NODE__CONTEXT__HANDLERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct__SMP__REQUEST}{\+\_\+\+SMP\+\_\+\+REQUEST}} }{\pageref{struct__SMP__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct__SMP__RESPONSE}{\+\_\+\+SMP\+\_\+\+RESPONSE}} }{\pageref{struct__SMP__RESPONSE}}{}
\item\contentsline{section}{\mbox{\hyperlink{struct__TRIM__PAIR}{\+\_\+\+TRIM\+\_\+\+PAIR}} }{\pageref{struct__TRIM__PAIR}}{}
\item\contentsline{section}{\mbox{\hyperlink{unionATA__DESCRIPTOR__ENTRY}{ATA\+\_\+\+DESCRIPTOR\+\_\+\+ENTRY}} }{\pageref{unionATA__DESCRIPTOR__ENTRY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structATA__EXTENDED__SMART__SELF__TEST__LOG}{ATA\+\_\+\+EXTENDED\+\_\+\+SMART\+\_\+\+SELF\+\_\+\+TEST\+\_\+\+LOG}} \\*The following structure depicts the ATA-\/8 version of the Extended SMART self test log page descriptor entry }{\pageref{structATA__EXTENDED__SMART__SELF__TEST__LOG}}{}
\item\contentsline{section}{\mbox{\hyperlink{structATA__IDENTIFY__DEVICE}{ATA\+\_\+\+IDENTIFY\+\_\+\+DEVICE}} \\*This structure depicts the ATA IDENTIFY DEVICE data format }{\pageref{structATA__IDENTIFY__DEVICE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structATA__IDENTIFY__DEVICE__DATA}{ATA\+\_\+\+IDENTIFY\+\_\+\+DEVICE\+\_\+\+DATA}} }{\pageref{structATA__IDENTIFY__DEVICE__DATA}}{}
\item\contentsline{section}{\mbox{\hyperlink{structATA__NCQ__COMMAND__ERROR__LOG}{ATA\+\_\+\+NCQ\+\_\+\+COMMAND\+\_\+\+ERROR\+\_\+\+LOG}} \\*The following structure depicts the ATA-\/8 version of the NCQ command error log page }{\pageref{structATA__NCQ__COMMAND__ERROR__LOG}}{}
\item\contentsline{section}{\mbox{\hyperlink{unionATA__SMART__DESCRIPTOR__ENTRY}{ATA\+\_\+\+SMART\+\_\+\+DESCRIPTOR\+\_\+\+ENTRY}} }{\pageref{unionATA__SMART__DESCRIPTOR__ENTRY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structATA__SMART__SELF__TEST__LOG}{ATA\+\_\+\+SMART\+\_\+\+SELF\+\_\+\+TEST\+\_\+\+LOG}} }{\pageref{structATA__SMART__SELF__TEST__LOG}}{}
\item\contentsline{section}{\mbox{\hyperlink{structATAPI__IDENTIFY__PACKET__DATA}{ATAPI\+\_\+\+IDENTIFY\+\_\+\+PACKET\+\_\+\+DATA}} \\*The following structure depicts the ATA-\/\+ATAPI 7 version of the IDENTIFY PACKET DEVICE data structure }{\pageref{structATAPI__IDENTIFY__PACKET__DATA}}{}
\item\contentsline{section}{\mbox{\hyperlink{structATAPI__IDENTIFY__PACKET__DEVICE}{ATAPI\+\_\+\+IDENTIFY\+\_\+\+PACKET\+\_\+\+DEVICE}} }{\pageref{structATAPI__IDENTIFY__PACKET__DEVICE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structATA__DESCRIPTOR__ENTRY_1_1DESCRIPTOR__ENTRY}{ATA\+\_\+\+DESCRIPTOR\+\_\+\+ENTRY\+::\+DESCRIPTOR\+\_\+\+ENTRY}} }{\pageref{structATA__DESCRIPTOR__ENTRY_1_1DESCRIPTOR__ENTRY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structISCI__CONTROLLER}{ISCI\+\_\+\+CONTROLLER}} }{\pageref{structISCI__CONTROLLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structISCI__DOMAIN}{ISCI\+\_\+\+DOMAIN}} }{\pageref{structISCI__DOMAIN}}{}
\item\contentsline{section}{\mbox{\hyperlink{structISCI__INTERRUPT__INFO}{ISCI\+\_\+\+INTERRUPT\+\_\+\+INFO}} }{\pageref{structISCI__INTERRUPT__INFO}}{}
\item\contentsline{section}{\mbox{\hyperlink{structISCI__IO__REQUEST}{ISCI\+\_\+\+IO\+\_\+\+REQUEST}} }{\pageref{structISCI__IO__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structISCI__MEMORY}{ISCI\+\_\+\+MEMORY}} }{\pageref{structISCI__MEMORY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structISCI__PCI__BAR}{ISCI\+\_\+\+PCI\+\_\+\+BAR}} }{\pageref{structISCI__PCI__BAR}}{}
\item\contentsline{section}{\mbox{\hyperlink{structISCI__PHY}{ISCI\+\_\+\+PHY}} }{\pageref{structISCI__PHY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structISCI__REMOTE__DEVICE}{ISCI\+\_\+\+REMOTE\+\_\+\+DEVICE}} }{\pageref{structISCI__REMOTE__DEVICE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structISCI__REQUEST}{ISCI\+\_\+\+REQUEST}} }{\pageref{structISCI__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structisci__softc}{isci\+\_\+softc}} }{\pageref{structisci__softc}}{}
\item\contentsline{section}{\mbox{\hyperlink{structISCI__TASK__REQUEST}{ISCI\+\_\+\+TASK\+\_\+\+REQUEST}} }{\pageref{structISCI__TASK__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structISCI__TIMER}{ISCI\+\_\+\+TIMER}} }{\pageref{structISCI__TIMER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structMODE__PARAMETER__BLOCK__DESCRIPTOR}{MODE\+\_\+\+PARAMETER\+\_\+\+BLOCK\+\_\+\+DESCRIPTOR}} \\*This structure contains mode parameter block descriptor fields }{\pageref{structMODE__PARAMETER__BLOCK__DESCRIPTOR}}{}
\item\contentsline{section}{\mbox{\hyperlink{structMODE__PARAMETER__HEADER__10}{MODE\+\_\+\+PARAMETER\+\_\+\+HEADER\+\_\+10}} \\*This structure contains mode parameter header fields for 10 byte mode select command }{\pageref{structMODE__PARAMETER__HEADER__10}}{}
\item\contentsline{section}{\mbox{\hyperlink{structNOA__HOST__INTERFACE__PARTITION}{NOA\+\_\+\+HOST\+\_\+\+INTERFACE\+\_\+\+PARTITION}} \\*Placeholder since I am not yet sure what these registers are here for }{\pageref{structNOA__HOST__INTERFACE__PARTITION}}{}
\item\contentsline{section}{\mbox{\hyperlink{structNOA__HUB__PARTITION}{NOA\+\_\+\+HUB\+\_\+\+PARTITION}} \\*Placeholder since I am not yet sure what these registers are here for }{\pageref{structNOA__HUB__PARTITION}}{}
\item\contentsline{section}{\mbox{\hyperlink{structNOA__PROTOCOL__ENGINE__PARTITION}{NOA\+\_\+\+PROTOCOL\+\_\+\+ENGINE\+\_\+\+PARTITION}} \\*Placeholder since I am not yet sure what these registers are here for }{\pageref{structNOA__PROTOCOL__ENGINE__PARTITION}}{}
\item\contentsline{section}{\mbox{\hyperlink{structoem__parameters__table}{oem\+\_\+parameters\+\_\+table}} }{\pageref{structoem__parameters__table}}{}
\item\contentsline{section}{\mbox{\hyperlink{unionOEM__SSC__DATA}{OEM\+\_\+\+SSC\+\_\+\+DATA}} \\*This typedef provides a means to convert from the original 1.\+0 version of the OEM PARAMETER do\+\_\+enable\+\_\+ssc to the more comprehensive 1.\+1 version of enabling SSC parameters. For the definition of the field members see \mbox{\hyperlink{scu__bios__definitions_8h}{scu\+\_\+bios\+\_\+definitions.\+h}} header file or refer to the SCU BIOS Writers Guide }{\pageref{unionOEM__SSC__DATA}}{}
\item\contentsline{section}{\mbox{\hyperlink{unionOEM__SSC__PARAMETERS}{OEM\+\_\+\+SSC\+\_\+\+PARAMETERS}} }{\pageref{unionOEM__SSC__PARAMETERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structpcir__header}{pcir\+\_\+header}} }{\pageref{structpcir__header}}{}
\item\contentsline{section}{\mbox{\hyperlink{structPRIMITIVE__TASK__CONTEXT}{PRIMITIVE\+\_\+\+TASK\+\_\+\+CONTEXT}} \\*This is the SCU hardware definition used when the driver wants to send a primitive on the link }{\pageref{structPRIMITIVE__TASK__CONTEXT}}{}
\item\contentsline{section}{\mbox{\hyperlink{unionPROTOCOL__CONTEXT}{PROTOCOL\+\_\+\+CONTEXT}} \\*The union of the protocols that can be selected in the SCU task context field }{\pageref{unionPROTOCOL__CONTEXT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structoem__parameters__table_1_1revision}{oem\+\_\+parameters\+\_\+table\+::revision}} }{\pageref{structoem__parameters__table_1_1revision}}{}
\item\contentsline{section}{\mbox{\hyperlink{structrom__header}{rom\+\_\+header}} }{\pageref{structrom__header}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSAS__CAPABILITIES}{SAS\+\_\+\+CAPABILITIES}} \\*This structure depicts the various SAS capabilities supported by the directly attached target device. For specific information on each of these individual fields please reference the SAS specification Phy layer section on speed negotiation windows }{\pageref{structSAS__CAPABILITIES}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATA__FIS__BIST__ACTIVATE}{SATA\+\_\+\+FIS\+\_\+\+BIST\+\_\+\+ACTIVATE}} \\*SATA BIST Activate FIS }{\pageref{structSATA__FIS__BIST__ACTIVATE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATA__FIS__DATA}{SATA\+\_\+\+FIS\+\_\+\+DATA}} \\*SATA Data FIS }{\pageref{structSATA__FIS__DATA}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATA__FIS__DMA__ACTIVATE}{SATA\+\_\+\+FIS\+\_\+\+DMA\+\_\+\+ACTIVATE}} \\*SATA DMA Activate FIS }{\pageref{structSATA__FIS__DMA__ACTIVATE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATA__FIS__DMA__SETUP}{SATA\+\_\+\+FIS\+\_\+\+DMA\+\_\+\+SETUP}} \\*SATA DMA Setup FIS }{\pageref{structSATA__FIS__DMA__SETUP}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATA__FIS__HEADER}{SATA\+\_\+\+FIS\+\_\+\+HEADER}} \\*This is the common definition for a SATA FIS Header word. A different header word is defined for any FIS type that does not use the standard header }{\pageref{structSATA__FIS__HEADER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATA__FIS__PIO__SETUP}{SATA\+\_\+\+FIS\+\_\+\+PIO\+\_\+\+SETUP}} }{\pageref{structSATA__FIS__PIO__SETUP}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATA__FIS__REG__D2H}{SATA\+\_\+\+FIS\+\_\+\+REG\+\_\+\+D2H}} \\*SATA Device To Host FIS }{\pageref{structSATA__FIS__REG__D2H}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATA__FIS__REG__H2D}{SATA\+\_\+\+FIS\+\_\+\+REG\+\_\+\+H2D}} \\*This is the definition for a SATA Host to Device Register FIS }{\pageref{structSATA__FIS__REG__H2D}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATA__FIS__SET__DEV__BITS}{SATA\+\_\+\+FIS\+\_\+\+SET\+\_\+\+DEV\+\_\+\+BITS}} \\*SATA Set Device Bits FIS }{\pageref{structSATA__FIS__SET__DEV__BITS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATI__ATAPI__DATA}{SATI\+\_\+\+ATAPI\+\_\+\+DATA}} \\*The \mbox{\hyperlink{structSATI__ATAPI__DATA}{SATI\+\_\+\+ATAPI\+\_\+\+DATA}} structure is for sati atapi IO specific data }{\pageref{structSATI__ATAPI__DATA}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATI__DEVICE}{SATI\+\_\+\+DEVICE}} \\*The \mbox{\hyperlink{structSATI__DEVICE}{SATI\+\_\+\+DEVICE}} structure define the state of the remote device with respect to translation }{\pageref{structSATI__DEVICE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATI__MODE__SELECT__PROCESSING__STATE}{SATI\+\_\+\+MODE\+\_\+\+SELECT\+\_\+\+PROCESSING\+\_\+\+STATE}} \\*This structure contains all of the current processing states for processing mode select 6 and 10 commands\textquotesingle{} parameter fields }{\pageref{structSATI__MODE__SELECT__PROCESSING__STATE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATI__REASSIGN__BLOCKS__PROCESSING__STATE}{SATI\+\_\+\+REASSIGN\+\_\+\+BLOCKS\+\_\+\+PROCESSING\+\_\+\+STATE}} \\*This structure contains all of the current processing states for processing reassign block command\textquotesingle{}s parameter fields }{\pageref{structSATI__REASSIGN__BLOCKS__PROCESSING__STATE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATI__TRANSLATOR__SEQUENCE}{SATI\+\_\+\+TRANSLATOR\+\_\+\+SEQUENCE}} \\*This structure contains all of the translation information associated with a particular request }{\pageref{structSATI__TRANSLATOR__SEQUENCE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSATI__UNMAP__PROCESSING__STATE}{SATI\+\_\+\+UNMAP\+\_\+\+PROCESSING\+\_\+\+STATE}} \\*This structure contains all of the current processing states for processing unmap command data translation }{\pageref{structSATI__UNMAP__PROCESSING__STATE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__ABSTRACT__ELEMENT}{SCI\+\_\+\+ABSTRACT\+\_\+\+ELEMENT}} \\*This object represents an element of a abstract list. NOTE\+: This structure does not evenly align on a cache line boundary. If SSP specific code ends up using this list, then it may be a good idea to force the alignment. Now it is more important to save the space }{\pageref{structSCI__ABSTRACT__ELEMENT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__ABSTRACT__ELEMENT__LIST}{SCI\+\_\+\+ABSTRACT\+\_\+\+ELEMENT\+\_\+\+LIST}} \\*This object represents an element list object. It can have elements added and removed from it }{\pageref{structSCI__ABSTRACT__ELEMENT__LIST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__ABSTRACT__ELEMENT__POOL}{SCI\+\_\+\+ABSTRACT\+\_\+\+ELEMENT\+\_\+\+POOL}} \\*This structure provides the pool of free abstract elements to be utilized by an \mbox{\hyperlink{structSCI__ABSTRACT__LIST}{SCI\+\_\+\+ABSTRACT\+\_\+\+LIST}} }{\pageref{structSCI__ABSTRACT__ELEMENT__POOL}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__ABSTRACT__LIST}{SCI\+\_\+\+ABSTRACT\+\_\+\+LIST}} \\*This object provides the ability to queue any type of object or even the same object multiple times. The object must be provided an element pool from which to draw free elements }{\pageref{structSCI__ABSTRACT__LIST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__CONTROLLER}{SCI\+\_\+\+BASE\+\_\+\+CONTROLLER}} \\*The base controller object abstracts the fields common to all SCI controller objects }{\pageref{structSCI__BASE__CONTROLLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__CONTROLLER__STATE__HANDLER}{SCI\+\_\+\+BASE\+\_\+\+CONTROLLER\+\_\+\+STATE\+\_\+\+HANDLER}} \\*This structure contains all of the state handler methods common to base controller state machines. Handler methods provide the ability to change the behavior for user requests or transitions depending on the state the machine is in }{\pageref{structSCI__BASE__CONTROLLER__STATE__HANDLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__DOMAIN}{SCI\+\_\+\+BASE\+\_\+\+DOMAIN}} \\*This structure defines all of the fields common to DOMAIN objects }{\pageref{structSCI__BASE__DOMAIN}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__DOMAIN__STATE__HANDLER}{SCI\+\_\+\+BASE\+\_\+\+DOMAIN\+\_\+\+STATE\+\_\+\+HANDLER}} \\*This structure contains all of the state handler methods common to base domain state machines. Handler methods provide the ability to change the behavior for user requests or transitions depending on the state the machine is in }{\pageref{structSCI__BASE__DOMAIN__STATE__HANDLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__ITERATOR}{SCI\+\_\+\+BASE\+\_\+\+ITERATOR}} \\*This object represents an iterator of an abstract list }{\pageref{structSCI__BASE__ITERATOR}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__LIBRARY}{SCI\+\_\+\+BASE\+\_\+\+LIBRARY}} \\*This structure contains all of the objects common to all library sub-\/objects }{\pageref{structSCI__BASE__LIBRARY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__LOGGER}{SCI\+\_\+\+BASE\+\_\+\+LOGGER}} \\*This structure contains the set of log objects and verbosities that are enabled for logging. It\textquotesingle{}s parent is the SCI\+\_\+\+BASE\+\_\+\+OBJECT\+\_\+T }{\pageref{structSCI__BASE__LOGGER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__MEMORY__DESCRIPTOR__LIST}{SCI\+\_\+\+BASE\+\_\+\+MEMORY\+\_\+\+DESCRIPTOR\+\_\+\+LIST}} \\*This structure contains all of the fields necessary to implement a simple stack for managing the list of available controller indices }{\pageref{structSCI__BASE__MEMORY__DESCRIPTOR__LIST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__OBJECT}{SCI\+\_\+\+BASE\+\_\+\+OBJECT}} \\*The \mbox{\hyperlink{structSCI__BASE__OBJECT}{SCI\+\_\+\+BASE\+\_\+\+OBJECT}} object represents the data and functionality that is common to all SCI objects. It is the base class }{\pageref{structSCI__BASE__OBJECT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__PHY}{SCI\+\_\+\+BASE\+\_\+\+PHY}} \\*This structure defines all of the fields common to PHY objects }{\pageref{structSCI__BASE__PHY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__PHY__STATE__HANDLER}{SCI\+\_\+\+BASE\+\_\+\+PHY\+\_\+\+STATE\+\_\+\+HANDLER}} \\*This structure contains all of the state handler methods common to base phy state machines. Handler methods provide the ability to change the behavior for user requests or transitions depending on the state the machine is in }{\pageref{structSCI__BASE__PHY__STATE__HANDLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__PORT}{SCI\+\_\+\+BASE\+\_\+\+PORT}} \\*The base port object abstracts the fields common to all SCI port objects }{\pageref{structSCI__BASE__PORT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__PORT__STATE__HANDLER}{SCI\+\_\+\+BASE\+\_\+\+PORT\+\_\+\+STATE\+\_\+\+HANDLER}} \\*This structure contains all of the state handler methods common to base port state machines. Handler methods provide the ability to change the behavior for user requests or transitions depending on the state the machine is in }{\pageref{structSCI__BASE__PORT__STATE__HANDLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__REMOTE__DEVICE}{SCI\+\_\+\+BASE\+\_\+\+REMOTE\+\_\+\+DEVICE}} \\*The base remote device object abstracts the fields common to all SCI remote device objects }{\pageref{structSCI__BASE__REMOTE__DEVICE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__REMOTE__DEVICE__STATE__HANDLER}{SCI\+\_\+\+BASE\+\_\+\+REMOTE\+\_\+\+DEVICE\+\_\+\+STATE\+\_\+\+HANDLER}} }{\pageref{structSCI__BASE__REMOTE__DEVICE__STATE__HANDLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__REQUEST}{SCI\+\_\+\+BASE\+\_\+\+REQUEST}} \\*The base request object abstracts the fields common to all SCI IO and task request objects }{\pageref{structSCI__BASE__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__REQUEST__STATE__HANDLER}{SCI\+\_\+\+BASE\+\_\+\+REQUEST\+\_\+\+STATE\+\_\+\+HANDLER}} \\*This structure contains all of the state handler methods common to base IO and task request state machines. Handler methods provide the ability to change the behavior for user requests or transitions depending on the state the machine is in }{\pageref{structSCI__BASE__REQUEST__STATE__HANDLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__STATE}{SCI\+\_\+\+BASE\+\_\+\+STATE}} \\*The base state object abstracts the fields common to all state objects defined in SCI }{\pageref{structSCI__BASE__STATE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BASE__STATE__MACHINE}{SCI\+\_\+\+BASE\+\_\+\+STATE\+\_\+\+MACHINE}} \\*This structure defines the fields common to all state machines }{\pageref{structSCI__BASE__STATE__MACHINE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BIOS__OEM__PARAM__BLOCK}{SCI\+\_\+\+BIOS\+\_\+\+OEM\+\_\+\+PARAM\+\_\+\+BLOCK}} \\*This structure defines the OEM Parameter block as it will be stored in the last 512 bytes of the PDR region in the SPI flash. It must be unpacked or pack(1) }{\pageref{structSCI__BIOS__OEM__PARAM__BLOCK}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BIOS__OEM__PARAM__BLOCK__HDR}{SCI\+\_\+\+BIOS\+\_\+\+OEM\+\_\+\+PARAM\+\_\+\+BLOCK\+\_\+\+HDR}} \\*This structure defines the OEM Parameter block header }{\pageref{structSCI__BIOS__OEM__PARAM__BLOCK__HDR}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BIOS__OEM__PARAM__ELEMENT}{SCI\+\_\+\+BIOS\+\_\+\+OEM\+\_\+\+PARAM\+\_\+\+ELEMENT}} }{\pageref{structSCI__BIOS__OEM__PARAM__ELEMENT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BIOS__OEM__PARAM__ELEMENT__v__1__1}{SCI\+\_\+\+BIOS\+\_\+\+OEM\+\_\+\+PARAM\+\_\+\+ELEMENT\+\_\+v\+\_\+1\+\_\+1}} }{\pageref{structSCI__BIOS__OEM__PARAM__ELEMENT__v__1__1}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BIOS__OEM__PARAM__ELEMENT__v__1__2}{SCI\+\_\+\+BIOS\+\_\+\+OEM\+\_\+\+PARAM\+\_\+\+ELEMENT\+\_\+v\+\_\+1\+\_\+2}} }{\pageref{structSCI__BIOS__OEM__PARAM__ELEMENT__v__1__2}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__BIOS__OEM__PARAM__ELEMENT__v__1__3}{SCI\+\_\+\+BIOS\+\_\+\+OEM\+\_\+\+PARAM\+\_\+\+ELEMENT\+\_\+v\+\_\+1\+\_\+3}} }{\pageref{structSCI__BIOS__OEM__PARAM__ELEMENT__v__1__3}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__FAST__LIST}{SCI\+\_\+\+FAST\+\_\+\+LIST}} \\*List owner or list anchor for a set of \mbox{\hyperlink{structSCI__FAST__LIST}{SCI\+\_\+\+FAST\+\_\+\+LIST}} elements }{\pageref{structSCI__FAST__LIST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__FAST__LIST__ELEMENT}{SCI\+\_\+\+FAST\+\_\+\+LIST\+\_\+\+ELEMENT}} \\*This structure defines what a doubly linked list element contains }{\pageref{structSCI__FAST__LIST__ELEMENT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structsci__pci__common__header}{sci\+\_\+pci\+\_\+common\+\_\+header}} }{\pageref{structsci__pci__common__header}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__PHYSICAL__MEMORY__DESCRIPTOR}{SCI\+\_\+\+PHYSICAL\+\_\+\+MEMORY\+\_\+\+DESCRIPTOR}} \\*This structure defines a description of a memory location for the SCI implementation }{\pageref{structSCI__PHYSICAL__MEMORY__DESCRIPTOR}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__SAS__ADDRESS}{SCI\+\_\+\+SAS\+\_\+\+ADDRESS}} \\*This structure depicts how a SAS address is represented by SCI }{\pageref{structSCI__SAS__ADDRESS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__SAS__IDENTIFY__ADDRESS__FRAME}{SCI\+\_\+\+SAS\+\_\+\+IDENTIFY\+\_\+\+ADDRESS\+\_\+\+FRAME}} \\*This structure depicts the contents of the SAS IDENTIFY ADDRESS FRAME (IAF) }{\pageref{structSCI__SAS__IDENTIFY__ADDRESS__FRAME}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__SAS__IDENTIFY__ADDRESS__FRAME__PROTOCOLS}{SCI\+\_\+\+SAS\+\_\+\+IDENTIFY\+\_\+\+ADDRESS\+\_\+\+FRAME\+\_\+\+PROTOCOLS}} \\*This structure depicts the contents of bytes 2 and 3 in the SAS IDENTIFY ADDRESS FRAME (IAF) }{\pageref{structSCI__SAS__IDENTIFY__ADDRESS__FRAME__PROTOCOLS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__SIMPLE__LIST}{SCI\+\_\+\+SIMPLE\+\_\+\+LIST}} }{\pageref{structSCI__SIMPLE__LIST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__SIMPLE__LIST__ELEMENT}{SCI\+\_\+\+SIMPLE\+\_\+\+LIST\+\_\+\+ELEMENT}} \\*This structure defines what a singely linked list element contains }{\pageref{structSCI__SIMPLE__LIST__ELEMENT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__SINGLE__LEVEL__LUN}{SCI\+\_\+\+SINGLE\+\_\+\+LEVEL\+\_\+\+LUN}} \\*This struct describes the single level LUN structure as per the SAM 4 }{\pageref{structSCI__SINGLE__LEVEL__LUN}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__SSP__COMMAND__IU}{SCI\+\_\+\+SSP\+\_\+\+COMMAND\+\_\+\+IU}} \\*This structure depicts the contents of the SSP COMMAND INFORMATION UNIT. For specific information on each of these individual fields please reference the SAS specification SSP transport layer section }{\pageref{structSCI__SSP__COMMAND__IU}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__SSP__FRAME__HEADER}{SCI\+\_\+\+SSP\+\_\+\+FRAME\+\_\+\+HEADER}} \\*This structure depicts the contents of an SSP frame header. For specific information on the individual fields please reference the SAS specification transport layer SSP frame format }{\pageref{structSCI__SSP__FRAME__HEADER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__SSP__RESPONSE__IU}{SCI\+\_\+\+SSP\+\_\+\+RESPONSE\+\_\+\+IU}} \\*This structure depicts the contents of the SSP RESPONSE INFORMATION UNIT. For specific information on each of these individual fields please reference the SAS specification SSP transport layer section }{\pageref{structSCI__SSP__RESPONSE__IU}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCI__SSP__TASK__IU}{SCI\+\_\+\+SSP\+\_\+\+TASK\+\_\+\+IU}} \\*This structure depicts the contents of the SSP TASK INFORMATION UNIT. For specific information on each of these individual fields please reference the SAS specification SSP transport layer section }{\pageref{structSCI__SSP__TASK__IU}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__CONTROLLER__HANDLER__METHODS}{SCIC\+\_\+\+CONTROLLER\+\_\+\+HANDLER\+\_\+\+METHODS}} \\*This structure contains an interrupt handler and completion handler function pointers }{\pageref{structSCIC__CONTROLLER__HANDLER__METHODS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__IO__PARAMETERS}{SCIC\+\_\+\+IO\+\_\+\+PARAMETERS}} \\*This structure contains additional optional parameters for STP/\+SATA IO requests. These parameters are utilized with the \mbox{\hyperlink{scic__io__request_8h_ae8b76696fdc6314143e710bdfb542fb8}{scic\+\_\+io\+\_\+request\+\_\+construct\+\_\+advanced\+\_\+sata()}} method }{\pageref{structSCIC__IO__PARAMETERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__IO__SATA__PARAMETERS}{SCIC\+\_\+\+IO\+\_\+\+SATA\+\_\+\+PARAMETERS}} }{\pageref{structSCIC__IO__SATA__PARAMETERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__IO__SSP__PARAMETERS}{SCIC\+\_\+\+IO\+\_\+\+SSP\+\_\+\+PARAMETERS}} \\*This structure contains additional optional parameters for SSP IO requests. These parameters are utilized with the \mbox{\hyperlink{scic__io__request_8h_a2b95315f92906d0bad6e9dc5bb761fc5}{scic\+\_\+io\+\_\+request\+\_\+construct\+\_\+advanced\+\_\+ssp()}} method }{\pageref{structSCIC__IO__SSP__PARAMETERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{unionSCIC__OEM__PARAMETERS}{SCIC\+\_\+\+OEM\+\_\+\+PARAMETERS}} \\*This structure/union specifies the various different OEM parameter sets available. Each type is specific to a hardware controller version }{\pageref{unionSCIC__OEM__PARAMETERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__PASSTHRU__REQUEST__CALLBACKS}{SCIC\+\_\+\+PASSTHRU\+\_\+\+REQUEST\+\_\+\+CALLBACKS}} \\*This structure contains the pointer to the callback functions for constructing the passthrough request common to SSP, SMP and STP. This structure must be set by the win sci layer before the passthrough build is called }{\pageref{structSCIC__PASSTHRU__REQUEST__CALLBACKS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__PHY__PROPERTIES}{SCIC\+\_\+\+PHY\+\_\+\+PROPERTIES}} \\*This structure defines the properties common to all phys that can be retrieved }{\pageref{structSCIC__PHY__PROPERTIES}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__PORT__END__POINT__PROPERTIES}{SCIC\+\_\+\+PORT\+\_\+\+END\+\_\+\+POINT\+\_\+\+PROPERTIES}} \\*This structure defines the properties that can be retrieved for each end-\/point local or remote (attached) port in the controller }{\pageref{structSCIC__PORT__END__POINT__PROPERTIES}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__PORT__PROPERTIES}{SCIC\+\_\+\+PORT\+\_\+\+PROPERTIES}} \\*This structure defines the properties that can be retrieved for each port in the controller }{\pageref{structSCIC__PORT__PROPERTIES}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__POWER__CONTROL}{SCIC\+\_\+\+POWER\+\_\+\+CONTROL}} }{\pageref{structSCIC__POWER__CONTROL}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__REMOTE__NODE__TABLE}{SCIC\+\_\+\+REMOTE\+\_\+\+NODE\+\_\+\+TABLE}} }{\pageref{structSCIC__REMOTE__NODE__TABLE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SAS__PHY__PROPERTIES}{SCIC\+\_\+\+SAS\+\_\+\+PHY\+\_\+\+PROPERTIES}} \\*This structure defines the properties, specific to a SAS phy, that can be retrieved }{\pageref{structSCIC__SAS__PHY__PROPERTIES}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SATA__PHY__PROPERTIES}{SCIC\+\_\+\+SATA\+\_\+\+PHY\+\_\+\+PROPERTIES}} \\*This structure defines the properties, specific to a SATA phy, that can be retrieved }{\pageref{structSCIC__SATA__PHY__PROPERTIES}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__CONTROLLER}{SCIC\+\_\+\+SDS\+\_\+\+CONTROLLER}} }{\pageref{structSCIC__SDS__CONTROLLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__CONTROLLER__STATE__HANDLER}{SCIC\+\_\+\+SDS\+\_\+\+CONTROLLER\+\_\+\+STATE\+\_\+\+HANDLER}} }{\pageref{structSCIC__SDS__CONTROLLER__STATE__HANDLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__IO__REQUEST}{SCIC\+\_\+\+SDS\+\_\+\+IO\+\_\+\+REQUEST}} \\*This structure contains or references all of the data necessary to process a task management or normal IO request }{\pageref{structSCIC__SDS__IO__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__IO__REQUEST__STATE__HANDLER}{SCIC\+\_\+\+SDS\+\_\+\+IO\+\_\+\+REQUEST\+\_\+\+STATE\+\_\+\+HANDLER}} \\*This is the SDS core definition of the state handlers }{\pageref{structSCIC__SDS__IO__REQUEST__STATE__HANDLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__LIBRARY}{SCIC\+\_\+\+SDS\+\_\+\+LIBRARY}} }{\pageref{structSCIC__SDS__LIBRARY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__OEM__PARAMETERS}{SCIC\+\_\+\+SDS\+\_\+\+OEM\+\_\+\+PARAMETERS}} \\*This structure delineates the various OEM parameters that must be set for the Intel SAS Storage Controller Unit (SCU) }{\pageref{structSCIC__SDS__OEM__PARAMETERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__PHY}{SCIC\+\_\+\+SDS\+\_\+\+PHY}} \\*This structure contains or references all of the data necessary to represent the core phy object and SCU hardware protocol engine }{\pageref{structSCIC__SDS__PHY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__PHY__STATE__HANDLER}{SCIC\+\_\+\+SDS\+\_\+\+PHY\+\_\+\+STATE\+\_\+\+HANDLER}} }{\pageref{structSCIC__SDS__PHY__STATE__HANDLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__PORT}{SCIC\+\_\+\+SDS\+\_\+\+PORT}} }{\pageref{structSCIC__SDS__PORT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__PORT__CONFIGURATION__AGENT}{SCIC\+\_\+\+SDS\+\_\+\+PORT\+\_\+\+CONFIGURATION\+\_\+\+AGENT}} }{\pageref{structSCIC__SDS__PORT__CONFIGURATION__AGENT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__PORT__RANGE}{SCIC\+\_\+\+SDS\+\_\+\+PORT\+\_\+\+RANGE}} }{\pageref{structSCIC__SDS__PORT__RANGE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__PORT__STATE__HANDLER}{SCIC\+\_\+\+SDS\+\_\+\+PORT\+\_\+\+STATE\+\_\+\+HANDLER}} }{\pageref{structSCIC__SDS__PORT__STATE__HANDLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__REMOTE__DEVICE}{SCIC\+\_\+\+SDS\+\_\+\+REMOTE\+\_\+\+DEVICE}} \\*This structure contains the data for an SCU implementation of the SCU Core device data }{\pageref{structSCIC__SDS__REMOTE__DEVICE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__REMOTE__DEVICE__STATE__HANDLER}{SCIC\+\_\+\+SDS\+\_\+\+REMOTE\+\_\+\+DEVICE\+\_\+\+STATE\+\_\+\+HANDLER}} \\*This structure conains the state handlers that are needed to process requests for the SCU remote device objects }{\pageref{structSCIC__SDS__REMOTE__DEVICE__STATE__HANDLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__REMOTE__NODE__CONTEXT}{SCIC\+\_\+\+SDS\+\_\+\+REMOTE\+\_\+\+NODE\+\_\+\+CONTEXT}} \\*This structure contains the data associated with the remote node context object. The remote node context (RNC) object models the remote device information necessary to manage the silicon RNC }{\pageref{structSCIC__SDS__REMOTE__NODE__CONTEXT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__REQUEST}{SCIC\+\_\+\+SDS\+\_\+\+REQUEST}} }{\pageref{structSCIC__SDS__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__STP__REQUEST}{SCIC\+\_\+\+SDS\+\_\+\+STP\+\_\+\+REQUEST}} }{\pageref{structSCIC__SDS__STP__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__UF__ADDRESS__TABLE__ARRAY}{SCIC\+\_\+\+SDS\+\_\+\+UF\+\_\+\+ADDRESS\+\_\+\+TABLE\+\_\+\+ARRAY}} }{\pageref{structSCIC__SDS__UF__ADDRESS__TABLE__ARRAY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__UF__BUFFER__ARRAY}{SCIC\+\_\+\+SDS\+\_\+\+UF\+\_\+\+BUFFER\+\_\+\+ARRAY}} }{\pageref{structSCIC__SDS__UF__BUFFER__ARRAY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__UF__HEADER__ARRAY}{SCIC\+\_\+\+SDS\+\_\+\+UF\+\_\+\+HEADER\+\_\+\+ARRAY}} }{\pageref{structSCIC__SDS__UF__HEADER__ARRAY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__UNSOLICITED__FRAME}{SCIC\+\_\+\+SDS\+\_\+\+UNSOLICITED\+\_\+\+FRAME}} }{\pageref{structSCIC__SDS__UNSOLICITED__FRAME}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__UNSOLICITED__FRAME__CONTROL}{SCIC\+\_\+\+SDS\+\_\+\+UNSOLICITED\+\_\+\+FRAME\+\_\+\+CONTROL}} }{\pageref{structSCIC__SDS__UNSOLICITED__FRAME__CONTROL}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SDS__USER__PARAMETERS}{SCIC\+\_\+\+SDS\+\_\+\+USER\+\_\+\+PARAMETERS}} \\*This structure delineates the various user parameters that can be changed by the core user }{\pageref{structSCIC__SDS__USER__PARAMETERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SMP__PASSTHRU__REQUEST__CALLBACKS}{SCIC\+\_\+\+SMP\+\_\+\+PASSTHRU\+\_\+\+REQUEST\+\_\+\+CALLBACKS}} \\*This structure contains the pointer to the callback functions for constructing the passthrough request specific to SMP. This structure must be set by the win sci layer before the passthrough build is called }{\pageref{structSCIC__SMP__PASSTHRU__REQUEST__CALLBACKS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__SSP__PASSTHRU__REQUEST__CALLBACKS}{SCIC\+\_\+\+SSP\+\_\+\+PASSTHRU\+\_\+\+REQUEST\+\_\+\+CALLBACKS}} \\*This structure contains the pointer to the callback functions for constructing the passthrough request specific to SSP. This structure must be set by the win sci layer before the passthrough build is called }{\pageref{structSCIC__SSP__PASSTHRU__REQUEST__CALLBACKS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIC__STP__PASSTHRU__REQUEST__CALLBACKS}{SCIC\+\_\+\+STP\+\_\+\+PASSTHRU\+\_\+\+REQUEST\+\_\+\+CALLBACKS}} \\*This structure contains the pointer to the callback functions for constructing the passthrough request specific to STP. This structure must be set by the win sci layer before the passthrough build is called }{\pageref{structSCIC__STP__PASSTHRU__REQUEST__CALLBACKS}}{}
\item\contentsline{section}{\mbox{\hyperlink{unionSCIC__USER__PARAMETERS}{SCIC\+\_\+\+USER\+\_\+\+PARAMETERS}} \\*This structure/union specifies the various different user parameter sets available. Each type is specific to a hardware controller version }{\pageref{unionSCIC__USER__PARAMETERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__CONTROLLER}{SCIF\+\_\+\+SAS\+\_\+\+CONTROLLER}} \\*The SCI SAS Framework controller object abstracts storage controller level behavior for the framework component }{\pageref{structSCIF__SAS__CONTROLLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__DOMAIN}{SCIF\+\_\+\+SAS\+\_\+\+DOMAIN}} \\*The SCI SAS Framework domain object abstracts the SAS domain level behavior for the framework component. Additionally, it provides a higher level of abstraction for the core port object. There is a 1\+:1 correspondance between core ports and framework domain objects. Essentially, each core port provides the access to the remote devices in the domain }{\pageref{structSCIF__SAS__DOMAIN}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__HIGH__PRIORITY__REQUEST__QUEUE}{SCIF\+\_\+\+SAS\+\_\+\+HIGH\+\_\+\+PRIORITY\+\_\+\+REQUEST\+\_\+\+QUEUE}} }{\pageref{structSCIF__SAS__HIGH__PRIORITY__REQUEST__QUEUE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__HIGH__PRIORITY__REQUEST__QUEUE__T}{SCIF\+\_\+\+SAS\+\_\+\+HIGH\+\_\+\+PRIORITY\+\_\+\+REQUEST\+\_\+\+QUEUE\+\_\+T}} \\*This structure depicts the fields contain in the high priority request queue (HPRQ) object. The HPRQ is used to store IO or task requests that need to be completed in short order }{\pageref{structSCIF__SAS__HIGH__PRIORITY__REQUEST__QUEUE__T}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__INTERNAL__IO__REQUEST}{SCIF\+\_\+\+SAS\+\_\+\+INTERNAL\+\_\+\+IO\+\_\+\+REQUEST}} \\*The \mbox{\hyperlink{structSCIF__SAS__INTERNAL__IO__REQUEST}{SCIF\+\_\+\+SAS\+\_\+\+INTERNAL\+\_\+\+IO\+\_\+\+REQUEST}} object represents the internal SAS IO request behavior for the framework component }{\pageref{structSCIF__SAS__INTERNAL__IO__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__IO__REQUEST}{SCIF\+\_\+\+SAS\+\_\+\+IO\+\_\+\+REQUEST}} \\*The SCI SAS Framework IO request object abstracts the SAS IO level behavior for the framework component. Additionally, it provides a higher level of abstraction for the core IO request object }{\pageref{structSCIF__SAS__IO__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__LIBRARY}{SCIF\+\_\+\+SAS\+\_\+\+LIBRARY}} \\*The SCI SAS Framework library object acts as the root of the containment hierarchy for all framework objects }{\pageref{structSCIF__SAS__LIBRARY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__LOCK}{SCIF\+\_\+\+SAS\+\_\+\+LOCK}} }{\pageref{structSCIF__SAS__LOCK}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__REMOTE__DEVICE}{SCIF\+\_\+\+SAS\+\_\+\+REMOTE\+\_\+\+DEVICE}} \\*The SCI SAS Framework remote device object abstracts the SAS remote device level behavior for the framework component. Additionally, it provides a higher level of abstraction for the core remote device object }{\pageref{structSCIF__SAS__REMOTE__DEVICE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__REMOTE__DEVICE__STATE__HANDLER}{SCIF\+\_\+\+SAS\+\_\+\+REMOTE\+\_\+\+DEVICE\+\_\+\+STATE\+\_\+\+HANDLER}} \\*This structure defines the state handler methods for states and substates applicable for the framework remote device object }{\pageref{structSCIF__SAS__REMOTE__DEVICE__STATE__HANDLER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__REQUEST}{SCIF\+\_\+\+SAS\+\_\+\+REQUEST}} \\*The \mbox{\hyperlink{structSCIF__SAS__REQUEST}{SCIF\+\_\+\+SAS\+\_\+\+REQUEST}} object abstracts the common SAS IO \& task management data and behavior for the framework component }{\pageref{structSCIF__SAS__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__SMP__PHY}{SCIF\+\_\+\+SAS\+\_\+\+SMP\+\_\+\+PHY}} \\*This structure stores data for a smp phy of a smp device (expander) }{\pageref{structSCIF__SAS__SMP__PHY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__SMP__REMOTE__DEVICE}{SCIF\+\_\+\+SAS\+\_\+\+SMP\+\_\+\+REMOTE\+\_\+\+DEVICE}} \\*The \mbox{\hyperlink{structSCIF__SAS__SMP__REMOTE__DEVICE}{SCIF\+\_\+\+SAS\+\_\+\+SMP\+\_\+\+REMOTE\+\_\+\+DEVICE}} stores data for smp remote devices (expanders) discovering attached targets }{\pageref{structSCIF__SAS__SMP__REMOTE__DEVICE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__STP__REMOTE__DEVICE}{SCIF\+\_\+\+SAS\+\_\+\+STP\+\_\+\+REMOTE\+\_\+\+DEVICE}} \\*The SCI SAS STP Framework remote device object abstracts the SAS SATA/\+STP remote device level behavior for the framework component }{\pageref{structSCIF__SAS__STP__REMOTE__DEVICE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__STP__REQUEST}{SCIF\+\_\+\+SAS\+\_\+\+STP\+\_\+\+REQUEST}} \\*This structure contains all of the data specific to performing SATA/\+STP IO and TASK requests }{\pageref{structSCIF__SAS__STP__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__STP__TASK__REQUEST}{SCIF\+\_\+\+SAS\+\_\+\+STP\+\_\+\+TASK\+\_\+\+REQUEST}} \\*This structure contains all of the data specific to performing SATA/\+STP IO requests }{\pageref{structSCIF__SAS__STP__TASK__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__TASK__REQUEST}{SCIF\+\_\+\+SAS\+\_\+\+TASK\+\_\+\+REQUEST}} \\*The SCI SAS Framework Task request object abstracts the SAS task management behavior for the framework component. Additionally, it provides a higher level of abstraction for the core task request object }{\pageref{structSCIF__SAS__TASK__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCIF__SAS__USER__PARAMETERS}{SCIF\+\_\+\+SAS\+\_\+\+USER\+\_\+\+PARAMETERS}} \\*This structure delineates the various user parameters that can be changed by the framework user }{\pageref{structSCIF__SAS__USER__PARAMETERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{unionSCIF__USER__PARAMETERS}{SCIF\+\_\+\+USER\+\_\+\+PARAMETERS}} \\*This structure/union specifies the various different user parameter sets available. Each type is specific to a Serial Attached SCSI implementation of the framework }{\pageref{unionSCIF__USER__PARAMETERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCSI__MODE__SELECT__MODE__PARAMETER__BLOCK__DESCRIPTOR}{SCSI\+\_\+\+MODE\+\_\+\+SELECT\+\_\+\+MODE\+\_\+\+PARAMETER\+\_\+\+BLOCK\+\_\+\+DESCRIPTOR}} }{\pageref{structSCSI__MODE__SELECT__MODE__PARAMETER__BLOCK__DESCRIPTOR}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCSI__MODE__SELECT__MODE__PARAMETER__HEADER__10}{SCSI\+\_\+\+MODE\+\_\+\+SELECT\+\_\+\+MODE\+\_\+\+PARAMETER\+\_\+\+HEADER\+\_\+10}} }{\pageref{structSCSI__MODE__SELECT__MODE__PARAMETER__HEADER__10}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCSI__MODE__SELECT__MODE__PARAMETER__HEADER__6}{SCSI\+\_\+\+MODE\+\_\+\+SELECT\+\_\+\+MODE\+\_\+\+PARAMETER\+\_\+\+HEADER\+\_\+6}} \\*This structure contains mode parameter header fields for 6 byte mode select command }{\pageref{structSCSI__MODE__SELECT__MODE__PARAMETER__HEADER__6}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__AFE__REGISTERS}{SCU\+\_\+\+AFE\+\_\+\+REGISTERS}} \\*AFE Regsiters See SCU AFE Specification for use of these registers }{\pageref{structSCU__AFE__REGISTERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__AFE__TRANSCEIVER}{SCU\+\_\+\+AFE\+\_\+\+TRANSCEIVER}} \\*AFE Transceiver Registers See SCU AFE Specification for use of these registers }{\pageref{structSCU__AFE__TRANSCEIVER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__COMPLETION__RAM}{SCU\+\_\+\+COMPLETION\+\_\+\+RAM}} \\*CRAM register. MMR base address for CRAMC is 0x6400 relative to SCUBAR }{\pageref{structSCU__COMPLETION__RAM}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__FRAME__BUFFER__RAM}{SCU\+\_\+\+FRAME\+\_\+\+BUFFER\+\_\+\+RAM}} \\*FBRAM registers. MMR base address for FBRAM is 0x6600 relative to SCUBAR }{\pageref{structSCU__FRAME__BUFFER__RAM}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__IIT__ENTRY}{SCU\+\_\+\+IIT\+\_\+\+ENTRY}} \\*This will be implemented later when we support virtual functions }{\pageref{structSCU__IIT__ENTRY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__LINK__LAYER__REGISTERS}{SCU\+\_\+\+LINK\+\_\+\+LAYER\+\_\+\+REGISTERS}} \\*SCU Link Layer Registers See the SCU SSLL Specification on how these registers are used }{\pageref{structSCU__LINK__LAYER__REGISTERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__PEG__REGISTERS}{SCU\+\_\+\+PEG\+\_\+\+REGISTERS}} \\*SCU Protocol Engine Memory mapped register space. These registers are unique to each protocol engine group. There can be at most two PEG for a single SCU part }{\pageref{structSCU__PEG__REGISTERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__PORT__TASK__SCHEDULER__GROUP__REGISTERS}{SCU\+\_\+\+PORT\+\_\+\+TASK\+\_\+\+SCHEDULER\+\_\+\+GROUP\+\_\+\+REGISTERS}} \\*These are the PORT Task Scheduler registers See the SCU SCHED Specification on how these registers are used }{\pageref{structSCU__PORT__TASK__SCHEDULER__GROUP__REGISTERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__PORT__TASK__SCHEDULER__REGISTERS}{SCU\+\_\+\+PORT\+\_\+\+TASK\+\_\+\+SCHEDULER\+\_\+\+REGISTERS}} \\*These are the control/stats pairs for each Port Task Scheduler. See the SCU SCHED Specification on how these registers are used }{\pageref{structSCU__PORT__TASK__SCHEDULER__REGISTERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__PROTOCOL__ENGINE__GROUP__REGISTERS}{SCU\+\_\+\+PROTOCOL\+\_\+\+ENGINE\+\_\+\+GROUP\+\_\+\+REGISTERS}} }{\pageref{structSCU__PROTOCOL__ENGINE__GROUP__REGISTERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__REGISTERS}{SCU\+\_\+\+REGISTERS}} \\*SCU regsiters including both PEG registers if we turn on that compile option. All of these registers are in the memory mapped space returned from BAR1. See SCU SMU Specification for how these registers are mapped }{\pageref{structSCU__REGISTERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{unionSCU__REMOTE__NODE__CONTEXT}{SCU\+\_\+\+REMOTE\+\_\+\+NODE\+\_\+\+CONTEXT}} \\*This union combines the SAS and SATA remote node definitions }{\pageref{unionSCU__REMOTE__NODE__CONTEXT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__SCRATCH__RAM}{SCU\+\_\+\+SCRATCH\+\_\+\+RAM}} \\*Placeholder for the scratch RAM registers }{\pageref{structSCU__SCRATCH__RAM}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__SDMA__REGISTERS}{SCU\+\_\+\+SDMA\+\_\+\+REGISTERS}} \\*These are the SCU SDMA Registers See SCU SDMA specification on how these registers are used }{\pageref{structSCU__SDMA__REGISTERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__SGL__ELEMENT}{SCU\+\_\+\+SGL\+\_\+\+ELEMENT}} }{\pageref{structSCU__SGL__ELEMENT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__SGL__ELEMENT__PAIR}{SCU\+\_\+\+SGL\+\_\+\+ELEMENT\+\_\+\+PAIR}} \\*This structure is the SCU hardware definition of a pair of SGL elements }{\pageref{structSCU__SGL__ELEMENT__PAIR}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__SGPIO__REGISTERS}{SCU\+\_\+\+SGPIO\+\_\+\+REGISTERS}} \\*SCU SGPIO Registers See the SCU SGPIO Specification on how these registers are used }{\pageref{structSCU__SGPIO__REGISTERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__TASK__CONTEXT}{SCU\+\_\+\+TASK\+\_\+\+CONTEXT}} \\*This structure defines the contents of the SCU silicon task context. It lays out all of the fields according to the expected order and location for the Storage Controller unit }{\pageref{structSCU__TASK__CONTEXT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__TRANSPORT__LAYER__REGISTERS}{SCU\+\_\+\+TRANSPORT\+\_\+\+LAYER\+\_\+\+REGISTERS}} \\*These are the SCU Transport Layer registers see SSPTL spec for how they are used }{\pageref{structSCU__TRANSPORT__LAYER__REGISTERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__UNSOLICITED__FRAME__HEADER}{SCU\+\_\+\+UNSOLICITED\+\_\+\+FRAME\+\_\+\+HEADER}} }{\pageref{structSCU__UNSOLICITED__FRAME__HEADER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__VIIT__ENTRY}{SCU\+\_\+\+VIIT\+\_\+\+ENTRY}} \\*This is the SCU Virtual Initiator Table Entry }{\pageref{structSCU__VIIT__ENTRY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__VIIT__IIT}{SCU\+\_\+\+VIIT\+\_\+\+IIT}} }{\pageref{structSCU__VIIT__IIT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__VIIT__REGISTERS}{SCU\+\_\+\+VIIT\+\_\+\+REGISTERS}} }{\pageref{structSCU__VIIT__REGISTERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSCU__ZONE__PARTITION__TABLE}{SCU\+\_\+\+ZONE\+\_\+\+PARTITION\+\_\+\+TABLE}} \\*Placeholder for the ZONE Partition Table information ZONING will not be included in the 1.\+1 release }{\pageref{structSCU__ZONE__PARTITION__TABLE}}{}
\item\contentsline{section}{\mbox{\hyperlink{structATA__SMART__DESCRIPTOR__ENTRY_1_1SMART__DESCRIPTOR__ENTRY}{ATA\+\_\+\+SMART\+\_\+\+DESCRIPTOR\+\_\+\+ENTRY\+::\+SMART\+\_\+\+DESCRIPTOR\+\_\+\+ENTRY}} }{\pageref{structATA__SMART__DESCRIPTOR__ENTRY_1_1SMART__DESCRIPTOR__ENTRY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__DISCOVER__RESPONSE__PROTOCOLS}{SMP\+\_\+\+DISCOVER\+\_\+\+RESPONSE\+\_\+\+PROTOCOLS}} \\*This structure depicts the discover response where the supported protocols by the remote phy are specified }{\pageref{structSMP__DISCOVER__RESPONSE__PROTOCOLS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__REQUEST}{SMP\+\_\+\+REQUEST}} \\*This structure simply unionizes the existing request structures into a common request type }{\pageref{structSMP__REQUEST}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__REQUEST__CONFIGURE__ROUTE__INFORMATION}{SMP\+\_\+\+REQUEST\+\_\+\+CONFIGURE\+\_\+\+ROUTE\+\_\+\+INFORMATION}} \\*This structure defines the contents of an SMP Configure Route Information request }{\pageref{structSMP__REQUEST__CONFIGURE__ROUTE__INFORMATION}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__REQUEST__GENERAL}{SMP\+\_\+\+REQUEST\+\_\+\+GENERAL}} \\*This structure defines the contents of an SMP Request that is comprised of the \mbox{\hyperlink{structSMP__REQUEST__HEADER}{SMP\+\_\+\+REQUEST\+\_\+\+HEADER}} and a CRC }{\pageref{structSMP__REQUEST__GENERAL}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__REQUEST__HEADER}{SMP\+\_\+\+REQUEST\+\_\+\+HEADER}} \\*This structure defines the contents of an SMP Request header }{\pageref{structSMP__REQUEST__HEADER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__REQUEST__PHY__CONTROL}{SMP\+\_\+\+REQUEST\+\_\+\+PHY\+\_\+\+CONTROL}} \\*This structure defines the contents of an SMP Phy Controller request }{\pageref{structSMP__REQUEST__PHY__CONTROL}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__REQUEST__PHY__IDENTIFIER}{SMP\+\_\+\+REQUEST\+\_\+\+PHY\+\_\+\+IDENTIFIER}} \\*This structure defines the contents of an SMP Request that is comprised of the \mbox{\hyperlink{structSMP__REQUEST__HEADER}{SMP\+\_\+\+REQUEST\+\_\+\+HEADER}} and a phy identifier. Examples\+: SMP\+\_\+\+REQUEST\+\_\+\+DISCOVER, SMP\+\_\+\+REQUEST\+\_\+\+REPORT\+\_\+\+PHY\+\_\+\+SATA }{\pageref{structSMP__REQUEST__PHY__IDENTIFIER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__REQUEST__VENDOR__SPECIFIC}{SMP\+\_\+\+REQUEST\+\_\+\+VENDOR\+\_\+\+SPECIFIC}} \\*This structure depicts the vendor specific space for SMP request }{\pageref{structSMP__REQUEST__VENDOR__SPECIFIC}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__RESPONSE}{SMP\+\_\+\+RESPONSE}} \\*This structure simply unionizes the existing response structures into a common response type }{\pageref{structSMP__RESPONSE}}{}
\item\contentsline{section}{\mbox{\hyperlink{unionSMP__RESPONSE__BODY}{SMP\+\_\+\+RESPONSE\+\_\+\+BODY}} }{\pageref{unionSMP__RESPONSE__BODY}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__RESPONSE__DISCOVER}{SMP\+\_\+\+RESPONSE\+\_\+\+DISCOVER}} }{\pageref{structSMP__RESPONSE__DISCOVER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__RESPONSE__DISCOVER__FORMAT}{SMP\+\_\+\+RESPONSE\+\_\+\+DISCOVER\+\_\+\+FORMAT}} \\*This structure defines the SMP phy discover response format. It handles both SAS1.\+1 and SAS 2 definitions. The unions indicate locations where the SAS specification versions differ from one another }{\pageref{structSMP__RESPONSE__DISCOVER__FORMAT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__RESPONSE__HEADER}{SMP\+\_\+\+RESPONSE\+\_\+\+HEADER}} \\*This structure depicts the contents of the SAS SMP DISCOVER RESPONSE frame. For specific information on each of these individual fields please reference the SAS specification Link layer section on address frames }{\pageref{structSMP__RESPONSE__HEADER}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__RESPONSE__REPORT__GENERAL}{SMP\+\_\+\+RESPONSE\+\_\+\+REPORT\+\_\+\+GENERAL}} \\*This structure depicts the SMP Report General for expander devices. It adheres to the SAS-\/2.\+1 specification }{\pageref{structSMP__RESPONSE__REPORT__GENERAL}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__RESPONSE__REPORT__GENERAL__LONG}{SMP\+\_\+\+RESPONSE\+\_\+\+REPORT\+\_\+\+GENERAL\+\_\+\+LONG}} }{\pageref{structSMP__RESPONSE__REPORT__GENERAL__LONG}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__RESPONSE__REPORT__MANUFACTURER__INFORMATION}{SMP\+\_\+\+RESPONSE\+\_\+\+REPORT\+\_\+\+MANUFACTURER\+\_\+\+INFORMATION}} \\*This structure depicts the SMP report manufacturer information for expander devices. It adheres to the SAS-\/2.\+1 specification }{\pageref{structSMP__RESPONSE__REPORT__MANUFACTURER__INFORMATION}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__RESPONSE__REPORT__PHY__SATA}{SMP\+\_\+\+RESPONSE\+\_\+\+REPORT\+\_\+\+PHY\+\_\+\+SATA}} \\*This structure depicts the contents of the SAS SMP REPORT PHY SATA frame. For specific information on each of these individual fields please reference the SAS specification Link layer section on address frames }{\pageref{structSMP__RESPONSE__REPORT__PHY__SATA}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__RESPONSE__VENDOR__SPECIFIC}{SMP\+\_\+\+RESPONSE\+\_\+\+VENDOR\+\_\+\+SPECIFIC}} }{\pageref{structSMP__RESPONSE__VENDOR__SPECIFIC}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMP__TASK__CONTEXT}{SMP\+\_\+\+TASK\+\_\+\+CONTEXT}} \\*This is the SCU hardware definition for an SMP request }{\pageref{structSMP__TASK__CONTEXT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSMU__REGISTERS}{SMU\+\_\+\+REGISTERS}} \\*These are the SMU registers See SCU SMU Specification on how this register space is used }{\pageref{structSMU__REGISTERS}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSSP__REMOTE__NODE__CONTEXT}{SSP\+\_\+\+REMOTE\+\_\+\+NODE\+\_\+\+CONTEXT}} \\*This structure contains the SCU hardware definition for an SSP remote node }{\pageref{structSSP__REMOTE__NODE__CONTEXT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSSP__TASK__CONTEXT}{SSP\+\_\+\+TASK\+\_\+\+CONTEXT}} \\*This is the SCU hardware definition for an SSP request }{\pageref{structSSP__TASK__CONTEXT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSTP__REMOTE__NODE__CONTEXT}{STP\+\_\+\+REMOTE\+\_\+\+NODE\+\_\+\+CONTEXT}} \\*This structure contains the SCU hardware definition for a STP remote node }{\pageref{structSTP__REMOTE__NODE__CONTEXT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structSTP__TASK__CONTEXT}{STP\+\_\+\+TASK\+\_\+\+CONTEXT}} \\*This is the SCU hardware definition for an STP request }{\pageref{structSTP__TASK__CONTEXT}}{}
\item\contentsline{section}{\mbox{\hyperlink{structTRANSPORT__LINK__LAYER__PAIR}{TRANSPORT\+\_\+\+LINK\+\_\+\+LAYER\+\_\+\+PAIR}} \\*The SCU Hardware pairs up the TL registers with the LL registers so we must place them adjcent to make the array of registers in the PEG }{\pageref{structTRANSPORT__LINK__LAYER__PAIR}}{}
\item\contentsline{section}{\mbox{\hyperlink{structTRANSPORT__SNAPSHOT}{TRANSPORT\+\_\+\+SNAPSHOT}} \\*This structure is the SCU hardware scratch area for the task context }{\pageref{structTRANSPORT__SNAPSHOT}}{}
\end{DoxyCompactList}
