\hypertarget{xhcireg_8h_source}{}\doxysection{xhcireg.\+h}
\label{xhcireg_8h_source}\index{dev/usb/controller/xhcireg.h@{dev/usb/controller/xhcireg.h}}
\mbox{\hyperlink{xhcireg_8h}{Go to the documentation of this file.}}
\begin{DoxyCode}{0}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00001}00001 \textcolor{comment}{/* \$FreeBSD\$ */}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00002}00002 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00003}00003 \textcolor{comment}{/*-\/}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00004}00004 \textcolor{comment}{ * SPDX-\/License-\/Identifier: BSD-\/2-\/Clause-\/FreeBSD}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00005}00005 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00006}00006 \textcolor{comment}{ * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00007}00007 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00008}00008 \textcolor{comment}{ * Redistribution and use in source and binary forms, with or without}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00009}00009 \textcolor{comment}{ * modification, are permitted provided that the following conditions}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00010}00010 \textcolor{comment}{ * are met:}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00011}00011 \textcolor{comment}{ * 1. Redistributions of source code must retain the above copyright}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00012}00012 \textcolor{comment}{ *    notice, this list of conditions and the following disclaimer.}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00013}00013 \textcolor{comment}{ * 2. Redistributions in binary form must reproduce the above copyright}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00014}00014 \textcolor{comment}{ *    notice, this list of conditions and the following disclaimer in the}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00015}00015 \textcolor{comment}{ *    documentation and/or other materials provided with the distribution.}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00016}00016 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00017}00017 \textcolor{comment}{ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00018}00018 \textcolor{comment}{ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00019}00019 \textcolor{comment}{ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00020}00020 \textcolor{comment}{ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00021}00021 \textcolor{comment}{ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00022}00022 \textcolor{comment}{ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00023}00023 \textcolor{comment}{ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00024}00024 \textcolor{comment}{ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00025}00025 \textcolor{comment}{ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00026}00026 \textcolor{comment}{ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00027}00027 \textcolor{comment}{ * SUCH DAMAGE.}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00028}00028 \textcolor{comment}{ */}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00029}00029 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00030}00030 \textcolor{preprocessor}{\#ifndef \_XHCIREG\_H\_}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00031}00031 \textcolor{preprocessor}{\#define \_XHCIREG\_H\_}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00032}00032 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00033}00033 \textcolor{comment}{/* XHCI PCI config registers */}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00034}\mbox{\hyperlink{xhcireg_8h_ad6e30131b3bcc1dc00c99e562ffdf472}{00034}} \textcolor{preprocessor}{\#define PCI\_XHCI\_CBMEM          0x10    }\textcolor{comment}{/* configuration base MEM */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00035}\mbox{\hyperlink{xhcireg_8h_a075972e844d4504fcd704ec0bf361cd7}{00035}} \textcolor{preprocessor}{\#define PCI\_XHCI\_USBREV         0x60    }\textcolor{comment}{/* RO USB protocol revision */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00036}\mbox{\hyperlink{xhcireg_8h_a1bc8964ed5783a3360b16f35aa3ff1a9}{00036}} \textcolor{preprocessor}{\#define PCI\_USB\_REV\_3\_0         0x30    }\textcolor{comment}{/* USB 3.0 */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00037}\mbox{\hyperlink{xhcireg_8h_abc8f7dfb8347eb3596d687bdcc83e6ed}{00037}} \textcolor{preprocessor}{\#define PCI\_XHCI\_FLADJ          0x61    }\textcolor{comment}{/* RW frame length adjust */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00038}00038 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00039}\mbox{\hyperlink{xhcireg_8h_a1094c3d5d6e9b11925cab60fe0a355a1}{00039}} \textcolor{preprocessor}{\#define PCI\_XHCI\_INTEL\_XUSB2PR  0xD0    }\textcolor{comment}{/* Intel USB2 Port Routing */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00040}\mbox{\hyperlink{xhcireg_8h_ae51eeea91489aaa82c04fa5d0a180a55}{00040}} \textcolor{preprocessor}{\#define PCI\_XHCI\_INTEL\_USB2PRM  0xD4    }\textcolor{comment}{/* Intel USB2 Port Routing Mask */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00041}\mbox{\hyperlink{xhcireg_8h_ae0666a45f422d69240781733b86b160c}{00041}} \textcolor{preprocessor}{\#define PCI\_XHCI\_INTEL\_USB3\_PSSEN 0xD8  }\textcolor{comment}{/* Intel USB3 Port SuperSpeed Enable */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00042}\mbox{\hyperlink{xhcireg_8h_a6a60ed89e112f254aa57c0aa26453c89}{00042}} \textcolor{preprocessor}{\#define PCI\_XHCI\_INTEL\_USB3PRM  0xDC    }\textcolor{comment}{/* Intel USB3 Port Routing Mask */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00043}00043 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00044}00044 \textcolor{comment}{/* XHCI capability registers */}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00045}\mbox{\hyperlink{xhcireg_8h_a9eb421accfa3703cbd3cc412cb4c248a}{00045}} \textcolor{preprocessor}{\#define XHCI\_CAPLENGTH          0x00    }\textcolor{comment}{/* RO capability */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00046}\mbox{\hyperlink{xhcireg_8h_a5c5346a47466f6d97fd388e623cf24dc}{00046}} \textcolor{preprocessor}{\#define XHCI\_RESERVED           0x01    }\textcolor{comment}{/* Reserved */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00047}\mbox{\hyperlink{xhcireg_8h_ac0e3294d2230f4cf1c8343bc6cea3e6c}{00047}} \textcolor{preprocessor}{\#define XHCI\_HCIVERSION         0x02    }\textcolor{comment}{/* RO Interface version number */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00048}\mbox{\hyperlink{xhcireg_8h_afa3c9f8d5187958014d82a53be2dbec4}{00048}} \textcolor{preprocessor}{\#define XHCI\_HCIVERSION\_0\_9     0x0090  }\textcolor{comment}{/* xHCI version 0.9 */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00049}\mbox{\hyperlink{xhcireg_8h_afa79277be9fd556c10bc95cf685dea16}{00049}} \textcolor{preprocessor}{\#define XHCI\_HCIVERSION\_1\_0     0x0100  }\textcolor{comment}{/* xHCI version 1.0 */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00050}\mbox{\hyperlink{xhcireg_8h_abe894882caf19ae9166ec01f62a8c04a}{00050}} \textcolor{preprocessor}{\#define XHCI\_HCSPARAMS1         0x04    }\textcolor{comment}{/* RO structural parameters 1 */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00051}\mbox{\hyperlink{xhcireg_8h_ade1a03e3249532249360050c8923cc06}{00051}} \textcolor{preprocessor}{\#define XHCI\_HCS1\_DEVSLOT\_MAX(x)((x) \& 0xFF)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00052}\mbox{\hyperlink{xhcireg_8h_a32991da45264fc25121a314ea9dc3dfb}{00052}} \textcolor{preprocessor}{\#define XHCI\_HCS1\_IRQ\_MAX(x)    (((x) >> 8) \& 0x3FF)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00053}\mbox{\hyperlink{xhcireg_8h_ad5a7839d67ed3df6302229a037783fbc}{00053}} \textcolor{preprocessor}{\#define XHCI\_HCS1\_N\_PORTS(x)    (((x) >> 24) \& 0xFF)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00054}\mbox{\hyperlink{xhcireg_8h_a6835159e3a6e9944b5a0ce49e0c9a514}{00054}} \textcolor{preprocessor}{\#define XHCI\_HCSPARAMS2         0x08    }\textcolor{comment}{/* RO structural parameters 2 */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00055}\mbox{\hyperlink{xhcireg_8h_afb7d2a1d25d30ddedc2c9ab9eda25b08}{00055}} \textcolor{preprocessor}{\#define XHCI\_HCS2\_IST(x)        ((x) \& 0xF)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00056}\mbox{\hyperlink{xhcireg_8h_a150598a334f942b8701fe55ff5fa52d1}{00056}} \textcolor{preprocessor}{\#define XHCI\_HCS2\_ERST\_MAX(x)   (((x) >> 4) \& 0xF)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00057}\mbox{\hyperlink{xhcireg_8h_a204c8896a9fa729b4496aad938129cc1}{00057}} \textcolor{preprocessor}{\#define XHCI\_HCS2\_SPR(x)        (((x) >> 26) \& 0x1)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00058}\mbox{\hyperlink{xhcireg_8h_ae7f7ce7b9abe19f6a432da3a1e081955}{00058}} \textcolor{preprocessor}{\#define XHCI\_HCS2\_SPB\_MAX(x)    ((((x) >> 16) \& 0x3E0) | (((x) >> 27) \& 0x1F))}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00059}\mbox{\hyperlink{xhcireg_8h_a4c4760835948e3fc08c3f31a4820deca}{00059}} \textcolor{preprocessor}{\#define XHCI\_HCSPARAMS3         0x0C    }\textcolor{comment}{/* RO structural parameters 3 */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00060}\mbox{\hyperlink{xhcireg_8h_aaa6bc83b8c8c4b364c1c985e37707219}{00060}} \textcolor{preprocessor}{\#define XHCI\_HCS3\_U1\_DEL(x)     ((x) \& 0xFF)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00061}\mbox{\hyperlink{xhcireg_8h_a28e901909c9b51d42b6c0f3b3afdd337}{00061}} \textcolor{preprocessor}{\#define XHCI\_HCS3\_U2\_DEL(x)     (((x) >> 16) \& 0xFFFF)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00062}\mbox{\hyperlink{xhcireg_8h_a4dc5731fb089b7c91cfa13cf3c62c6b5}{00062}} \textcolor{preprocessor}{\#define XHCI\_HCSPARAMS0         0x10    }\textcolor{comment}{/* RO capability parameters */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00063}\mbox{\hyperlink{xhcireg_8h_a56610946618533c9dd1f282b8f2f531e}{00063}} \textcolor{preprocessor}{\#define XHCI\_HCS0\_AC64(x)       ((x) \& 0x1)             }\textcolor{comment}{/* 64-\/bit capable */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00064}\mbox{\hyperlink{xhcireg_8h_aeee473716e33d853e27a2fafef950221}{00064}} \textcolor{preprocessor}{\#define XHCI\_HCS0\_BNC(x)        (((x) >> 1) \& 0x1)      }\textcolor{comment}{/* BW negotiation */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00065}\mbox{\hyperlink{xhcireg_8h_a2dedde0ccc57f632c7c0f49a8c4fc878}{00065}} \textcolor{preprocessor}{\#define XHCI\_HCS0\_CSZ(x)        (((x) >> 2) \& 0x1)      }\textcolor{comment}{/* context size */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00066}\mbox{\hyperlink{xhcireg_8h_ae9303dcf9dce3f1c7c1fcbb8b9033789}{00066}} \textcolor{preprocessor}{\#define XHCI\_HCS0\_PPC(x)        (((x) >> 3) \& 0x1)      }\textcolor{comment}{/* port power control */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00067}\mbox{\hyperlink{xhcireg_8h_a011ef15f56ad4483ef709e436a0d371d}{00067}} \textcolor{preprocessor}{\#define XHCI\_HCS0\_PIND(x)       (((x) >> 4) \& 0x1)      }\textcolor{comment}{/* port indicators */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00068}\mbox{\hyperlink{xhcireg_8h_a2f66cd96b897b987baf6510f033076d7}{00068}} \textcolor{preprocessor}{\#define XHCI\_HCS0\_LHRC(x)       (((x) >> 5) \& 0x1)      }\textcolor{comment}{/* light HC reset */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00069}\mbox{\hyperlink{xhcireg_8h_a037eb9d6cf494bb4a04475bc7fa6dc3a}{00069}} \textcolor{preprocessor}{\#define XHCI\_HCS0\_LTC(x)        (((x) >> 6) \& 0x1)      }\textcolor{comment}{/* latency tolerance msg */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00070}\mbox{\hyperlink{xhcireg_8h_adef5bfe51694d751e6c5ab2c9482f3d0}{00070}} \textcolor{preprocessor}{\#define XHCI\_HCS0\_NSS(x)        (((x) >> 7) \& 0x1)      }\textcolor{comment}{/* no secondary sid */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00071}\mbox{\hyperlink{xhcireg_8h_ac0e7fc8f17308c485bd370da2772e40d}{00071}} \textcolor{preprocessor}{\#define XHCI\_HCS0\_PSA\_SZ\_MAX(x) (((x) >> 12) \& 0xF)     }\textcolor{comment}{/* max pri. stream array size */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00072}\mbox{\hyperlink{xhcireg_8h_a688e0d926ad9f4bbd14472a204bc3723}{00072}} \textcolor{preprocessor}{\#define XHCI\_HCS0\_XECP(x)       (((x) >> 16) \& 0xFFFF)  }\textcolor{comment}{/* extended capabilities pointer */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00073}\mbox{\hyperlink{xhcireg_8h_aa78159a18783ebe5c4ccb1ad666a5658}{00073}} \textcolor{preprocessor}{\#define XHCI\_DBOFF              0x14    }\textcolor{comment}{/* RO doorbell offset */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00074}\mbox{\hyperlink{xhcireg_8h_a2419137254c9e37d5225f136751dcbfa}{00074}} \textcolor{preprocessor}{\#define XHCI\_RTSOFF             0x18    }\textcolor{comment}{/* RO runtime register space offset */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00075}00075 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00076}00076 \textcolor{comment}{/* XHCI operational registers.  Offset given by XHCI\_CAPLENGTH register */}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00077}\mbox{\hyperlink{xhcireg_8h_a1d6d2838b0a4b24cd4067572523ee346}{00077}} \textcolor{preprocessor}{\#define XHCI\_USBCMD             0x00    }\textcolor{comment}{/* XHCI command */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00078}\mbox{\hyperlink{xhcireg_8h_a1e13f11c24817d264c199ee4714ec13b}{00078}} \textcolor{preprocessor}{\#define XHCI\_CMD\_RS             0x00000001      }\textcolor{comment}{/* RW Run/Stop */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00079}\mbox{\hyperlink{xhcireg_8h_ad2a59ed3421ba1e51afd3ee773879b85}{00079}} \textcolor{preprocessor}{\#define XHCI\_CMD\_HCRST          0x00000002      }\textcolor{comment}{/* RW Host Controller Reset */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00080}\mbox{\hyperlink{xhcireg_8h_aff9c6d6c7a2f437c79cd18b9e2645dd7}{00080}} \textcolor{preprocessor}{\#define XHCI\_CMD\_INTE           0x00000004      }\textcolor{comment}{/* RW Interrupter Enable */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00081}\mbox{\hyperlink{xhcireg_8h_a5072372af7147a9494b45445a2679786}{00081}} \textcolor{preprocessor}{\#define XHCI\_CMD\_HSEE           0x00000008      }\textcolor{comment}{/* RW Host System Error Enable */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00082}\mbox{\hyperlink{xhcireg_8h_a7f471a4e5c91e1a93d412f9f72eda866}{00082}} \textcolor{preprocessor}{\#define XHCI\_CMD\_LHCRST         0x00000080      }\textcolor{comment}{/* RO/RW Light Host Controller Reset */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00083}\mbox{\hyperlink{xhcireg_8h_a4b61a78b2af5b66702c29fb0ba6e7293}{00083}} \textcolor{preprocessor}{\#define XHCI\_CMD\_CSS            0x00000100      }\textcolor{comment}{/* RW Controller Save State */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00084}\mbox{\hyperlink{xhcireg_8h_ac4c8dd247851d11be904a3e24454ff45}{00084}} \textcolor{preprocessor}{\#define XHCI\_CMD\_CRS            0x00000200      }\textcolor{comment}{/* RW Controller Restore State */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00085}\mbox{\hyperlink{xhcireg_8h_aa8c7a39ff42d5f6e2f0a4bddaf3522ab}{00085}} \textcolor{preprocessor}{\#define XHCI\_CMD\_EWE            0x00000400      }\textcolor{comment}{/* RW Enable Wrap Event */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00086}\mbox{\hyperlink{xhcireg_8h_a951b3d8819e9e52bd84c93ef2d0a184a}{00086}} \textcolor{preprocessor}{\#define XHCI\_CMD\_EU3S           0x00000800      }\textcolor{comment}{/* RW Enable U3 MFINDEX Stop */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00087}\mbox{\hyperlink{xhcireg_8h_aac4af15758e601077fbefb4465b0d8d7}{00087}} \textcolor{preprocessor}{\#define XHCI\_USBSTS             0x04    }\textcolor{comment}{/* XHCI status */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00088}\mbox{\hyperlink{xhcireg_8h_a0388c1acea4a4b50c5a61ebde8df68b0}{00088}} \textcolor{preprocessor}{\#define XHCI\_STS\_HCH            0x00000001      }\textcolor{comment}{/* RO -\/ Host Controller Halted */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00089}\mbox{\hyperlink{xhcireg_8h_a560471703723a2e934a30e60b5b8934d}{00089}} \textcolor{preprocessor}{\#define XHCI\_STS\_HSE            0x00000004      }\textcolor{comment}{/* RW -\/ Host System Error */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00090}\mbox{\hyperlink{xhcireg_8h_a161da31ba05848c4fce976e3c4921a95}{00090}} \textcolor{preprocessor}{\#define XHCI\_STS\_EINT           0x00000008      }\textcolor{comment}{/* RW -\/ Event Interrupt */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00091}\mbox{\hyperlink{xhcireg_8h_a170e64bde9bb0790ea2fbe9f19338162}{00091}} \textcolor{preprocessor}{\#define XHCI\_STS\_PCD            0x00000010      }\textcolor{comment}{/* RW -\/ Port Change Detect */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00092}\mbox{\hyperlink{xhcireg_8h_a91532520cd833d4e2eea3ffc394da4a4}{00092}} \textcolor{preprocessor}{\#define XHCI\_STS\_SSS            0x00000100      }\textcolor{comment}{/* RO -\/ Save State Status */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00093}\mbox{\hyperlink{xhcireg_8h_a8144741c0e3f12735c4cba3cf23c40c4}{00093}} \textcolor{preprocessor}{\#define XHCI\_STS\_RSS            0x00000200      }\textcolor{comment}{/* RO -\/ Restore State Status */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00094}\mbox{\hyperlink{xhcireg_8h_a9aa30dd2e8ef161eeedf5bc70da4d91a}{00094}} \textcolor{preprocessor}{\#define XHCI\_STS\_SRE            0x00000400      }\textcolor{comment}{/* RW -\/ Save/Restore Error */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00095}\mbox{\hyperlink{xhcireg_8h_af132c9d4d7fa59c09448301919db3e39}{00095}} \textcolor{preprocessor}{\#define XHCI\_STS\_CNR            0x00000800      }\textcolor{comment}{/* RO -\/ Controller Not Ready */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00096}\mbox{\hyperlink{xhcireg_8h_a28763f546507ec7ac06e27b9b24758f3}{00096}} \textcolor{preprocessor}{\#define XHCI\_STS\_HCE            0x00001000      }\textcolor{comment}{/* RO -\/ Host Controller Error */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00097}\mbox{\hyperlink{xhcireg_8h_a58eca7c7aeecb3b2041c78d324958d5c}{00097}} \textcolor{preprocessor}{\#define XHCI\_PAGESIZE           0x08    }\textcolor{comment}{/* XHCI page size mask */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00098}\mbox{\hyperlink{xhcireg_8h_af216d2cc0c27b7cbd5bf0d243fedd7f5}{00098}} \textcolor{preprocessor}{\#define XHCI\_PAGESIZE\_4K        0x00000001      }\textcolor{comment}{/* 4K Page Size */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00099}\mbox{\hyperlink{xhcireg_8h_a10943942313758ea6968ce8b2aa5b64f}{00099}} \textcolor{preprocessor}{\#define XHCI\_PAGESIZE\_8K        0x00000002      }\textcolor{comment}{/* 8K Page Size */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00100}\mbox{\hyperlink{xhcireg_8h_a9f55ff2cfa46ae21b063d5a077a2b9a7}{00100}} \textcolor{preprocessor}{\#define XHCI\_PAGESIZE\_16K       0x00000004      }\textcolor{comment}{/* 16K Page Size */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00101}\mbox{\hyperlink{xhcireg_8h_a04448e17d205569085b8347bd469d6cf}{00101}} \textcolor{preprocessor}{\#define XHCI\_PAGESIZE\_32K       0x00000008      }\textcolor{comment}{/* 32K Page Size */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00102}\mbox{\hyperlink{xhcireg_8h_a1f0cbe2c50901b1a0f19fddbc75ad6a7}{00102}} \textcolor{preprocessor}{\#define XHCI\_PAGESIZE\_64K       0x00000010      }\textcolor{comment}{/* 64K Page Size */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00103}\mbox{\hyperlink{xhcireg_8h_a034e24d4522fa3c26ab1ad8771f71179}{00103}} \textcolor{preprocessor}{\#define XHCI\_DNCTRL             0x14    }\textcolor{comment}{/* XHCI device notification control */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00104}\mbox{\hyperlink{xhcireg_8h_a7ab405587f79a057bd9251ed0863a2c0}{00104}} \textcolor{preprocessor}{\#define XHCI\_DNCTRL\_MASK(n)     (1U << (n))}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00105}\mbox{\hyperlink{xhcireg_8h_ac90d9513cbbcb160fa2438040c919647}{00105}} \textcolor{preprocessor}{\#define XHCI\_CRCR\_LO            0x18    }\textcolor{comment}{/* XHCI command ring control */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00106}\mbox{\hyperlink{xhcireg_8h_a4d3ffe4c6482cae83c912ad1777278cd}{00106}} \textcolor{preprocessor}{\#define XHCI\_CRCR\_LO\_RCS        0x00000001      }\textcolor{comment}{/* RW -\/ consumer cycle state */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00107}\mbox{\hyperlink{xhcireg_8h_a2622341abd8c467d5d3006a77f3bd09f}{00107}} \textcolor{preprocessor}{\#define XHCI\_CRCR\_LO\_CS         0x00000002      }\textcolor{comment}{/* RW -\/ command stop */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00108}\mbox{\hyperlink{xhcireg_8h_a3bb5ca7214d759f15e6c44c38f966e9e}{00108}} \textcolor{preprocessor}{\#define XHCI\_CRCR\_LO\_CA         0x00000004      }\textcolor{comment}{/* RW -\/ command abort */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00109}\mbox{\hyperlink{xhcireg_8h_a18cd4b3bf848d6837f50ea5c0cb9b9ed}{00109}} \textcolor{preprocessor}{\#define XHCI\_CRCR\_LO\_CRR        0x00000008      }\textcolor{comment}{/* RW -\/ command ring running */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00110}\mbox{\hyperlink{xhcireg_8h_a31ab4176b1cf3f01e5bb5c97ab4260de}{00110}} \textcolor{preprocessor}{\#define XHCI\_CRCR\_LO\_MASK       0x0000000F}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00111}\mbox{\hyperlink{xhcireg_8h_ad1f896e47806ae455282e6c9a7e40d5b}{00111}} \textcolor{preprocessor}{\#define XHCI\_CRCR\_HI            0x1C    }\textcolor{comment}{/* XHCI command ring control */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00112}\mbox{\hyperlink{xhcireg_8h_aa88a74faa5093ac64bf204766f88e7bf}{00112}} \textcolor{preprocessor}{\#define XHCI\_DCBAAP\_LO          0x30    }\textcolor{comment}{/* XHCI dev context BA pointer */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00113}\mbox{\hyperlink{xhcireg_8h_adc344d0ccfd5cbb5ba518c885ad4aa3b}{00113}} \textcolor{preprocessor}{\#define XHCI\_DCBAAP\_HI          0x34    }\textcolor{comment}{/* XHCI dev context BA pointer */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00114}\mbox{\hyperlink{xhcireg_8h_a26e4e2cb2ebdb4a4359b84ecdec3faf3}{00114}} \textcolor{preprocessor}{\#define XHCI\_CONFIG             0x38}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00115}\mbox{\hyperlink{xhcireg_8h_ae2250eb786b51490c5609b5a34ab1c89}{00115}} \textcolor{preprocessor}{\#define XHCI\_CONFIG\_SLOTS\_MASK  0x000000FF      }\textcolor{comment}{/* RW -\/ number of device slots enabled */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00116}00116 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00117}00117 \textcolor{comment}{/* XHCI port status registers */}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00118}\mbox{\hyperlink{xhcireg_8h_a5fc3a868a2a89aeff110dfd0a3701462}{00118}} \textcolor{preprocessor}{\#define XHCI\_PORTSC(n)          (0x3F0 + (0x10 * (n)))  }\textcolor{comment}{/* XHCI port status */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00119}\mbox{\hyperlink{xhcireg_8h_af5f2331f90bf150e8dd3d55a7f0b8326}{00119}} \textcolor{preprocessor}{\#define XHCI\_PS\_CCS             0x00000001      }\textcolor{comment}{/* RO -\/ current connect status */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00120}\mbox{\hyperlink{xhcireg_8h_abcf46fc8d27d31c752337d88d238ecc5}{00120}} \textcolor{preprocessor}{\#define XHCI\_PS\_PED             0x00000002      }\textcolor{comment}{/* RW -\/ port enabled / disabled */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00121}\mbox{\hyperlink{xhcireg_8h_a8e994aee0193a17887e44944607b7b99}{00121}} \textcolor{preprocessor}{\#define XHCI\_PS\_OCA             0x00000008      }\textcolor{comment}{/* RO -\/ over current active */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00122}\mbox{\hyperlink{xhcireg_8h_ae71ce2c23b38dbe05c74020238f8647f}{00122}} \textcolor{preprocessor}{\#define XHCI\_PS\_PR              0x00000010      }\textcolor{comment}{/* RW -\/ port reset */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00123}\mbox{\hyperlink{xhcireg_8h_a70fd4582c7ebb2d536a133ad4b784fd0}{00123}} \textcolor{preprocessor}{\#define XHCI\_PS\_PLS\_GET(x)      (((x) >> 5) \& 0xF)      }\textcolor{comment}{/* RW -\/ port link state */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00124}\mbox{\hyperlink{xhcireg_8h_a864063c0c5ed3fc3d21ce3f09bb9c2c6}{00124}} \textcolor{preprocessor}{\#define XHCI\_PS\_PLS\_SET(x)      (((x) \& 0xF) << 5)      }\textcolor{comment}{/* RW -\/ port link state */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00125}\mbox{\hyperlink{xhcireg_8h_a6f8e3305290f7380ed49c8ffdc10de22}{00125}} \textcolor{preprocessor}{\#define XHCI\_PS\_PP              0x00000200      }\textcolor{comment}{/* RW -\/ port power */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00126}\mbox{\hyperlink{xhcireg_8h_a72a77f2aa51f668b5e1bcc3d8452058d}{00126}} \textcolor{preprocessor}{\#define XHCI\_PS\_SPEED\_GET(x)    (((x) >> 10) \& 0xF)     }\textcolor{comment}{/* RO -\/ port speed */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00127}\mbox{\hyperlink{xhcireg_8h_afccf4138d43ec09e12b1316eb6ceb0df}{00127}} \textcolor{preprocessor}{\#define XHCI\_PS\_PIC\_GET(x)      (((x) >> 14) \& 0x3)     }\textcolor{comment}{/* RW -\/ port indicator */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00128}\mbox{\hyperlink{xhcireg_8h_ab8d620c38a10a1e5d685459e9f297e5d}{00128}} \textcolor{preprocessor}{\#define XHCI\_PS\_PIC\_SET(x)      (((x) \& 0x3) << 14)     }\textcolor{comment}{/* RW -\/ port indicator */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00129}\mbox{\hyperlink{xhcireg_8h_a8b027493adc99dc41a73f72c349870e9}{00129}} \textcolor{preprocessor}{\#define XHCI\_PS\_LWS             0x00010000      }\textcolor{comment}{/* RW -\/ port link state write strobe */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00130}\mbox{\hyperlink{xhcireg_8h_a17a5d2da7a53516b1080d05b5de5815f}{00130}} \textcolor{preprocessor}{\#define XHCI\_PS\_CSC             0x00020000      }\textcolor{comment}{/* RW -\/ connect status change */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00131}\mbox{\hyperlink{xhcireg_8h_af7838a7c635af332a70ac27d8b807699}{00131}} \textcolor{preprocessor}{\#define XHCI\_PS\_PEC             0x00040000      }\textcolor{comment}{/* RW -\/ port enable/disable change */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00132}\mbox{\hyperlink{xhcireg_8h_ab89f476faf605c56e35c335c988cb55c}{00132}} \textcolor{preprocessor}{\#define XHCI\_PS\_WRC             0x00080000      }\textcolor{comment}{/* RW -\/ warm port reset change */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00133}\mbox{\hyperlink{xhcireg_8h_aef5d06e0627757c9dbebfcf78e9c0eed}{00133}} \textcolor{preprocessor}{\#define XHCI\_PS\_OCC             0x00100000      }\textcolor{comment}{/* RW -\/ over-\/current change */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00134}\mbox{\hyperlink{xhcireg_8h_a33181810d4b2c123bfe4d6dd8dd7907b}{00134}} \textcolor{preprocessor}{\#define XHCI\_PS\_PRC             0x00200000      }\textcolor{comment}{/* RW -\/ port reset change */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00135}\mbox{\hyperlink{xhcireg_8h_ac35f426018cce1012c24a61820eff33f}{00135}} \textcolor{preprocessor}{\#define XHCI\_PS\_PLC             0x00400000      }\textcolor{comment}{/* RW -\/ port link state change */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00136}\mbox{\hyperlink{xhcireg_8h_af6cc46aff4d9355dba9d4a6e9559be84}{00136}} \textcolor{preprocessor}{\#define XHCI\_PS\_CEC             0x00800000      }\textcolor{comment}{/* RW -\/ config error change */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00137}\mbox{\hyperlink{xhcireg_8h_abc71f973c65020d43debfe18398afc57}{00137}} \textcolor{preprocessor}{\#define XHCI\_PS\_CAS             0x01000000      }\textcolor{comment}{/* RO -\/ cold attach status */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00138}\mbox{\hyperlink{xhcireg_8h_a46f6c1277a43ca73d7e9790441d3f542}{00138}} \textcolor{preprocessor}{\#define XHCI\_PS\_WCE             0x02000000      }\textcolor{comment}{/* RW -\/ wake on connect enable */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00139}\mbox{\hyperlink{xhcireg_8h_acd4abae6c11a9bb9fa874459d740de2b}{00139}} \textcolor{preprocessor}{\#define XHCI\_PS\_WDE             0x04000000      }\textcolor{comment}{/* RW -\/ wake on disconnect enable */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00140}\mbox{\hyperlink{xhcireg_8h_ada1c93d0da817fcd79b0f39100931e4b}{00140}} \textcolor{preprocessor}{\#define XHCI\_PS\_WOE             0x08000000      }\textcolor{comment}{/* RW -\/ wake on over-\/current enable */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00141}\mbox{\hyperlink{xhcireg_8h_ad3e1e83f73638cc6e37b4cb583c00c16}{00141}} \textcolor{preprocessor}{\#define XHCI\_PS\_DR              0x40000000      }\textcolor{comment}{/* RO -\/ device removable */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00142}\mbox{\hyperlink{xhcireg_8h_a64f300f02a831268c4317515d0be17bc}{00142}} \textcolor{preprocessor}{\#define XHCI\_PS\_WPR             0x80000000U     }\textcolor{comment}{/* RW -\/ warm port reset */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00143}\mbox{\hyperlink{xhcireg_8h_a570362e82fd8ed1e282fec6bc39b8141}{00143}} \textcolor{preprocessor}{\#define XHCI\_PS\_CLEAR           0x80FF01FFU     }\textcolor{comment}{/* command bits */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00144}00144 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00145}\mbox{\hyperlink{xhcireg_8h_a8ea3a8fe30e63f4ba4134a40f2ec2f29}{00145}} \textcolor{preprocessor}{\#define XHCI\_PORTPMSC(n)        (0x3F4 + (0x10 * (n)))  }\textcolor{comment}{/* XHCI status and control */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00146}\mbox{\hyperlink{xhcireg_8h_a4725f4fa55ab4e8dfb571ce2595353c8}{00146}} \textcolor{preprocessor}{\#define XHCI\_PM3\_U1TO\_GET(x)    (((x) >> 0) \& 0xFF)     }\textcolor{comment}{/* RW -\/ U1 timeout */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00147}\mbox{\hyperlink{xhcireg_8h_a0c553b01ae022e25ffe86ffb789971ab}{00147}} \textcolor{preprocessor}{\#define XHCI\_PM3\_U1TO\_SET(x)    (((x) \& 0xFF) << 0)     }\textcolor{comment}{/* RW -\/ U1 timeout */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00148}\mbox{\hyperlink{xhcireg_8h_a5a7f633c3f822b1c054273112d6df095}{00148}} \textcolor{preprocessor}{\#define XHCI\_PM3\_U2TO\_GET(x)    (((x) >> 8) \& 0xFF)     }\textcolor{comment}{/* RW -\/ U2 timeout */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00149}\mbox{\hyperlink{xhcireg_8h_a56b97bf2761f8c8bf92e26ae3f7b5e24}{00149}} \textcolor{preprocessor}{\#define XHCI\_PM3\_U2TO\_SET(x)    (((x) \& 0xFF) << 8)     }\textcolor{comment}{/* RW -\/ U2 timeout */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00150}\mbox{\hyperlink{xhcireg_8h_a6f71c9d87ec4109bb201498bbedf86cf}{00150}} \textcolor{preprocessor}{\#define XHCI\_PM3\_FLA            0x00010000      }\textcolor{comment}{/* RW -\/ Force Link PM Accept */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00151}\mbox{\hyperlink{xhcireg_8h_a1eeeda6f852820d046ca96eaa8283e76}{00151}} \textcolor{preprocessor}{\#define XHCI\_PM2\_L1S\_GET(x)     (((x) >> 0) \& 0x7)      }\textcolor{comment}{/* RO -\/ L1 status */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00152}\mbox{\hyperlink{xhcireg_8h_ab8f834d6f79e95d792d725a85562c054}{00152}} \textcolor{preprocessor}{\#define XHCI\_PM2\_RWE            0x00000008              }\textcolor{comment}{/* RW -\/ remote wakup enable */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00153}\mbox{\hyperlink{xhcireg_8h_abc2778fd8c2294754b28e2dc9481bf2a}{00153}} \textcolor{preprocessor}{\#define XHCI\_PM2\_HIRD\_GET(x)    (((x) >> 4) \& 0xF)      }\textcolor{comment}{/* RW -\/ host initiated resume duration */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00154}\mbox{\hyperlink{xhcireg_8h_a95a129dfac7e11668f557b43807613a6}{00154}} \textcolor{preprocessor}{\#define XHCI\_PM2\_HIRD\_SET(x)    (((x) \& 0xF) << 4)      }\textcolor{comment}{/* RW -\/ host initiated resume duration */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00155}\mbox{\hyperlink{xhcireg_8h_a5c90b303cbc6dfa0ec75bc3e4f9fbd5e}{00155}} \textcolor{preprocessor}{\#define XHCI\_PM2\_L1SLOT\_GET(x)  (((x) >> 8) \& 0xFF)     }\textcolor{comment}{/* RW -\/ L1 device slot */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00156}\mbox{\hyperlink{xhcireg_8h_a2a8150368770830b5970d77d1798f854}{00156}} \textcolor{preprocessor}{\#define XHCI\_PM2\_L1SLOT\_SET(x)  (((x) \& 0xFF) << 8)     }\textcolor{comment}{/* RW -\/ L1 device slot */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00157}\mbox{\hyperlink{xhcireg_8h_a96361a490429ac3fce27108822ef2629}{00157}} \textcolor{preprocessor}{\#define XHCI\_PM2\_HLE            0x00010000              }\textcolor{comment}{/* RW -\/ hardware LPM enable */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00158}\mbox{\hyperlink{xhcireg_8h_a702c054f44b111ebfc25a837fa50e1de}{00158}} \textcolor{preprocessor}{\#define XHCI\_PORTLI(n)          (0x3F8 + (0x10 * (n)))  }\textcolor{comment}{/* XHCI port link info */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00159}\mbox{\hyperlink{xhcireg_8h_ae19bada841c79ac1b6d809ee2920a68d}{00159}} \textcolor{preprocessor}{\#define XHCI\_PLI3\_ERR\_GET(x)    (((x) >> 0) \& 0xFFFF)   }\textcolor{comment}{/* RO -\/ port link errors */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00160}\mbox{\hyperlink{xhcireg_8h_a11eb20eca112ae175f910f1aba9e389a}{00160}} \textcolor{preprocessor}{\#define XHCI\_PORTRSV(n)         (0x3FC + (0x10 * (n)))  }\textcolor{comment}{/* XHCI port reserved */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00161}00161 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00162}00162 \textcolor{comment}{/* XHCI runtime registers.  Offset given by XHCI\_CAPLENGTH + XHCI\_RTSOFF registers */}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00163}\mbox{\hyperlink{xhcireg_8h_aeda9ef077a3022d8d1c5ade54b32c960}{00163}} \textcolor{preprocessor}{\#define XHCI\_MFINDEX            0x0000          }\textcolor{comment}{/* RO -\/ microframe index */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00164}\mbox{\hyperlink{xhcireg_8h_a6e570459d450bac6c40eb6842b64bc87}{00164}} \textcolor{preprocessor}{\#define XHCI\_MFINDEX\_GET(x)     ((x) \& 0x3FFF)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00165}\mbox{\hyperlink{xhcireg_8h_a6d4c1a2eb813b6c60026458dc7034526}{00165}} \textcolor{preprocessor}{\#define XHCI\_IMAN(n)            (0x0020 + (0x20 * (n))) }\textcolor{comment}{/* XHCI interrupt management */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00166}\mbox{\hyperlink{xhcireg_8h_a0d050d13db1059a45773ed0769ae117d}{00166}} \textcolor{preprocessor}{\#define XHCI\_IMAN\_INTR\_PEND     0x00000001      }\textcolor{comment}{/* RW -\/ interrupt pending */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00167}\mbox{\hyperlink{xhcireg_8h_a57b850d101e7404864e999caf13512b1}{00167}} \textcolor{preprocessor}{\#define XHCI\_IMAN\_INTR\_ENA      0x00000002      }\textcolor{comment}{/* RW -\/ interrupt enable */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00168}\mbox{\hyperlink{xhcireg_8h_a1dcc5e4d6cd538d2466317e8bf6cbb91}{00168}} \textcolor{preprocessor}{\#define XHCI\_IMOD(n)            (0x0024 + (0x20 * (n))) }\textcolor{comment}{/* XHCI interrupt moderation */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00169}\mbox{\hyperlink{xhcireg_8h_a1d8506b546e7c6c51168265422c0c667}{00169}} \textcolor{preprocessor}{\#define XHCI\_IMOD\_IVAL\_GET(x)   (((x) >> 0) \& 0xFFFF)   }\textcolor{comment}{/* 250ns unit */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00170}\mbox{\hyperlink{xhcireg_8h_a12b9a2b27ce13a6c66ee276bdf12f9ab}{00170}} \textcolor{preprocessor}{\#define XHCI\_IMOD\_IVAL\_SET(x)   (((x) \& 0xFFFF) << 0)   }\textcolor{comment}{/* 250ns unit */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00171}\mbox{\hyperlink{xhcireg_8h_abcf67db0358b0f983adea61f47337b1c}{00171}} \textcolor{preprocessor}{\#define XHCI\_IMOD\_ICNT\_GET(x)   (((x) >> 16) \& 0xFFFF)  }\textcolor{comment}{/* 250ns unit */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00172}\mbox{\hyperlink{xhcireg_8h_ac85a23a75fab092e8257680fc14d6f8b}{00172}} \textcolor{preprocessor}{\#define XHCI\_IMOD\_ICNT\_SET(x)   (((x) \& 0xFFFF) << 16)  }\textcolor{comment}{/* 250ns unit */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00173}\mbox{\hyperlink{xhcireg_8h_a1f640a535167c7709ee66dc690363052}{00173}} \textcolor{preprocessor}{\#define XHCI\_IMOD\_DEFAULT       0x000001F4U     }\textcolor{comment}{/* 8000 IRQs/second */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00174}\mbox{\hyperlink{xhcireg_8h_ad345af222cc4042978cbeba3422a57d1}{00174}} \textcolor{preprocessor}{\#define XHCI\_IMOD\_DEFAULT\_LP    0x000003F8U     }\textcolor{comment}{/* 4000 IRQs/second -\/ LynxPoint */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00175}\mbox{\hyperlink{xhcireg_8h_a3ac467a9f8ff1f4fc232e7719fc80a34}{00175}} \textcolor{preprocessor}{\#define XHCI\_ERSTSZ(n)          (0x0028 + (0x20 * (n))) }\textcolor{comment}{/* XHCI event ring segment table size */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00176}\mbox{\hyperlink{xhcireg_8h_aeed796a55ee6d314ecdf05f94a3ebfba}{00176}} \textcolor{preprocessor}{\#define XHCI\_ERSTS\_GET(x)       ((x) \& 0xFFFF)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00177}\mbox{\hyperlink{xhcireg_8h_a9d8826d9da1bb47bc277beb470722170}{00177}} \textcolor{preprocessor}{\#define XHCI\_ERSTS\_SET(x)       ((x) \& 0xFFFF)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00178}\mbox{\hyperlink{xhcireg_8h_ad184281c7ae02c8073c8e429284e748c}{00178}} \textcolor{preprocessor}{\#define XHCI\_ERSTBA\_LO(n)       (0x0030 + (0x20 * (n))) }\textcolor{comment}{/* XHCI event ring segment table BA */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00179}\mbox{\hyperlink{xhcireg_8h_ae2a417902887d2f467b4b99f3ac4d6a6}{00179}} \textcolor{preprocessor}{\#define XHCI\_ERSTBA\_HI(n)       (0x0034 + (0x20 * (n))) }\textcolor{comment}{/* XHCI event ring segment table BA */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00180}\mbox{\hyperlink{xhcireg_8h_a9d29850de9597ee9387b5827e509066f}{00180}} \textcolor{preprocessor}{\#define XHCI\_ERDP\_LO(n) (0x0038 + (0x20 * (n))) }\textcolor{comment}{/* XHCI event ring dequeue pointer */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00181}\mbox{\hyperlink{xhcireg_8h_acde44486a530476900c16576579f2903}{00181}} \textcolor{preprocessor}{\#define XHCI\_ERDP\_LO\_SINDEX(x)  ((x) \& 0x7)     }\textcolor{comment}{/* RO -\/ dequeue segment index */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00182}\mbox{\hyperlink{xhcireg_8h_ad266405575c5ce7ebab6d63b49605444}{00182}} \textcolor{preprocessor}{\#define XHCI\_ERDP\_LO\_BUSY       0x00000008      }\textcolor{comment}{/* RW -\/ event handler busy */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00183}\mbox{\hyperlink{xhcireg_8h_ab89bf9fe3d9247a7ea029000a1bfa95e}{00183}} \textcolor{preprocessor}{\#define XHCI\_ERDP\_HI(n) (0x003C + (0x20 * (n))) }\textcolor{comment}{/* XHCI event ring dequeue pointer */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00184}00184 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00185}00185 \textcolor{comment}{/* XHCI doorbell registers. Offset given by XHCI\_CAPLENGTH + XHCI\_DBOFF registers */}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00186}\mbox{\hyperlink{xhcireg_8h_a6b426074e34edc0a6aef5a1d32ac445b}{00186}} \textcolor{preprocessor}{\#define XHCI\_DOORBELL(n)        (0x0000 + (4 * (n)))}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00187}\mbox{\hyperlink{xhcireg_8h_a357547bf476360ad4bbb3fb86e8fa7a9}{00187}} \textcolor{preprocessor}{\#define XHCI\_DB\_TARGET\_GET(x)   ((x) \& 0xFF)            }\textcolor{comment}{/* RW -\/ doorbell target */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00188}\mbox{\hyperlink{xhcireg_8h_adf4151ebfbae68d017002b3edd4ef0cd}{00188}} \textcolor{preprocessor}{\#define XHCI\_DB\_TARGET\_SET(x)   ((x) \& 0xFF)            }\textcolor{comment}{/* RW -\/ doorbell target */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00189}\mbox{\hyperlink{xhcireg_8h_aab99a855901c05ef54a23545685725c7}{00189}} \textcolor{preprocessor}{\#define XHCI\_DB\_SID\_GET(x)      (((x) >> 16) \& 0xFFFF)  }\textcolor{comment}{/* RW -\/ doorbell stream ID */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00190}\mbox{\hyperlink{xhcireg_8h_acb878531e6b4ccaa0cb904370d8d2ab5}{00190}} \textcolor{preprocessor}{\#define XHCI\_DB\_SID\_SET(x)      (((x) \& 0xFFFF) << 16)  }\textcolor{comment}{/* RW -\/ doorbell stream ID */}\textcolor{preprocessor}{}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00191}00191 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00192}00192 \textcolor{comment}{/* XHCI legacy support */}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00193}\mbox{\hyperlink{xhcireg_8h_aecd60540fa159516a40b9c6c616405c4}{00193}} \textcolor{preprocessor}{\#define XHCI\_XECP\_ID(x)         ((x) \& 0xFF)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00194}\mbox{\hyperlink{xhcireg_8h_a60b5e53d5e9bb0cc35c5fc788891063c}{00194}} \textcolor{preprocessor}{\#define XHCI\_XECP\_NEXT(x)       (((x) >> 8) \& 0xFF)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00195}\mbox{\hyperlink{xhcireg_8h_aeacf67eba124c2d66aa194e1c38a9b26}{00195}} \textcolor{preprocessor}{\#define XHCI\_XECP\_BIOS\_SEM      0x0002}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00196}\mbox{\hyperlink{xhcireg_8h_a39a71133a2fdf8ec0ff5fef9ffeb360a}{00196}} \textcolor{preprocessor}{\#define XHCI\_XECP\_OS\_SEM        0x0003}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00197}00197 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00198}00198 \textcolor{comment}{/* XHCI capability ID's */}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00199}\mbox{\hyperlink{xhcireg_8h_ae03bc3ff9fd8e2aa3f1afa5d4b07d290}{00199}} \textcolor{preprocessor}{\#define XHCI\_ID\_USB\_LEGACY      0x0001}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00200}\mbox{\hyperlink{xhcireg_8h_a710efb082e4b66c2b7a92608137ffc11}{00200}} \textcolor{preprocessor}{\#define XHCI\_ID\_PROTOCOLS       0x0002}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00201}\mbox{\hyperlink{xhcireg_8h_afc253081fa23935809612087ccb1269f}{00201}} \textcolor{preprocessor}{\#define XHCI\_ID\_POWER\_MGMT      0x0003}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00202}\mbox{\hyperlink{xhcireg_8h_aebfd0de964d848ffa8e2f909c411dea3}{00202}} \textcolor{preprocessor}{\#define XHCI\_ID\_VIRTUALIZATION  0x0004}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00203}\mbox{\hyperlink{xhcireg_8h_a437d70d8f6d7c374f0d905bcd1f7f792}{00203}} \textcolor{preprocessor}{\#define XHCI\_ID\_MSG\_IRQ         0x0005}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00204}\mbox{\hyperlink{xhcireg_8h_ad9bedeffbc71129b61de855514b68e81}{00204}} \textcolor{preprocessor}{\#define XHCI\_ID\_USB\_LOCAL\_MEM   0x0006}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00205}00205 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00206}00206 \textcolor{comment}{/* XHCI register R/W wrappers */}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00207}\mbox{\hyperlink{xhcireg_8h_a0d25503aa95ca95bac42c2d153744987}{00207}} \textcolor{preprocessor}{\#define XREAD1(sc, what, a) \(\backslash\)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00208}00208 \textcolor{preprocessor}{        bus\_space\_read\_1((sc)-\/>sc\_io\_tag, (sc)-\/>sc\_io\_hdl, \(\backslash\)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00209}00209 \textcolor{preprocessor}{                (a) + (sc)-\/>sc\_\#\#what\#\#\_off)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00210}\mbox{\hyperlink{xhcireg_8h_a44e65597cfebc9361f35d65f66a92d32}{00210}} \textcolor{preprocessor}{\#define XREAD2(sc, what, a) \(\backslash\)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00211}00211 \textcolor{preprocessor}{        bus\_space\_read\_2((sc)-\/>sc\_io\_tag, (sc)-\/>sc\_io\_hdl, \(\backslash\)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00212}00212 \textcolor{preprocessor}{                (a) + (sc)-\/>sc\_\#\#what\#\#\_off)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00213}\mbox{\hyperlink{xhcireg_8h_ab6a4f3983e8f6624ad909c5ed8df4b70}{00213}} \textcolor{preprocessor}{\#define XREAD4(sc, what, a) \(\backslash\)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00214}00214 \textcolor{preprocessor}{        bus\_space\_read\_4((sc)-\/>sc\_io\_tag, (sc)-\/>sc\_io\_hdl, \(\backslash\)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00215}00215 \textcolor{preprocessor}{                (a) + (sc)-\/>sc\_\#\#what\#\#\_off)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00216}\mbox{\hyperlink{xhcireg_8h_ac915f7085c4a7edfee419941d35533f1}{00216}} \textcolor{preprocessor}{\#define XWRITE1(sc, what, a, x) \(\backslash\)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00217}00217 \textcolor{preprocessor}{        bus\_space\_write\_1((sc)-\/>sc\_io\_tag, (sc)-\/>sc\_io\_hdl, \(\backslash\)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00218}00218 \textcolor{preprocessor}{                (a) + (sc)-\/>sc\_\#\#what\#\#\_off, (x))}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00219}\mbox{\hyperlink{xhcireg_8h_a713942ec725874662547392bdc909fab}{00219}} \textcolor{preprocessor}{\#define XWRITE2(sc, what, a, x) \(\backslash\)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00220}00220 \textcolor{preprocessor}{        bus\_space\_write\_2((sc)-\/>sc\_io\_tag, (sc)-\/>sc\_io\_hdl, \(\backslash\)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00221}00221 \textcolor{preprocessor}{                (a) + (sc)-\/>sc\_\#\#what\#\#\_off, (x))}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00222}\mbox{\hyperlink{xhcireg_8h_a20ca65605ae6b2d03c8af13fd1014bad}{00222}} \textcolor{preprocessor}{\#define XWRITE4(sc, what, a, x) \(\backslash\)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00223}00223 \textcolor{preprocessor}{        bus\_space\_write\_4((sc)-\/>sc\_io\_tag, (sc)-\/>sc\_io\_hdl, \(\backslash\)}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00224}00224 \textcolor{preprocessor}{                (a) + (sc)-\/>sc\_\#\#what\#\#\_off, (x))}}
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00225}00225 }
\DoxyCodeLine{\Hypertarget{xhcireg_8h_source_l00226}00226 \textcolor{preprocessor}{\#endif  }\textcolor{comment}{/* \_XHCIREG\_H\_ */}\textcolor{preprocessor}{}}

\end{DoxyCode}
