\hypertarget{structmlx5__fpga__trans__device__state}{}\doxysection{mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+state Struct Reference}
\label{structmlx5__fpga__trans__device__state}\index{mlx5\_fpga\_trans\_device\_state@{mlx5\_fpga\_trans\_device\_state}}


Collaboration diagram for mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+state\+:
\nopagebreak
\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=350pt]{d2/d72/structmlx5__fpga__trans__device__state__coll__graph}
\end{center}
\end{figure}
\doxysubsection*{Data Fields}
\begin{DoxyCompactItemize}
\item 
spinlock\+\_\+t \mbox{\hyperlink{structmlx5__fpga__trans__device__state_a1a2534843e15b09363adeb886e569a9f}{lock}}
\item 
struct list\+\_\+head \mbox{\hyperlink{structmlx5__fpga__trans__device__state_a3b734cba6886822291e2bdec83e3bd87}{free\+\_\+queue}}
\item 
struct \mbox{\hyperlink{structmlx5__fpga__trans__priv}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv}} \mbox{\hyperlink{structmlx5__fpga__trans__device__state_a6717c88236657214241c7da9b8a2a61b}{transactions}} \mbox{[}\mbox{\hyperlink{trans_8h_a1afba54e768e37759c00c92a83ee1789}{MLX5\+\_\+\+FPGA\+\_\+\+TID\+\_\+\+COUNT}}\mbox{]}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}


Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00055}{55}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



\doxysubsection{Field Documentation}
\mbox{\Hypertarget{structmlx5__fpga__trans__device__state_a3b734cba6886822291e2bdec83e3bd87}\label{structmlx5__fpga__trans__device__state_a3b734cba6886822291e2bdec83e3bd87}} 
\index{mlx5\_fpga\_trans\_device\_state@{mlx5\_fpga\_trans\_device\_state}!free\_queue@{free\_queue}}
\index{free\_queue@{free\_queue}!mlx5\_fpga\_trans\_device\_state@{mlx5\_fpga\_trans\_device\_state}}
\doxysubsubsection{\texorpdfstring{free\_queue}{free\_queue}}
{\footnotesize\ttfamily struct list\+\_\+head mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+state\+::free\+\_\+queue}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00057}{57}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.

\mbox{\Hypertarget{structmlx5__fpga__trans__device__state_a1a2534843e15b09363adeb886e569a9f}\label{structmlx5__fpga__trans__device__state_a1a2534843e15b09363adeb886e569a9f}} 
\index{mlx5\_fpga\_trans\_device\_state@{mlx5\_fpga\_trans\_device\_state}!lock@{lock}}
\index{lock@{lock}!mlx5\_fpga\_trans\_device\_state@{mlx5\_fpga\_trans\_device\_state}}
\doxysubsubsection{\texorpdfstring{lock}{lock}}
{\footnotesize\ttfamily spinlock\+\_\+t mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+state\+::lock}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00056}{56}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.

\mbox{\Hypertarget{structmlx5__fpga__trans__device__state_a6717c88236657214241c7da9b8a2a61b}\label{structmlx5__fpga__trans__device__state_a6717c88236657214241c7da9b8a2a61b}} 
\index{mlx5\_fpga\_trans\_device\_state@{mlx5\_fpga\_trans\_device\_state}!transactions@{transactions}}
\index{transactions@{transactions}!mlx5\_fpga\_trans\_device\_state@{mlx5\_fpga\_trans\_device\_state}}
\doxysubsubsection{\texorpdfstring{transactions}{transactions}}
{\footnotesize\ttfamily struct \mbox{\hyperlink{structmlx5__fpga__trans__priv}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv}} mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+state\+::transactions\mbox{[}\mbox{\hyperlink{trans_8h_a1afba54e768e37759c00c92a83ee1789}{MLX5\+\_\+\+FPGA\+\_\+\+TID\+\_\+\+COUNT}}\mbox{]}}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00058}{58}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
dev/mlx5/mlx5\+\_\+fpga/\mbox{\hyperlink{mlx5fpga__trans_8c}{mlx5fpga\+\_\+trans.\+c}}\end{DoxyCompactItemize}
