\hypertarget{mlx5fpga__trans_8c}{}\doxysection{dev/mlx5/mlx5\+\_\+fpga/mlx5fpga\+\_\+trans.c File Reference}
\label{mlx5fpga__trans_8c}\index{dev/mlx5/mlx5\_fpga/mlx5fpga\_trans.c@{dev/mlx5/mlx5\_fpga/mlx5fpga\_trans.c}}
{\ttfamily \#include $<$dev/mlx5/mlx5\+\_\+fpga/trans.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/mlx5\+\_\+fpga/conn.\+h$>$}\newline
Include dependency graph for mlx5fpga\+\_\+trans.\+c\+:
\nopagebreak
\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=350pt]{df/dec/mlx5fpga__trans_8c__incl}
\end{center}
\end{figure}
\doxysubsection*{Data Structures}
\begin{DoxyCompactItemize}
\item 
struct \mbox{\hyperlink{structmlx5__fpga__trans__priv}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv}}
\item 
struct \mbox{\hyperlink{structmlx5__fpga__trans__device__state}{mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+state}}
\end{DoxyCompactItemize}
\doxysubsection*{Enumerations}
\begin{DoxyCompactItemize}
\item 
enum \mbox{\hyperlink{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8}{mlx5\+\_\+fpga\+\_\+transaction\+\_\+state}} \{ \mbox{\hyperlink{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8a04638289ddc110fffcecee59a1715387}{TRANS\+\_\+\+STATE\+\_\+\+NONE}}
, \mbox{\hyperlink{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8a39edde2049f2cf434c3342a92fe119bd}{TRANS\+\_\+\+STATE\+\_\+\+SEND}}
, \mbox{\hyperlink{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8a82654c0aafdbb3e4ea1da939cccb9374}{TRANS\+\_\+\+STATE\+\_\+\+WAIT}}
, \mbox{\hyperlink{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8a62d7917e9ba7f9eec4dd0347e6c2cb8b}{TRANS\+\_\+\+STATE\+\_\+\+COMPLETE}}
 \}
\end{DoxyCompactItemize}
\doxysubsection*{Functions}
\begin{DoxyCompactItemize}
\item 
static struct \mbox{\hyperlink{structmlx5__fpga__trans__priv}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv}} $\ast$ \mbox{\hyperlink{mlx5fpga__trans_8c_acca9065dee8a04e8a25c84959dd24f43}{find\+\_\+tid}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev, u8 tid)
\item 
static struct \mbox{\hyperlink{structmlx5__fpga__trans__priv}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv}} $\ast$ \mbox{\hyperlink{mlx5fpga__trans_8c_a046d441270edd1bb944834bd0e883121}{alloc\+\_\+tid}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev)
\item 
static void \mbox{\hyperlink{mlx5fpga__trans_8c_a836875bfc3344e74edeb4b0f2c436c93}{free\+\_\+tid}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev, struct \mbox{\hyperlink{structmlx5__fpga__trans__priv}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv}} $\ast$trans\+\_\+priv)
\item 
static void \mbox{\hyperlink{mlx5fpga__trans_8c_a05338a5b5c6f538ecb516f3aefc01347}{trans\+\_\+complete}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev, struct \mbox{\hyperlink{structmlx5__fpga__trans__priv}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv}} $\ast$trans\+\_\+priv, u8 status)
\item 
static void \mbox{\hyperlink{mlx5fpga__trans_8c_a924834d0e9343004ccd461ea0467d085}{trans\+\_\+send\+\_\+complete}} (struct \mbox{\hyperlink{structmlx5__fpga__conn}{mlx5\+\_\+fpga\+\_\+conn}} $\ast$conn, struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev, struct \mbox{\hyperlink{structmlx5__fpga__dma__buf}{mlx5\+\_\+fpga\+\_\+dma\+\_\+buf}} $\ast$buf, u8 status)
\item 
static int \mbox{\hyperlink{mlx5fpga__trans_8c_a245675d5f19bf8580f68d6cdc7e8ab67}{trans\+\_\+validate}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev, u64 addr, size\+\_\+t size)
\item 
int \mbox{\hyperlink{mlx5fpga__trans_8c_a5ab19e75b9ee247a0e1edf9878a61aad}{mlx5\+\_\+fpga\+\_\+trans\+\_\+exec}} (const struct \mbox{\hyperlink{structmlx5__fpga__transaction}{mlx5\+\_\+fpga\+\_\+transaction}} $\ast$trans)
\item 
void \mbox{\hyperlink{mlx5fpga__trans_8c_a51ec92711d42a593954be18f06275d3a}{mlx5\+\_\+fpga\+\_\+trans\+\_\+recv}} (void $\ast$cb\+\_\+arg, struct \mbox{\hyperlink{structmlx5__fpga__dma__buf}{mlx5\+\_\+fpga\+\_\+dma\+\_\+buf}} $\ast$buf)
\item 
int \mbox{\hyperlink{mlx5fpga__trans_8c_ae13a014b26163a451655dc60d864aeb4}{mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+init}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev)
\item 
void \mbox{\hyperlink{mlx5fpga__trans_8c_ad684faeee8b96af775d6082d8ed779fc}{mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+cleanup}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev)
\end{DoxyCompactItemize}


\doxysubsection{Enumeration Type Documentation}
\mbox{\Hypertarget{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8}\label{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8}} 
\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!mlx5\_fpga\_transaction\_state@{mlx5\_fpga\_transaction\_state}}
\index{mlx5\_fpga\_transaction\_state@{mlx5\_fpga\_transaction\_state}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_transaction\_state}{mlx5\_fpga\_transaction\_state}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8}{mlx5\+\_\+fpga\+\_\+transaction\+\_\+state}}}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{TRANS\_STATE\_NONE@{TRANS\_STATE\_NONE}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!TRANS\_STATE\_NONE@{TRANS\_STATE\_NONE}}}\mbox{\Hypertarget{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8a04638289ddc110fffcecee59a1715387}\label{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8a04638289ddc110fffcecee59a1715387}} 
TRANS\+\_\+\+STATE\+\_\+\+NONE&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{TRANS\_STATE\_SEND@{TRANS\_STATE\_SEND}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!TRANS\_STATE\_SEND@{TRANS\_STATE\_SEND}}}\mbox{\Hypertarget{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8a39edde2049f2cf434c3342a92fe119bd}\label{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8a39edde2049f2cf434c3342a92fe119bd}} 
TRANS\+\_\+\+STATE\+\_\+\+SEND&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{TRANS\_STATE\_WAIT@{TRANS\_STATE\_WAIT}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!TRANS\_STATE\_WAIT@{TRANS\_STATE\_WAIT}}}\mbox{\Hypertarget{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8a82654c0aafdbb3e4ea1da939cccb9374}\label{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8a82654c0aafdbb3e4ea1da939cccb9374}} 
TRANS\+\_\+\+STATE\+\_\+\+WAIT&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{TRANS\_STATE\_COMPLETE@{TRANS\_STATE\_COMPLETE}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!TRANS\_STATE\_COMPLETE@{TRANS\_STATE\_COMPLETE}}}\mbox{\Hypertarget{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8a62d7917e9ba7f9eec4dd0347e6c2cb8b}\label{mlx5fpga__trans_8c_a54102e3e363218ae3a3382469d00f7b8a62d7917e9ba7f9eec4dd0347e6c2cb8b}} 
TRANS\+\_\+\+STATE\+\_\+\+COMPLETE&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00038}{38}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



\doxysubsection{Function Documentation}
\mbox{\Hypertarget{mlx5fpga__trans_8c_a046d441270edd1bb944834bd0e883121}\label{mlx5fpga__trans_8c_a046d441270edd1bb944834bd0e883121}} 
\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!alloc\_tid@{alloc\_tid}}
\index{alloc\_tid@{alloc\_tid}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}
\doxysubsubsection{\texorpdfstring{alloc\_tid()}{alloc\_tid()}}
{\footnotesize\ttfamily static struct \mbox{\hyperlink{structmlx5__fpga__trans__priv}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv}} $\ast$ alloc\+\_\+tid (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00071}{71}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



References \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00052}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::list\+\_\+item}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00048}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::state}}, and \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00039}{TRANS\+\_\+\+STATE\+\_\+\+NONE}}.



Referenced by \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00184}{mlx5\+\_\+fpga\+\_\+trans\+\_\+exec()}}.

Here is the caller graph for this function\+:
\nopagebreak
\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=350pt]{dd/df4/mlx5fpga__trans_8c_a046d441270edd1bb944834bd0e883121_icgraph}
\end{center}
\end{figure}
\mbox{\Hypertarget{mlx5fpga__trans_8c_acca9065dee8a04e8a25c84959dd24f43}\label{mlx5fpga__trans_8c_acca9065dee8a04e8a25c84959dd24f43}} 
\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!find\_tid@{find\_tid}}
\index{find\_tid@{find\_tid}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}
\doxysubsubsection{\texorpdfstring{find\_tid()}{find\_tid()}}
{\footnotesize\ttfamily static struct \mbox{\hyperlink{structmlx5__fpga__trans__priv}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv}} $\ast$ find\+\_\+tid (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev,  }\item[{u8}]{tid }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00061}{61}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



References \mbox{\hyperlink{trans_8h_source_l00044}{MLX5\+\_\+\+FPGA\+\_\+\+TID\+\_\+\+COUNT}}, and \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00047}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::tid}}.



Referenced by \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00245}{mlx5\+\_\+fpga\+\_\+trans\+\_\+recv()}}.

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\begin{center}
\leavevmode
\includegraphics[width=350pt]{dd/df4/mlx5fpga__trans_8c_acca9065dee8a04e8a25c84959dd24f43_icgraph}
\end{center}
\end{figure}
\mbox{\Hypertarget{mlx5fpga__trans_8c_a836875bfc3344e74edeb4b0f2c436c93}\label{mlx5fpga__trans_8c_a836875bfc3344e74edeb4b0f2c436c93}} 
\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!free\_tid@{free\_tid}}
\index{free\_tid@{free\_tid}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}
\doxysubsubsection{\texorpdfstring{free\_tid()}{free\_tid()}}
{\footnotesize\ttfamily static void free\+\_\+tid (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev,  }\item[{struct \mbox{\hyperlink{structmlx5__fpga__trans__priv}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv}} $\ast$}]{trans\+\_\+priv }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00094}{94}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



References \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00052}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::list\+\_\+item}}.



Referenced by \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00184}{mlx5\+\_\+fpga\+\_\+trans\+\_\+exec()}}, and \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00104}{trans\+\_\+complete()}}.

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\begin{center}
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\includegraphics[width=350pt]{dd/df4/mlx5fpga__trans_8c_a836875bfc3344e74edeb4b0f2c436c93_icgraph}
\end{center}
\end{figure}
\mbox{\Hypertarget{mlx5fpga__trans_8c_ad684faeee8b96af775d6082d8ed779fc}\label{mlx5fpga__trans_8c_ad684faeee8b96af775d6082d8ed779fc}} 
\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!mlx5\_fpga\_trans\_device\_cleanup@{mlx5\_fpga\_trans\_device\_cleanup}}
\index{mlx5\_fpga\_trans\_device\_cleanup@{mlx5\_fpga\_trans\_device\_cleanup}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_trans\_device\_cleanup()}{mlx5\_fpga\_trans\_device\_cleanup()}}
{\footnotesize\ttfamily void mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+cleanup (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00332}{332}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00206}{mlx5\+\_\+fpga\+\_\+device\+\_\+start()}}, and \mbox{\hyperlink{mlx5fpga__core_8c_source_l00361}{mlx5\+\_\+fpga\+\_\+device\+\_\+stop()}}.

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\leavevmode
\includegraphics[width=350pt]{dd/df4/mlx5fpga__trans_8c_ad684faeee8b96af775d6082d8ed779fc_icgraph}
\end{center}
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\mbox{\Hypertarget{mlx5fpga__trans_8c_ae13a014b26163a451655dc60d864aeb4}\label{mlx5fpga__trans_8c_ae13a014b26163a451655dc60d864aeb4}} 
\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!mlx5\_fpga\_trans\_device\_init@{mlx5\_fpga\_trans\_device\_init}}
\index{mlx5\_fpga\_trans\_device\_init@{mlx5\_fpga\_trans\_device\_init}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_trans\_device\_init()}{mlx5\_fpga\_trans\_device\_init()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+init (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00308}{308}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



References \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00047}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::tid}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00206}{mlx5\+\_\+fpga\+\_\+device\+\_\+start()}}.

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\includegraphics[width=350pt]{dd/df4/mlx5fpga__trans_8c_ae13a014b26163a451655dc60d864aeb4_icgraph}
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\mbox{\Hypertarget{mlx5fpga__trans_8c_a5ab19e75b9ee247a0e1edf9878a61aad}\label{mlx5fpga__trans_8c_a5ab19e75b9ee247a0e1edf9878a61aad}} 
\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!mlx5\_fpga\_trans\_exec@{mlx5\_fpga\_trans\_exec}}
\index{mlx5\_fpga\_trans\_exec@{mlx5\_fpga\_trans\_exec}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_trans\_exec()}{mlx5\_fpga\_trans\_exec()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+trans\+\_\+exec (\begin{DoxyParamCaption}\item[{const struct \mbox{\hyperlink{structmlx5__fpga__transaction}{mlx5\+\_\+fpga\+\_\+transaction}} $\ast$}]{trans }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00184}{184}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



References \mbox{\hyperlink{trans_8h_source_l00055}{mlx5\+\_\+fpga\+\_\+transaction\+::addr}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00071}{alloc\+\_\+tid()}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00051}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::buf}}, \mbox{\hyperlink{sdk_8h_source_l00126}{mlx5\+\_\+fpga\+\_\+dma\+\_\+buf\+::complete}}, \mbox{\hyperlink{trans_8h_source_l00057}{mlx5\+\_\+fpga\+\_\+transaction\+::complete1}}, \mbox{\hyperlink{trans_8h_source_l00052}{mlx5\+\_\+fpga\+\_\+transaction\+::conn}}, \mbox{\hyperlink{sdk_8h_source_l00101}{mlx5\+\_\+fpga\+\_\+dma\+\_\+entry\+::data}}, \mbox{\hyperlink{trans_8h_source_l00056}{mlx5\+\_\+fpga\+\_\+transaction\+::data}}, \mbox{\hyperlink{trans_8h_source_l00053}{mlx5\+\_\+fpga\+\_\+transaction\+::direction}}, \mbox{\hyperlink{conn_8h_source_l00046}{mlx5\+\_\+fpga\+\_\+conn\+::fdev}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00094}{free\+\_\+tid()}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00050}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::header}}, \mbox{\hyperlink{mlx5fpga__conn_8c_source_l00175}{mlx5\+\_\+fpga\+\_\+conn\+\_\+send()}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00465}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+READ}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00466}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+WRITE}}, \mbox{\hyperlink{trans_8h_source_l00048}{MLX5\+\_\+\+FPGA\+\_\+\+WRITE}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, \mbox{\hyperlink{device_8h_source_l00106}{MLX5\+\_\+\+SET64}}, \mbox{\hyperlink{sdk_8h_source_l00116}{mlx5\+\_\+fpga\+\_\+dma\+\_\+buf\+::sg}}, \mbox{\hyperlink{sdk_8h_source_l00103}{mlx5\+\_\+fpga\+\_\+dma\+\_\+entry\+::size}}, \mbox{\hyperlink{trans_8h_source_l00054}{mlx5\+\_\+fpga\+\_\+transaction\+::size}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00048}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::state}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00047}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::tid}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00125}{trans\+\_\+send\+\_\+complete()}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00040}{TRANS\+\_\+\+STATE\+\_\+\+SEND}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00146}{trans\+\_\+validate()}}, and \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00046}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::user\+\_\+trans}}.



Referenced by \mbox{\hyperlink{mlx5fpga__xfer_8c_source_l00071}{exec\+\_\+more()}}.

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\includegraphics[width=350pt]{dd/df4/mlx5fpga__trans_8c_a5ab19e75b9ee247a0e1edf9878a61aad_cgraph}
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\mbox{\Hypertarget{mlx5fpga__trans_8c_a51ec92711d42a593954be18f06275d3a}\label{mlx5fpga__trans_8c_a51ec92711d42a593954be18f06275d3a}} 
\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!mlx5\_fpga\_trans\_recv@{mlx5\_fpga\_trans\_recv}}
\index{mlx5\_fpga\_trans\_recv@{mlx5\_fpga\_trans\_recv}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_trans\_recv()}{mlx5\_fpga\_trans\_recv()}}
{\footnotesize\ttfamily void mlx5\+\_\+fpga\+\_\+trans\+\_\+recv (\begin{DoxyParamCaption}\item[{void $\ast$}]{cb\+\_\+arg,  }\item[{struct \mbox{\hyperlink{structmlx5__fpga__dma__buf}{mlx5\+\_\+fpga\+\_\+dma\+\_\+buf}} $\ast$}]{buf }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00245}{245}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



References \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00051}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::buf}}, \mbox{\hyperlink{mlx5__en__tx_8c_source_l00001}{data}}, \mbox{\hyperlink{sdk_8h_source_l00101}{mlx5\+\_\+fpga\+\_\+dma\+\_\+entry\+::data}}, \mbox{\hyperlink{trans_8h_source_l00056}{mlx5\+\_\+fpga\+\_\+transaction\+::data}}, \mbox{\hyperlink{trans_8h_source_l00053}{mlx5\+\_\+fpga\+\_\+transaction\+::direction}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00061}{find\+\_\+tid()}}, \mbox{\hyperlink{device_8h_source_l00070}{MLX5\+\_\+\+ADDR\+\_\+\+OF}}, \mbox{\hyperlink{trans_8h_source_l00047}{MLX5\+\_\+\+FPGA\+\_\+\+READ}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00467}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+READ\+\_\+\+RESPONSE}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00468}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+WRITE\+\_\+\+RESPONSE}}, \mbox{\hyperlink{trans_8h_source_l00048}{MLX5\+\_\+\+FPGA\+\_\+\+WRITE}}, \mbox{\hyperlink{device_8h_source_l00091}{MLX5\+\_\+\+GET}}, \mbox{\hyperlink{device_8h_source_l00064}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+BYTES}}, \mbox{\hyperlink{sdk_8h_source_l00116}{mlx5\+\_\+fpga\+\_\+dma\+\_\+buf\+::sg}}, \mbox{\hyperlink{sdk_8h_source_l00103}{mlx5\+\_\+fpga\+\_\+dma\+\_\+entry\+::size}}, \mbox{\hyperlink{trans_8h_source_l00054}{mlx5\+\_\+fpga\+\_\+transaction\+::size}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00049}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::status}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00047}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::tid}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00104}{trans\+\_\+complete()}}, and \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00046}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::user\+\_\+trans}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00206}{mlx5\+\_\+fpga\+\_\+device\+\_\+start()}}.

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\mbox{\Hypertarget{mlx5fpga__trans_8c_a05338a5b5c6f538ecb516f3aefc01347}\label{mlx5fpga__trans_8c_a05338a5b5c6f538ecb516f3aefc01347}} 
\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!trans\_complete@{trans\_complete}}
\index{trans\_complete@{trans\_complete}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}
\doxysubsubsection{\texorpdfstring{trans\_complete()}{trans\_complete()}}
{\footnotesize\ttfamily static void trans\+\_\+complete (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev,  }\item[{struct \mbox{\hyperlink{structmlx5__fpga__trans__priv}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv}} $\ast$}]{trans\+\_\+priv,  }\item[{u8}]{status }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00104}{104}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



References \mbox{\hyperlink{trans_8h_source_l00057}{mlx5\+\_\+fpga\+\_\+transaction\+::complete1}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00094}{free\+\_\+tid()}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00048}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::state}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00049}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::status}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00047}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::tid}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00042}{TRANS\+\_\+\+STATE\+\_\+\+COMPLETE}}, and \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00046}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::user\+\_\+trans}}.



Referenced by \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00245}{mlx5\+\_\+fpga\+\_\+trans\+\_\+recv()}}, and \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00125}{trans\+\_\+send\+\_\+complete()}}.

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\mbox{\Hypertarget{mlx5fpga__trans_8c_a924834d0e9343004ccd461ea0467d085}\label{mlx5fpga__trans_8c_a924834d0e9343004ccd461ea0467d085}} 
\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!trans\_send\_complete@{trans\_send\_complete}}
\index{trans\_send\_complete@{trans\_send\_complete}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}
\doxysubsubsection{\texorpdfstring{trans\_send\_complete()}{trans\_send\_complete()}}
{\footnotesize\ttfamily static void trans\+\_\+send\+\_\+complete (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__fpga__conn}{mlx5\+\_\+fpga\+\_\+conn}} $\ast$}]{conn,  }\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev,  }\item[{struct \mbox{\hyperlink{structmlx5__fpga__dma__buf}{mlx5\+\_\+fpga\+\_\+dma\+\_\+buf}} $\ast$}]{buf,  }\item[{u8}]{status }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00125}{125}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



References \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00051}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::buf}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00048}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::state}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00049}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::status}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00047}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::tid}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00104}{trans\+\_\+complete()}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00040}{TRANS\+\_\+\+STATE\+\_\+\+SEND}}, and \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00041}{TRANS\+\_\+\+STATE\+\_\+\+WAIT}}.



Referenced by \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00184}{mlx5\+\_\+fpga\+\_\+trans\+\_\+exec()}}.

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\mbox{\Hypertarget{mlx5fpga__trans_8c_a245675d5f19bf8580f68d6cdc7e8ab67}\label{mlx5fpga__trans_8c_a245675d5f19bf8580f68d6cdc7e8ab67}} 
\index{mlx5fpga\_trans.c@{mlx5fpga\_trans.c}!trans\_validate@{trans\_validate}}
\index{trans\_validate@{trans\_validate}!mlx5fpga\_trans.c@{mlx5fpga\_trans.c}}
\doxysubsubsection{\texorpdfstring{trans\_validate()}{trans\_validate()}}
{\footnotesize\ttfamily static int trans\+\_\+validate (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev,  }\item[{u64}]{addr,  }\item[{size\+\_\+t}]{size }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00146}{146}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



References \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00273}{mlx5\+\_\+fpga\+\_\+ddr\+\_\+base\+\_\+get()}}, \mbox{\hyperlink{trans_8h_source_l00041}{MLX5\+\_\+\+FPGA\+\_\+\+TRANSACTION\+\_\+\+MAX\+\_\+\+SIZE}}, \mbox{\hyperlink{trans_8h_source_l00042}{MLX5\+\_\+\+FPGA\+\_\+\+TRANSACTION\+\_\+\+SEND\+\_\+\+ALIGN\+\_\+\+BITS}}, and \mbox{\hyperlink{trans_8h_source_l00043}{MLX5\+\_\+\+FPGA\+\_\+\+TRANSACTION\+\_\+\+SEND\+\_\+\+PAGE\+\_\+\+BITS}}.



Referenced by \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00184}{mlx5\+\_\+fpga\+\_\+trans\+\_\+exec()}}.

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