\hypertarget{mlx5io_8h}{}\doxysection{dev/mlx5/mlx5io.h File Reference}
\label{mlx5io_8h}\index{dev/mlx5/mlx5io.h@{dev/mlx5/mlx5io.h}}
{\ttfamily \#include $<$sys/ioccom.\+h$>$}\newline
Include dependency graph for mlx5io.\+h\+:
\nopagebreak
\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=188pt]{d6/d27/mlx5io_8h__incl}
\end{center}
\end{figure}
This graph shows which files directly or indirectly include this file\+:
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\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=350pt]{de/dda/mlx5io_8h__dep__incl}
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\end{figure}
\doxysubsection*{Data Structures}
\begin{DoxyCompactItemize}
\item 
struct \mbox{\hyperlink{structmlx5__fwdump__reg}{mlx5\+\_\+fwdump\+\_\+reg}}
\item 
struct \mbox{\hyperlink{structmlx5__tool__addr}{mlx5\+\_\+tool\+\_\+addr}}
\item 
struct \mbox{\hyperlink{structmlx5__fwdump__get}{mlx5\+\_\+fwdump\+\_\+get}}
\item 
struct \mbox{\hyperlink{structmlx5__fw__update}{mlx5\+\_\+fw\+\_\+update}}
\item 
struct \mbox{\hyperlink{structmlx5__eeprom__get}{mlx5\+\_\+eeprom\+\_\+get}}
\item 
struct \mbox{\hyperlink{structmlx5__fpga__query}{mlx5\+\_\+fpga\+\_\+query}}
\item 
struct \mbox{\hyperlink{structmlx5__fpga__temperature}{mlx5\+\_\+fpga\+\_\+temperature}}
\end{DoxyCompactItemize}
\doxysubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{mlx5io_8h_ae7979e6fb39624762871e455cc89c6ca}{MLX5\+\_\+\+FWDUMP\+\_\+\+GET}}~\+\_\+\+IOWR(\textquotesingle{}m\textquotesingle{}, 1, struct \mbox{\hyperlink{structmlx5__fwdump__get}{mlx5\+\_\+fwdump\+\_\+get}})
\item 
\#define \mbox{\hyperlink{mlx5io_8h_a124898102e789e80f011f38742004c62}{MLX5\+\_\+\+FWDUMP\+\_\+\+RESET}}~\+\_\+\+IOW(\textquotesingle{}m\textquotesingle{}, 2, struct \mbox{\hyperlink{structmlx5__tool__addr}{mlx5\+\_\+tool\+\_\+addr}})
\item 
\#define \mbox{\hyperlink{mlx5io_8h_a258e15696b53d7001acb45a3a1030a31}{MLX5\+\_\+\+FWDUMP\+\_\+\+FORCE}}~\+\_\+\+IOW(\textquotesingle{}m\textquotesingle{}, 3, struct \mbox{\hyperlink{structmlx5__tool__addr}{mlx5\+\_\+tool\+\_\+addr}})
\item 
\#define \mbox{\hyperlink{mlx5io_8h_af106927d97330f0e8ba454b3c22c2056}{MLX5\+\_\+\+FW\+\_\+\+UPDATE}}~\+\_\+\+IOW(\textquotesingle{}m\textquotesingle{}, 4, struct \mbox{\hyperlink{structmlx5__fw__update}{mlx5\+\_\+fw\+\_\+update}})
\item 
\#define \mbox{\hyperlink{mlx5io_8h_a19a88a371e35e3dd3ba06a5cff09b1e1}{MLX5\+\_\+\+FW\+\_\+\+RESET}}~\+\_\+\+IOW(\textquotesingle{}m\textquotesingle{}, 5, struct \mbox{\hyperlink{structmlx5__tool__addr}{mlx5\+\_\+tool\+\_\+addr}})
\item 
\#define \mbox{\hyperlink{mlx5io_8h_acf38d9ae4010a977e4fd7f165295814f}{MLX5\+\_\+\+EEPROM\+\_\+\+GET}}~\+\_\+\+IOWR(\textquotesingle{}m\textquotesingle{}, 6, struct \mbox{\hyperlink{structmlx5__eeprom__get}{mlx5\+\_\+eeprom\+\_\+get}})
\item 
\#define \mbox{\hyperlink{mlx5io_8h_a9dab7452d445834b7855b9b228badf47}{MLX5\+\_\+\+FPGA\+\_\+\+INTERNAL\+\_\+\+SENSORS\+\_\+\+LOW}}~63
\item 
\#define \mbox{\hyperlink{mlx5io_8h_a48a75936a769361254a210208178def3}{MLX5\+\_\+\+FPGA\+\_\+\+INTERNAL\+\_\+\+SENSORS\+\_\+\+HIGH}}~63
\item 
\#define \mbox{\hyperlink{mlx5io_8h_a93efc072ca718fe70be5c4074f893b3d}{MLX5\+\_\+\+FPGA\+\_\+\+CAP\+\_\+\+ARR\+\_\+\+SZ}}~0x40
\item 
\#define \mbox{\hyperlink{mlx5io_8h_a6086ed777f8aaab5c886becc8ebfb935}{MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+TYPE}}~\+\_\+\+IOWINT(\textquotesingle{}m\textquotesingle{}, 0x80)
\item 
\#define \mbox{\hyperlink{mlx5io_8h_ab9f3bc632bf7f9343c4d251d25599793}{MLX5\+\_\+\+FPGA\+\_\+\+LOAD}}~\+\_\+\+IOWINT(\textquotesingle{}m\textquotesingle{}, 0x81)
\item 
\#define \mbox{\hyperlink{mlx5io_8h_a5c0e83bc8d678bb5673fb62f4a63b795}{MLX5\+\_\+\+FPGA\+\_\+\+RESET}}~\+\_\+\+IO(\textquotesingle{}m\textquotesingle{}, 0x82)
\item 
\#define \mbox{\hyperlink{mlx5io_8h_ae07914032d0b365f5f1c20aaf90fc647}{MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+SEL}}~\+\_\+\+IOWINT(\textquotesingle{}m\textquotesingle{}, 0x83)
\item 
\#define \mbox{\hyperlink{mlx5io_8h_addfac1cb858c7f4b729176bc6a78ca28}{MLX5\+\_\+\+FPGA\+\_\+\+QUERY}}~\+\_\+\+IOR(\textquotesingle{}m\textquotesingle{}, 0x84, struct \mbox{\hyperlink{structmlx5__fpga__query}{mlx5\+\_\+fpga\+\_\+query}})
\item 
\#define \mbox{\hyperlink{mlx5io_8h_a5702b9ff4e61807117c84acf6c48fe64}{MLX5\+\_\+\+FPGA\+\_\+\+CAP}}~\+\_\+\+IOR(\textquotesingle{}m\textquotesingle{}, 0x85, uint32\+\_\+t\mbox{[}\mbox{\hyperlink{mlx5io_8h_a93efc072ca718fe70be5c4074f893b3d}{MLX5\+\_\+\+FPGA\+\_\+\+CAP\+\_\+\+ARR\+\_\+\+SZ}}\mbox{]})
\item 
\#define \mbox{\hyperlink{mlx5io_8h_a68081017a5919d021a8b4f14165e615d}{MLX5\+\_\+\+FPGA\+\_\+\+TEMPERATURE}}~\+\_\+\+IOWR(\textquotesingle{}m\textquotesingle{}, 0x86, struct \mbox{\hyperlink{structmlx5__fpga__temperature}{mlx5\+\_\+fpga\+\_\+temperature}})
\item 
\#define \mbox{\hyperlink{mlx5io_8h_add979f66c27048495ea28167838a4713}{MLX5\+\_\+\+FPGA\+\_\+\+CONNECT}}~\+\_\+\+IOWR(\textquotesingle{}m\textquotesingle{}, 0x87, enum \mbox{\hyperlink{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4}{mlx5\+\_\+fpga\+\_\+connect}})
\item 
\#define \mbox{\hyperlink{mlx5io_8h_a3ffa877f2613e5b6cc356d8da599ca16}{MLX5\+\_\+\+FPGA\+\_\+\+RELOAD}}~\+\_\+\+IO(\textquotesingle{}m\textquotesingle{}, 0x88)
\item 
\#define \mbox{\hyperlink{mlx5io_8h_a7fff35b506c70a52e3916b9abaa7048c}{MLX5\+\_\+\+FPGA\+\_\+\+TOOLS\+\_\+\+NAME\+\_\+\+SUFFIX}}~\char`\"{}\+\_\+mlx5\+\_\+fpga\+\_\+tools\char`\"{}
\end{DoxyCompactItemize}
\doxysubsection*{Enumerations}
\begin{DoxyCompactItemize}
\item 
enum \mbox{\hyperlink{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77b}{mlx5\+\_\+fpga\+\_\+id}} \{ \mbox{\hyperlink{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77ba42100fffe7823343c272c481a162ff18}{MLX5\+\_\+\+FPGA\+\_\+\+NEWTON}} = 0
, \mbox{\hyperlink{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77ba41eb4efc3a09a2cb7f8273d663f0fe0b}{MLX5\+\_\+\+FPGA\+\_\+\+EDISON}} = 1
, \mbox{\hyperlink{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77ba17a673c00c03138ad756687a72561b6a}{MLX5\+\_\+\+FPGA\+\_\+\+MORSE}} = 2
, \mbox{\hyperlink{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77ba5473f711b463fb1a796162dee80fb47a}{MLX5\+\_\+\+FPGA\+\_\+\+MORSEQ}} = 3
 \}
\item 
enum \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303}{mlx5\+\_\+fpga\+\_\+image}} \{ \newline
\mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303a252b496c89a9e3e05c0ce1a23e906e2f}{MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+USER}} = 0
, \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303ad9b44985c2d3522dd22e3635e7cc5ad8}{MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+FACTORY}} = 1
, \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303ab562ea833cece978b4915f0b0c1ac940}{MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+FACTORY\+\_\+\+FAILOVER}} = 2
, \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303a0296a8cbe4b0668f22c2a2f1fb763cc8}{MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+RESET}} = 17
, \newline
\mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303a9309f20dbda27637d7a88ea23495e967}{MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+RELOAD}} = 18
 \}
\item 
enum \mbox{\hyperlink{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9e}{mlx5\+\_\+fpga\+\_\+status}} \{ \mbox{\hyperlink{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9ea0a3939935c0e7f3226152584ebfc1074}{MLX5\+\_\+\+FPGA\+\_\+\+STATUS\+\_\+\+SUCCESS}} = 0
, \mbox{\hyperlink{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9ea76cd99fcf30404a095f80f077b33955e}{MLX5\+\_\+\+FPGA\+\_\+\+STATUS\+\_\+\+FAILURE}} = 1
, \mbox{\hyperlink{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9ea953cd299aaf5b4595ff837fc986ad21d}{MLX5\+\_\+\+FPGA\+\_\+\+STATUS\+\_\+\+IN\+\_\+\+PROGRESS}} = 2
, \mbox{\hyperlink{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9eaf7f3d133ca46007b9587cf80bcf50579}{MLX5\+\_\+\+FPGA\+\_\+\+STATUS\+\_\+\+DISCONNECTED}} = 3
 \}
\item 
enum \mbox{\hyperlink{mlx5io_8h_a739cd041447d60e523dad80bbc596b13}{mlx5\+\_\+fpga\+\_\+tee}} \{ \mbox{\hyperlink{mlx5io_8h_a739cd041447d60e523dad80bbc596b13aac54e6cd772d6f886843d8e2b9e05cc9}{MLX5\+\_\+\+FPGA\+\_\+\+TEE\+\_\+\+DISABLE}} = 0
, \mbox{\hyperlink{mlx5io_8h_a739cd041447d60e523dad80bbc596b13a4a3028918b639950b85d2676f4eb6346}{MLX5\+\_\+\+FPGA\+\_\+\+TEE\+\_\+\+GENERATE\+\_\+\+EVENT}} = 1
, \mbox{\hyperlink{mlx5io_8h_a739cd041447d60e523dad80bbc596b13a2a40ee8120cf83b733222e89692573de}{MLX5\+\_\+\+FPGA\+\_\+\+TEE\+\_\+\+GENERATE\+\_\+\+SINGLE\+\_\+\+EVENT}} = 2
 \}
\item 
enum \mbox{\hyperlink{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4}{mlx5\+\_\+fpga\+\_\+connect}} \{ \mbox{\hyperlink{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4a8702c60fdc90287b1955eb98b92b5784}{MLX5\+\_\+\+FPGA\+\_\+\+CONNECT\+\_\+\+QUERY}} = 0
, \mbox{\hyperlink{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4a83361ce5e629a79d6aac3d59997dbb3a}{MLX5\+\_\+\+FPGA\+\_\+\+CONNECT\+\_\+\+DISCONNECT}} = 0x9
, \mbox{\hyperlink{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4a390c111156eeeecd32dd9d8e87208e32}{MLX5\+\_\+\+FPGA\+\_\+\+CONNECT\+\_\+\+CONNECT}} = 0xA
 \}
\item 
enum \mbox{\hyperlink{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350b}{mlx5\+\_\+fpga\+\_\+access\+\_\+type}} \{ \mbox{\hyperlink{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350ba01696d6c0ffc220341f5a7aaaa0bc2de}{MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+TYPE\+\_\+\+I2C}} = 0x0
, \mbox{\hyperlink{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350ba7e3df6c99d377a21f2925f4ac17fa5dc}{MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+TYPE\+\_\+\+RDMA}}
, \mbox{\hyperlink{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350ba61675a1252d96c29834cee811c8517d1}{MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+TYPE\+\_\+\+DONTCARE}}
, \mbox{\hyperlink{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350bae7ba3ff42a463c314ffe8b2f0d37f2a7}{MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+TYPE\+\_\+\+MAX}} = MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+TYPE\+\_\+\+DONTCARE
 \}
\end{DoxyCompactItemize}


\doxysubsection{Macro Definition Documentation}
\mbox{\Hypertarget{mlx5io_8h_acf38d9ae4010a977e4fd7f165295814f}\label{mlx5io_8h_acf38d9ae4010a977e4fd7f165295814f}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_EEPROM\_GET@{MLX5\_EEPROM\_GET}}
\index{MLX5\_EEPROM\_GET@{MLX5\_EEPROM\_GET}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_EEPROM\_GET}{MLX5\_EEPROM\_GET}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+EEPROM\+\_\+\+GET~\+\_\+\+IOWR(\textquotesingle{}m\textquotesingle{}, 6, struct \mbox{\hyperlink{structmlx5__eeprom__get}{mlx5\+\_\+eeprom\+\_\+get}})}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00070}{70}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a6086ed777f8aaab5c886becc8ebfb935}\label{mlx5io_8h_a6086ed777f8aaab5c886becc8ebfb935}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_ACCESS\_TYPE@{MLX5\_FPGA\_ACCESS\_TYPE}}
\index{MLX5\_FPGA\_ACCESS\_TYPE@{MLX5\_FPGA\_ACCESS\_TYPE}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_ACCESS\_TYPE}{MLX5\_FPGA\_ACCESS\_TYPE}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+TYPE~\+\_\+\+IOWINT(\textquotesingle{}m\textquotesingle{}, 0x80)}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00147}{147}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a5702b9ff4e61807117c84acf6c48fe64}\label{mlx5io_8h_a5702b9ff4e61807117c84acf6c48fe64}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_CAP@{MLX5\_FPGA\_CAP}}
\index{MLX5\_FPGA\_CAP@{MLX5\_FPGA\_CAP}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_CAP}{MLX5\_FPGA\_CAP}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+CAP~\+\_\+\+IOR(\textquotesingle{}m\textquotesingle{}, 0x85, uint32\+\_\+t\mbox{[}\mbox{\hyperlink{mlx5io_8h_a93efc072ca718fe70be5c4074f893b3d}{MLX5\+\_\+\+FPGA\+\_\+\+CAP\+\_\+\+ARR\+\_\+\+SZ}}\mbox{]})}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00152}{152}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a93efc072ca718fe70be5c4074f893b3d}\label{mlx5io_8h_a93efc072ca718fe70be5c4074f893b3d}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_CAP\_ARR\_SZ@{MLX5\_FPGA\_CAP\_ARR\_SZ}}
\index{MLX5\_FPGA\_CAP\_ARR\_SZ@{MLX5\_FPGA\_CAP\_ARR\_SZ}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_CAP\_ARR\_SZ}{MLX5\_FPGA\_CAP\_ARR\_SZ}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+CAP\+\_\+\+ARR\+\_\+\+SZ~0x40}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00145}{145}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_add979f66c27048495ea28167838a4713}\label{mlx5io_8h_add979f66c27048495ea28167838a4713}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_CONNECT@{MLX5\_FPGA\_CONNECT}}
\index{MLX5\_FPGA\_CONNECT@{MLX5\_FPGA\_CONNECT}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_CONNECT}{MLX5\_FPGA\_CONNECT}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+CONNECT~\+\_\+\+IOWR(\textquotesingle{}m\textquotesingle{}, 0x87, enum \mbox{\hyperlink{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4}{mlx5\+\_\+fpga\+\_\+connect}})}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00154}{154}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_ae07914032d0b365f5f1c20aaf90fc647}\label{mlx5io_8h_ae07914032d0b365f5f1c20aaf90fc647}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_IMAGE\_SEL@{MLX5\_FPGA\_IMAGE\_SEL}}
\index{MLX5\_FPGA\_IMAGE\_SEL@{MLX5\_FPGA\_IMAGE\_SEL}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_IMAGE\_SEL}{MLX5\_FPGA\_IMAGE\_SEL}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+SEL~\+\_\+\+IOWINT(\textquotesingle{}m\textquotesingle{}, 0x83)}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00150}{150}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a48a75936a769361254a210208178def3}\label{mlx5io_8h_a48a75936a769361254a210208178def3}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_INTERNAL\_SENSORS\_HIGH@{MLX5\_FPGA\_INTERNAL\_SENSORS\_HIGH}}
\index{MLX5\_FPGA\_INTERNAL\_SENSORS\_HIGH@{MLX5\_FPGA\_INTERNAL\_SENSORS\_HIGH}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_INTERNAL\_SENSORS\_HIGH}{MLX5\_FPGA\_INTERNAL\_SENSORS\_HIGH}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+INTERNAL\+\_\+\+SENSORS\+\_\+\+HIGH~63}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00131}{131}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a9dab7452d445834b7855b9b228badf47}\label{mlx5io_8h_a9dab7452d445834b7855b9b228badf47}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_INTERNAL\_SENSORS\_LOW@{MLX5\_FPGA\_INTERNAL\_SENSORS\_LOW}}
\index{MLX5\_FPGA\_INTERNAL\_SENSORS\_LOW@{MLX5\_FPGA\_INTERNAL\_SENSORS\_LOW}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_INTERNAL\_SENSORS\_LOW}{MLX5\_FPGA\_INTERNAL\_SENSORS\_LOW}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+INTERNAL\+\_\+\+SENSORS\+\_\+\+LOW~63}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00130}{130}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_ab9f3bc632bf7f9343c4d251d25599793}\label{mlx5io_8h_ab9f3bc632bf7f9343c4d251d25599793}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_LOAD@{MLX5\_FPGA\_LOAD}}
\index{MLX5\_FPGA\_LOAD@{MLX5\_FPGA\_LOAD}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_LOAD}{MLX5\_FPGA\_LOAD}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+LOAD~\+\_\+\+IOWINT(\textquotesingle{}m\textquotesingle{}, 0x81)}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00148}{148}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_addfac1cb858c7f4b729176bc6a78ca28}\label{mlx5io_8h_addfac1cb858c7f4b729176bc6a78ca28}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_QUERY@{MLX5\_FPGA\_QUERY}}
\index{MLX5\_FPGA\_QUERY@{MLX5\_FPGA\_QUERY}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_QUERY}{MLX5\_FPGA\_QUERY}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+QUERY~\+\_\+\+IOR(\textquotesingle{}m\textquotesingle{}, 0x84, struct \mbox{\hyperlink{structmlx5__fpga__query}{mlx5\+\_\+fpga\+\_\+query}})}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00151}{151}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a3ffa877f2613e5b6cc356d8da599ca16}\label{mlx5io_8h_a3ffa877f2613e5b6cc356d8da599ca16}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_RELOAD@{MLX5\_FPGA\_RELOAD}}
\index{MLX5\_FPGA\_RELOAD@{MLX5\_FPGA\_RELOAD}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_RELOAD}{MLX5\_FPGA\_RELOAD}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+RELOAD~\+\_\+\+IO(\textquotesingle{}m\textquotesingle{}, 0x88)}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00155}{155}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a5c0e83bc8d678bb5673fb62f4a63b795}\label{mlx5io_8h_a5c0e83bc8d678bb5673fb62f4a63b795}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_RESET@{MLX5\_FPGA\_RESET}}
\index{MLX5\_FPGA\_RESET@{MLX5\_FPGA\_RESET}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_RESET}{MLX5\_FPGA\_RESET}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+RESET~\+\_\+\+IO(\textquotesingle{}m\textquotesingle{}, 0x82)}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00149}{149}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a68081017a5919d021a8b4f14165e615d}\label{mlx5io_8h_a68081017a5919d021a8b4f14165e615d}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_TEMPERATURE@{MLX5\_FPGA\_TEMPERATURE}}
\index{MLX5\_FPGA\_TEMPERATURE@{MLX5\_FPGA\_TEMPERATURE}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_TEMPERATURE}{MLX5\_FPGA\_TEMPERATURE}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+TEMPERATURE~\+\_\+\+IOWR(\textquotesingle{}m\textquotesingle{}, 0x86, struct \mbox{\hyperlink{structmlx5__fpga__temperature}{mlx5\+\_\+fpga\+\_\+temperature}})}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00153}{153}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a7fff35b506c70a52e3916b9abaa7048c}\label{mlx5io_8h_a7fff35b506c70a52e3916b9abaa7048c}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_TOOLS\_NAME\_SUFFIX@{MLX5\_FPGA\_TOOLS\_NAME\_SUFFIX}}
\index{MLX5\_FPGA\_TOOLS\_NAME\_SUFFIX@{MLX5\_FPGA\_TOOLS\_NAME\_SUFFIX}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_TOOLS\_NAME\_SUFFIX}{MLX5\_FPGA\_TOOLS\_NAME\_SUFFIX}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+TOOLS\+\_\+\+NAME\+\_\+\+SUFFIX~\char`\"{}\+\_\+mlx5\+\_\+fpga\+\_\+tools\char`\"{}}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00157}{157}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a19a88a371e35e3dd3ba06a5cff09b1e1}\label{mlx5io_8h_a19a88a371e35e3dd3ba06a5cff09b1e1}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FW\_RESET@{MLX5\_FW\_RESET}}
\index{MLX5\_FW\_RESET@{MLX5\_FW\_RESET}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FW\_RESET}{MLX5\_FW\_RESET}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FW\+\_\+\+RESET~\+\_\+\+IOW(\textquotesingle{}m\textquotesingle{}, 5, struct \mbox{\hyperlink{structmlx5__tool__addr}{mlx5\+\_\+tool\+\_\+addr}})}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00069}{69}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_af106927d97330f0e8ba454b3c22c2056}\label{mlx5io_8h_af106927d97330f0e8ba454b3c22c2056}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FW\_UPDATE@{MLX5\_FW\_UPDATE}}
\index{MLX5\_FW\_UPDATE@{MLX5\_FW\_UPDATE}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FW\_UPDATE}{MLX5\_FW\_UPDATE}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FW\+\_\+\+UPDATE~\+\_\+\+IOW(\textquotesingle{}m\textquotesingle{}, 4, struct \mbox{\hyperlink{structmlx5__fw__update}{mlx5\+\_\+fw\+\_\+update}})}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00068}{68}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a258e15696b53d7001acb45a3a1030a31}\label{mlx5io_8h_a258e15696b53d7001acb45a3a1030a31}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FWDUMP\_FORCE@{MLX5\_FWDUMP\_FORCE}}
\index{MLX5\_FWDUMP\_FORCE@{MLX5\_FWDUMP\_FORCE}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FWDUMP\_FORCE}{MLX5\_FWDUMP\_FORCE}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FWDUMP\+\_\+\+FORCE~\+\_\+\+IOW(\textquotesingle{}m\textquotesingle{}, 3, struct \mbox{\hyperlink{structmlx5__tool__addr}{mlx5\+\_\+tool\+\_\+addr}})}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00067}{67}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_ae7979e6fb39624762871e455cc89c6ca}\label{mlx5io_8h_ae7979e6fb39624762871e455cc89c6ca}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FWDUMP\_GET@{MLX5\_FWDUMP\_GET}}
\index{MLX5\_FWDUMP\_GET@{MLX5\_FWDUMP\_GET}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FWDUMP\_GET}{MLX5\_FWDUMP\_GET}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FWDUMP\+\_\+\+GET~\+\_\+\+IOWR(\textquotesingle{}m\textquotesingle{}, 1, struct \mbox{\hyperlink{structmlx5__fwdump__get}{mlx5\+\_\+fwdump\+\_\+get}})}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00065}{65}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a124898102e789e80f011f38742004c62}\label{mlx5io_8h_a124898102e789e80f011f38742004c62}} 
\index{mlx5io.h@{mlx5io.h}!MLX5\_FWDUMP\_RESET@{MLX5\_FWDUMP\_RESET}}
\index{MLX5\_FWDUMP\_RESET@{MLX5\_FWDUMP\_RESET}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FWDUMP\_RESET}{MLX5\_FWDUMP\_RESET}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FWDUMP\+\_\+\+RESET~\+\_\+\+IOW(\textquotesingle{}m\textquotesingle{}, 2, struct \mbox{\hyperlink{structmlx5__tool__addr}{mlx5\+\_\+tool\+\_\+addr}})}



Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00066}{66}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.



\doxysubsection{Enumeration Type Documentation}
\mbox{\Hypertarget{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350b}\label{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350b}} 
\index{mlx5io.h@{mlx5io.h}!mlx5\_fpga\_access\_type@{mlx5\_fpga\_access\_type}}
\index{mlx5\_fpga\_access\_type@{mlx5\_fpga\_access\_type}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_access\_type}{mlx5\_fpga\_access\_type}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350b}{mlx5\+\_\+fpga\+\_\+access\+\_\+type}}}

enum mlx5\+\_\+fpga\+\_\+access\+\_\+type -\/ Enumerated the different methods possible for accessing the device memory address space \begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_ACCESS\_TYPE\_I2C@{MLX5\_FPGA\_ACCESS\_TYPE\_I2C}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_ACCESS\_TYPE\_I2C@{MLX5\_FPGA\_ACCESS\_TYPE\_I2C}}}\mbox{\Hypertarget{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350ba01696d6c0ffc220341f5a7aaaa0bc2de}\label{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350ba01696d6c0ffc220341f5a7aaaa0bc2de}} 
MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+TYPE\+\_\+\+I2C&Use the slow CX-\/\+FPGA I2C bus \\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_ACCESS\_TYPE\_RDMA@{MLX5\_FPGA\_ACCESS\_TYPE\_RDMA}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_ACCESS\_TYPE\_RDMA@{MLX5\_FPGA\_ACCESS\_TYPE\_RDMA}}}\mbox{\Hypertarget{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350ba7e3df6c99d377a21f2925f4ac17fa5dc}\label{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350ba7e3df6c99d377a21f2925f4ac17fa5dc}} 
MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+TYPE\+\_\+\+RDMA&Use the fast \textquotesingle{}shell QP\textquotesingle{} \\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_ACCESS\_TYPE\_DONTCARE@{MLX5\_FPGA\_ACCESS\_TYPE\_DONTCARE}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_ACCESS\_TYPE\_DONTCARE@{MLX5\_FPGA\_ACCESS\_TYPE\_DONTCARE}}}\mbox{\Hypertarget{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350ba61675a1252d96c29834cee811c8517d1}\label{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350ba61675a1252d96c29834cee811c8517d1}} 
MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+TYPE\+\_\+\+DONTCARE&Use the fastest available method \\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_ACCESS\_TYPE\_MAX@{MLX5\_FPGA\_ACCESS\_TYPE\_MAX}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_ACCESS\_TYPE\_MAX@{MLX5\_FPGA\_ACCESS\_TYPE\_MAX}}}\mbox{\Hypertarget{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350bae7ba3ff42a463c314ffe8b2f0d37f2a7}\label{mlx5io_8h_a3dfefb3a6f72bdc66a27282031d1350bae7ba3ff42a463c314ffe8b2f0d37f2a7}} 
MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+TYPE\+\_\+\+MAX&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00120}{120}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4}\label{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4}} 
\index{mlx5io.h@{mlx5io.h}!mlx5\_fpga\_connect@{mlx5\_fpga\_connect}}
\index{mlx5\_fpga\_connect@{mlx5\_fpga\_connect}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_connect}{mlx5\_fpga\_connect}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4}{mlx5\+\_\+fpga\+\_\+connect}}}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CONNECT\_QUERY@{MLX5\_FPGA\_CONNECT\_QUERY}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_CONNECT\_QUERY@{MLX5\_FPGA\_CONNECT\_QUERY}}}\mbox{\Hypertarget{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4a8702c60fdc90287b1955eb98b92b5784}\label{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4a8702c60fdc90287b1955eb98b92b5784}} 
MLX5\+\_\+\+FPGA\+\_\+\+CONNECT\+\_\+\+QUERY&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CONNECT\_DISCONNECT@{MLX5\_FPGA\_CONNECT\_DISCONNECT}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_CONNECT\_DISCONNECT@{MLX5\_FPGA\_CONNECT\_DISCONNECT}}}\mbox{\Hypertarget{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4a83361ce5e629a79d6aac3d59997dbb3a}\label{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4a83361ce5e629a79d6aac3d59997dbb3a}} 
MLX5\+\_\+\+FPGA\+\_\+\+CONNECT\+\_\+\+DISCONNECT&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CONNECT\_CONNECT@{MLX5\_FPGA\_CONNECT\_CONNECT}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_CONNECT\_CONNECT@{MLX5\_FPGA\_CONNECT\_CONNECT}}}\mbox{\Hypertarget{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4a390c111156eeeecd32dd9d8e87208e32}\label{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4a390c111156eeeecd32dd9d8e87208e32}} 
MLX5\+\_\+\+FPGA\+\_\+\+CONNECT\+\_\+\+CONNECT&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00110}{110}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77b}\label{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77b}} 
\index{mlx5io.h@{mlx5io.h}!mlx5\_fpga\_id@{mlx5\_fpga\_id}}
\index{mlx5\_fpga\_id@{mlx5\_fpga\_id}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_id}{mlx5\_fpga\_id}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77b}{mlx5\+\_\+fpga\+\_\+id}}}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_NEWTON@{MLX5\_FPGA\_NEWTON}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_NEWTON@{MLX5\_FPGA\_NEWTON}}}\mbox{\Hypertarget{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77ba42100fffe7823343c272c481a162ff18}\label{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77ba42100fffe7823343c272c481a162ff18}} 
MLX5\+\_\+\+FPGA\+\_\+\+NEWTON&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_EDISON@{MLX5\_FPGA\_EDISON}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_EDISON@{MLX5\_FPGA\_EDISON}}}\mbox{\Hypertarget{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77ba41eb4efc3a09a2cb7f8273d663f0fe0b}\label{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77ba41eb4efc3a09a2cb7f8273d663f0fe0b}} 
MLX5\+\_\+\+FPGA\+\_\+\+EDISON&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_MORSE@{MLX5\_FPGA\_MORSE}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_MORSE@{MLX5\_FPGA\_MORSE}}}\mbox{\Hypertarget{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77ba17a673c00c03138ad756687a72561b6a}\label{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77ba17a673c00c03138ad756687a72561b6a}} 
MLX5\+\_\+\+FPGA\+\_\+\+MORSE&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_MORSEQ@{MLX5\_FPGA\_MORSEQ}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_MORSEQ@{MLX5\_FPGA\_MORSEQ}}}\mbox{\Hypertarget{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77ba5473f711b463fb1a796162dee80fb47a}\label{mlx5io_8h_ab7b7125f7ca40d4bb405502f2a0ac77ba5473f711b463fb1a796162dee80fb47a}} 
MLX5\+\_\+\+FPGA\+\_\+\+MORSEQ&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00076}{76}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303}\label{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303}} 
\index{mlx5io.h@{mlx5io.h}!mlx5\_fpga\_image@{mlx5\_fpga\_image}}
\index{mlx5\_fpga\_image@{mlx5\_fpga\_image}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_image}{mlx5\_fpga\_image}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303}{mlx5\+\_\+fpga\+\_\+image}}}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_IMAGE\_USER@{MLX5\_FPGA\_IMAGE\_USER}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_IMAGE\_USER@{MLX5\_FPGA\_IMAGE\_USER}}}\mbox{\Hypertarget{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303a252b496c89a9e3e05c0ce1a23e906e2f}\label{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303a252b496c89a9e3e05c0ce1a23e906e2f}} 
MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+USER&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_IMAGE\_FACTORY@{MLX5\_FPGA\_IMAGE\_FACTORY}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_IMAGE\_FACTORY@{MLX5\_FPGA\_IMAGE\_FACTORY}}}\mbox{\Hypertarget{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303ad9b44985c2d3522dd22e3635e7cc5ad8}\label{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303ad9b44985c2d3522dd22e3635e7cc5ad8}} 
MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+FACTORY&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_IMAGE\_FACTORY\_FAILOVER@{MLX5\_FPGA\_IMAGE\_FACTORY\_FAILOVER}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_IMAGE\_FACTORY\_FAILOVER@{MLX5\_FPGA\_IMAGE\_FACTORY\_FAILOVER}}}\mbox{\Hypertarget{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303ab562ea833cece978b4915f0b0c1ac940}\label{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303ab562ea833cece978b4915f0b0c1ac940}} 
MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+FACTORY\+\_\+\+FAILOVER&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_IMAGE\_RESET@{MLX5\_FPGA\_IMAGE\_RESET}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_IMAGE\_RESET@{MLX5\_FPGA\_IMAGE\_RESET}}}\mbox{\Hypertarget{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303a0296a8cbe4b0668f22c2a2f1fb763cc8}\label{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303a0296a8cbe4b0668f22c2a2f1fb763cc8}} 
MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+RESET&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_IMAGE\_RELOAD@{MLX5\_FPGA\_IMAGE\_RELOAD}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_IMAGE\_RELOAD@{MLX5\_FPGA\_IMAGE\_RELOAD}}}\mbox{\Hypertarget{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303a9309f20dbda27637d7a88ea23495e967}\label{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303a9309f20dbda27637d7a88ea23495e967}} 
MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+RELOAD&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00083}{83}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9e}\label{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9e}} 
\index{mlx5io.h@{mlx5io.h}!mlx5\_fpga\_status@{mlx5\_fpga\_status}}
\index{mlx5\_fpga\_status@{mlx5\_fpga\_status}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_status}{mlx5\_fpga\_status}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9e}{mlx5\+\_\+fpga\+\_\+status}}}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_STATUS\_SUCCESS@{MLX5\_FPGA\_STATUS\_SUCCESS}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_STATUS\_SUCCESS@{MLX5\_FPGA\_STATUS\_SUCCESS}}}\mbox{\Hypertarget{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9ea0a3939935c0e7f3226152584ebfc1074}\label{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9ea0a3939935c0e7f3226152584ebfc1074}} 
MLX5\+\_\+\+FPGA\+\_\+\+STATUS\+\_\+\+SUCCESS&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_STATUS\_FAILURE@{MLX5\_FPGA\_STATUS\_FAILURE}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_STATUS\_FAILURE@{MLX5\_FPGA\_STATUS\_FAILURE}}}\mbox{\Hypertarget{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9ea76cd99fcf30404a095f80f077b33955e}\label{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9ea76cd99fcf30404a095f80f077b33955e}} 
MLX5\+\_\+\+FPGA\+\_\+\+STATUS\+\_\+\+FAILURE&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_STATUS\_IN\_PROGRESS@{MLX5\_FPGA\_STATUS\_IN\_PROGRESS}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_STATUS\_IN\_PROGRESS@{MLX5\_FPGA\_STATUS\_IN\_PROGRESS}}}\mbox{\Hypertarget{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9ea953cd299aaf5b4595ff837fc986ad21d}\label{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9ea953cd299aaf5b4595ff837fc986ad21d}} 
MLX5\+\_\+\+FPGA\+\_\+\+STATUS\+\_\+\+IN\+\_\+\+PROGRESS&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_STATUS\_DISCONNECTED@{MLX5\_FPGA\_STATUS\_DISCONNECTED}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_STATUS\_DISCONNECTED@{MLX5\_FPGA\_STATUS\_DISCONNECTED}}}\mbox{\Hypertarget{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9eaf7f3d133ca46007b9587cf80bcf50579}\label{mlx5io_8h_aa339313b4a975c2fc0d01900550b5d9eaf7f3d133ca46007b9587cf80bcf50579}} 
MLX5\+\_\+\+FPGA\+\_\+\+STATUS\+\_\+\+DISCONNECTED&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00091}{91}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

\mbox{\Hypertarget{mlx5io_8h_a739cd041447d60e523dad80bbc596b13}\label{mlx5io_8h_a739cd041447d60e523dad80bbc596b13}} 
\index{mlx5io.h@{mlx5io.h}!mlx5\_fpga\_tee@{mlx5\_fpga\_tee}}
\index{mlx5\_fpga\_tee@{mlx5\_fpga\_tee}!mlx5io.h@{mlx5io.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_tee}{mlx5\_fpga\_tee}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{mlx5io_8h_a739cd041447d60e523dad80bbc596b13}{mlx5\+\_\+fpga\+\_\+tee}}}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_TEE\_DISABLE@{MLX5\_FPGA\_TEE\_DISABLE}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_TEE\_DISABLE@{MLX5\_FPGA\_TEE\_DISABLE}}}\mbox{\Hypertarget{mlx5io_8h_a739cd041447d60e523dad80bbc596b13aac54e6cd772d6f886843d8e2b9e05cc9}\label{mlx5io_8h_a739cd041447d60e523dad80bbc596b13aac54e6cd772d6f886843d8e2b9e05cc9}} 
MLX5\+\_\+\+FPGA\+\_\+\+TEE\+\_\+\+DISABLE&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_TEE\_GENERATE\_EVENT@{MLX5\_FPGA\_TEE\_GENERATE\_EVENT}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_TEE\_GENERATE\_EVENT@{MLX5\_FPGA\_TEE\_GENERATE\_EVENT}}}\mbox{\Hypertarget{mlx5io_8h_a739cd041447d60e523dad80bbc596b13a4a3028918b639950b85d2676f4eb6346}\label{mlx5io_8h_a739cd041447d60e523dad80bbc596b13a4a3028918b639950b85d2676f4eb6346}} 
MLX5\+\_\+\+FPGA\+\_\+\+TEE\+\_\+\+GENERATE\+\_\+\+EVENT&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_TEE\_GENERATE\_SINGLE\_EVENT@{MLX5\_FPGA\_TEE\_GENERATE\_SINGLE\_EVENT}!mlx5io.h@{mlx5io.h}}\index{mlx5io.h@{mlx5io.h}!MLX5\_FPGA\_TEE\_GENERATE\_SINGLE\_EVENT@{MLX5\_FPGA\_TEE\_GENERATE\_SINGLE\_EVENT}}}\mbox{\Hypertarget{mlx5io_8h_a739cd041447d60e523dad80bbc596b13a2a40ee8120cf83b733222e89692573de}\label{mlx5io_8h_a739cd041447d60e523dad80bbc596b13a2a40ee8120cf83b733222e89692573de}} 
MLX5\+\_\+\+FPGA\+\_\+\+TEE\+\_\+\+GENERATE\+\_\+\+SINGLE\+\_\+\+EVENT&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5io_8h_source_l00104}{104}} of file \mbox{\hyperlink{mlx5io_8h_source}{mlx5io.\+h}}.

