\hypertarget{mlx5__ib__mem_8c_source}{}\doxysection{mlx5\+\_\+ib\+\_\+mem.\+c}
\label{mlx5__ib__mem_8c_source}\index{dev/mlx5/mlx5\_ib/mlx5\_ib\_mem.c@{dev/mlx5/mlx5\_ib/mlx5\_ib\_mem.c}}
\mbox{\hyperlink{mlx5__ib__mem_8c}{Go to the documentation of this file.}}
\begin{DoxyCode}{0}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00001}00001 \textcolor{comment}{/*-\/}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00002}00002 \textcolor{comment}{ * Copyright (c) 2013-\/2020, Mellanox Technologies, Ltd.  All rights reserved.}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00003}00003 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00004}00004 \textcolor{comment}{ * Redistribution and use in source and binary forms, with or without}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00005}00005 \textcolor{comment}{ * modification, are permitted provided that the following conditions}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00006}00006 \textcolor{comment}{ * are met:}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00007}00007 \textcolor{comment}{ * 1. Redistributions of source code must retain the above copyright}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00008}00008 \textcolor{comment}{ *    notice, this list of conditions and the following disclaimer.}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00009}00009 \textcolor{comment}{ * 2. Redistributions in binary form must reproduce the above copyright}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00010}00010 \textcolor{comment}{ *    notice, this list of conditions and the following disclaimer in the}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00011}00011 \textcolor{comment}{ *    documentation and/or other materials provided with the distribution.}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00012}00012 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00013}00013 \textcolor{comment}{ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00014}00014 \textcolor{comment}{ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00015}00015 \textcolor{comment}{ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00016}00016 \textcolor{comment}{ * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00017}00017 \textcolor{comment}{ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00018}00018 \textcolor{comment}{ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00019}00019 \textcolor{comment}{ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00020}00020 \textcolor{comment}{ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00021}00021 \textcolor{comment}{ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00022}00022 \textcolor{comment}{ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00023}00023 \textcolor{comment}{ * SUCH DAMAGE.}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00024}00024 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00025}00025 \textcolor{comment}{ * \$FreeBSD\$}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00026}00026 \textcolor{comment}{ */}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00027}00027 }
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00028}00028 \textcolor{preprocessor}{\#include "{}opt\_rss.h"{}}}
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\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00031}00031 \textcolor{preprocessor}{\#include <linux/module.h>}}
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\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00036}00036 \textcolor{comment}{/* @umem: umem object to scan}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00037}00037 \textcolor{comment}{ * @addr: ib virtual address requested by the user}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00038}00038 \textcolor{comment}{ * @max\_page\_shift: high limit for page\_shift -\/ 0 means no limit}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00039}00039 \textcolor{comment}{ * @count: number of PAGE\_SIZE pages covered by umem}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00040}00040 \textcolor{comment}{ * @shift: page shift for the compound pages found in the region}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00041}00041 \textcolor{comment}{ * @ncont: number of compund pages}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00042}00042 \textcolor{comment}{ * @order: log2 of the number of compound pages}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00043}00043 \textcolor{comment}{ */}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00044}\mbox{\hyperlink{mlx5__ib_8h_a078af05e9a50b56546252df6754917b9}{00044}} \textcolor{keywordtype}{void} \mbox{\hyperlink{mlx5__ib__mem_8c_a078af05e9a50b56546252df6754917b9}{mlx5\_ib\_cont\_pages}}(\textcolor{keyword}{struct} ib\_umem *umem, u64 addr,}
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\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00048}00048 \{}
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\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00054}00054         \textcolor{keyword}{struct }scatterlist *sg;}
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\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00056}00056 }
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00057}00057         addr = addr >> PAGE\_SHIFT;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00058}00058         tmp = (\textcolor{keywordtype}{unsigned} long)addr;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00059}00059         m = find\_first\_bit(\&tmp, BITS\_PER\_LONG);}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00060}00060         \textcolor{keywordflow}{if} (max\_page\_shift)}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00061}00061                 m = min\_t(\textcolor{keywordtype}{unsigned} \textcolor{keywordtype}{long}, max\_page\_shift -\/ PAGE\_SHIFT, m);}
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\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00063}00063         for\_each\_sg(umem-\/>sg\_head.sgl, sg, umem-\/>nmap, entry) \{}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00064}00064                 len = sg\_dma\_len(sg) >> PAGE\_SHIFT;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00065}00065                 pfn = sg\_dma\_address(sg) >> PAGE\_SHIFT;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00066}00066                 \textcolor{keywordflow}{if} (base + p != pfn) \{}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00067}00067                         \textcolor{comment}{/* If either the offset or the new}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00068}00068 \textcolor{comment}{                         * base are unaligned update m}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00069}00069 \textcolor{comment}{                         */}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00070}00070                         tmp = (\textcolor{keywordtype}{unsigned} long)(pfn | p);}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00071}00071                         \textcolor{keywordflow}{if} (!IS\_ALIGNED(tmp, 1 << m))}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00072}00072                                 m = find\_first\_bit(\&tmp, BITS\_PER\_LONG);}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00073}00073 }
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00074}00074                         base = pfn;}
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\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00078}00078                 p += len;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00079}00079                 i += len;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00080}00080         \}}
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\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00083}00083                 m = min\_t(\textcolor{keywordtype}{unsigned} \textcolor{keywordtype}{long}, ilog2(roundup\_pow\_of\_two(i)), m);}
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\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00086}00086                         *order = ilog2(roundup\_pow\_of\_two(i) >> m);}
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\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00088}00088                 *ncont = DIV\_ROUND\_UP(i, (1 << m));}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00089}00089         \} \textcolor{keywordflow}{else} \{}
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\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00093}00093                         *order = 0;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00094}00094 }
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00095}00095                 *ncont = 0;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00096}00096         \}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00097}00097         *shift = PAGE\_SHIFT + m;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00098}00098         *count = i;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00099}00099 \}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00100}00100 }
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00101}00101 \textcolor{preprocessor}{\#ifdef CONFIG\_INFINIBAND\_ON\_DEMAND\_PAGING}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00102}00102 \textcolor{keyword}{static} u64 umem\_dma\_to\_mtt(dma\_addr\_t umem\_dma)}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00103}00103 \{}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00104}00104         u64 mtt\_entry = umem\_dma \& ODP\_DMA\_ADDR\_MASK;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00105}00105 }
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00106}00106         \textcolor{keywordflow}{if} (umem\_dma \& ODP\_READ\_ALLOWED\_BIT)}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00107}00107                 mtt\_entry |= \mbox{\hyperlink{mlx5__ib_8h_aeed3fc60f05362ba4cdd1bb3f2f76ef7a5377f7f50ac597d445884d59aec0f63b}{MLX5\_IB\_MTT\_READ}};}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00108}00108         \textcolor{keywordflow}{if} (umem\_dma \& ODP\_WRITE\_ALLOWED\_BIT)}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00109}00109                 mtt\_entry |= \mbox{\hyperlink{mlx5__ib_8h_aeed3fc60f05362ba4cdd1bb3f2f76ef7ab2a75d1d779a696054498378d5cf7ba4}{MLX5\_IB\_MTT\_WRITE}};}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00110}00110 }
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00111}00111         \textcolor{keywordflow}{return} mtt\_entry;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00112}00112 \}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00113}00113 \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00114}00114 }
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00115}00115 \textcolor{comment}{/*}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00116}00116 \textcolor{comment}{ * Populate the given array with bus addresses from the umem.}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00117}00117 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00118}00118 \textcolor{comment}{ * dev -\/ mlx5\_ib device}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00119}00119 \textcolor{comment}{ * umem -\/ umem to use to fill the pages}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00120}00120 \textcolor{comment}{ * page\_shift -\/ determines the page size used in the resulting array}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00121}00121 \textcolor{comment}{ * offset -\/ offset into the umem to start from,}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00122}00122 \textcolor{comment}{ *          only implemented for ODP umems}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00123}00123 \textcolor{comment}{ * num\_pages -\/ total number of pages to fill}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00124}00124 \textcolor{comment}{ * pas -\/ bus addresses array to fill}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00125}00125 \textcolor{comment}{ * access\_flags -\/ access flags to set on all present pages.}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00126}00126 \textcolor{comment}{                  use enum mlx5\_ib\_mtt\_access\_flags for this.}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00127}00127 \textcolor{comment}{ */}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00128}\mbox{\hyperlink{mlx5__ib_8h_afbe5e36aecf0ca4446f6f7fadc61cc9e}{00128}} \textcolor{keywordtype}{void} \mbox{\hyperlink{mlx5__ib__mem_8c_afbe5e36aecf0ca4446f6f7fadc61cc9e}{\_\_mlx5\_ib\_populate\_pas}}(\textcolor{keyword}{struct} \mbox{\hyperlink{structmlx5__ib__dev}{mlx5\_ib\_dev}} *dev, \textcolor{keyword}{struct} ib\_umem *umem,}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00129}00129                             \textcolor{keywordtype}{int} page\_shift, \textcolor{keywordtype}{size\_t} offset, \textcolor{keywordtype}{size\_t} num\_pages,}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00130}00130                             \_\_be64 *pas, \textcolor{keywordtype}{int} access\_flags)}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00131}00131 \{}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00132}00132         \textcolor{keywordtype}{unsigned} \textcolor{keywordtype}{long} umem\_page\_shift = ilog2(umem-\/>page\_size);}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00133}00133         \textcolor{keywordtype}{int} shift = page\_shift -\/ umem\_page\_shift;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00134}00134         \textcolor{keywordtype}{int} mask = (1 << shift) -\/ 1;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00135}00135         \textcolor{keywordtype}{int} i, k;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00136}00136         u64 cur = 0;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00137}00137         u64 base;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00138}00138         \textcolor{keywordtype}{int} len;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00139}00139         \textcolor{keyword}{struct }scatterlist *sg;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00140}00140         \textcolor{keywordtype}{int} entry;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00141}00141 \textcolor{preprocessor}{\#ifdef CONFIG\_INFINIBAND\_ON\_DEMAND\_PAGING}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00142}00142         \textcolor{keyword}{const} \textcolor{keywordtype}{bool} odp = umem-\/>odp\_data != NULL;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00143}00143 }
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00144}00144         \textcolor{keywordflow}{if} (odp) \{}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00145}00145                 WARN\_ON(shift != 0);}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00146}00146                 WARN\_ON(access\_flags != (\mbox{\hyperlink{mlx5__ib_8h_aeed3fc60f05362ba4cdd1bb3f2f76ef7a5377f7f50ac597d445884d59aec0f63b}{MLX5\_IB\_MTT\_READ}} | \mbox{\hyperlink{mlx5__ib_8h_aeed3fc60f05362ba4cdd1bb3f2f76ef7ab2a75d1d779a696054498378d5cf7ba4}{MLX5\_IB\_MTT\_WRITE}}));}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00147}00147 }
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00148}00148                 \textcolor{keywordflow}{for} (i = 0; i < num\_pages; ++i) \{}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00149}00149                         dma\_addr\_t pa = umem-\/>odp\_data-\/>dma\_list[offset + i];}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00150}00150 }
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00151}00151                         pas[i] = cpu\_to\_be64(umem\_dma\_to\_mtt(pa));}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00152}00152                 \}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00153}00153                 \textcolor{keywordflow}{return};}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00154}00154         \}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00155}00155 \textcolor{preprocessor}{\#endif}}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00156}00156 }
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00157}00157         i = 0;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00158}00158         for\_each\_sg(umem-\/>sg\_head.sgl, sg, umem-\/>nmap, entry) \{}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00159}00159                 len = sg\_dma\_len(sg) >> umem\_page\_shift;}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00160}00160                 base = sg\_dma\_address(sg);}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00161}00161                 \textcolor{keywordflow}{for} (k = 0; k < len; k++) \{}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00162}00162                         \textcolor{keywordflow}{if} (!(i \& mask)) \{}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00163}00163                                 cur = base + (k << umem\_page\_shift);}
\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00164}00164                                 cur |= access\_flags;}
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\DoxyCodeLine{\Hypertarget{mlx5__ib__mem_8c_source_l00166}00166                                 pas[i >> shift] = cpu\_to\_be64(cur);}
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