\hypertarget{trans_8h_source}{}\doxysection{trans.\+h}
\label{trans_8h_source}\index{dev/mlx5/mlx5\_fpga/trans.h@{dev/mlx5/mlx5\_fpga/trans.h}}
\mbox{\hyperlink{trans_8h}{Go to the documentation of this file.}}
\begin{DoxyCode}{0}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00001}00001 \textcolor{comment}{/*-\/}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00002}00002 \textcolor{comment}{ * Copyright (c) 2017 Mellanox Technologies. All rights reserved.}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00003}00003 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00004}00004 \textcolor{comment}{ * This software is available to you under a choice of one of two}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00005}00005 \textcolor{comment}{ * licenses.  You may choose to be licensed under the terms of the GNU}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00006}00006 \textcolor{comment}{ * General Public License (GPL) Version 2, available from the file}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00007}00007 \textcolor{comment}{ * COPYING in the main directory of this source tree, or the}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00008}00008 \textcolor{comment}{ * OpenIB.org BSD license below:}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00009}00009 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00010}00010 \textcolor{comment}{ *     Redistribution and use in source and binary forms, with or}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00011}00011 \textcolor{comment}{ *     without modification, are permitted provided that the following}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00012}00012 \textcolor{comment}{ *     conditions are met:}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00013}00013 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00014}00014 \textcolor{comment}{ *      -\/ Redistributions of source code must retain the above}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00015}00015 \textcolor{comment}{ *        copyright notice, this list of conditions and the following}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00016}00016 \textcolor{comment}{ *        disclaimer.}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00017}00017 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00018}00018 \textcolor{comment}{ *      -\/ Redistributions in binary form must reproduce the above}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00019}00019 \textcolor{comment}{ *        copyright notice, this list of conditions and the following}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00020}00020 \textcolor{comment}{ *        disclaimer in the documentation and/or other materials}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00021}00021 \textcolor{comment}{ *        provided with the distribution.}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00022}00022 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00023}00023 \textcolor{comment}{ * THE SOFTWARE IS PROVIDED "{}AS IS"{}, WITHOUT WARRANTY OF ANY KIND,}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00024}00024 \textcolor{comment}{ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00025}00025 \textcolor{comment}{ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00026}00026 \textcolor{comment}{ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00027}00027 \textcolor{comment}{ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00028}00028 \textcolor{comment}{ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00029}00029 \textcolor{comment}{ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00030}00030 \textcolor{comment}{ * SOFTWARE.}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00031}00031 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00032}00032 \textcolor{comment}{ * \$FreeBSD\$}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00033}00033 \textcolor{comment}{ */}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00034}00034 }
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00035}00035 \textcolor{preprocessor}{\#ifndef \_\_MLX5\_FPGA\_TRANS\_H\_\_}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00036}00036 \textcolor{preprocessor}{\#define \_\_MLX5\_FPGA\_TRANS\_H\_\_}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00037}00037 }
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00038}00038 \textcolor{preprocessor}{\#include <\mbox{\hyperlink{sdk_8h}{dev/mlx5/mlx5\_fpga/sdk.h}}>}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00039}00039 \textcolor{preprocessor}{\#include <\mbox{\hyperlink{core_8h}{dev/mlx5/mlx5\_fpga/core.h}}>}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00040}00040 }
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00041}\mbox{\hyperlink{trans_8h_a554ee58c41defe5b93f9843d48f42365}{00041}} \textcolor{preprocessor}{\#define MLX5\_FPGA\_TRANSACTION\_MAX\_SIZE 1008}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00042}\mbox{\hyperlink{trans_8h_a1b58adbf91b112cc75974ae0672e0729}{00042}} \textcolor{preprocessor}{\#define MLX5\_FPGA\_TRANSACTION\_SEND\_ALIGN\_BITS 3}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00043}\mbox{\hyperlink{trans_8h_a45ca64bf1bbf18bcac41cbcc178018fa}{00043}} \textcolor{preprocessor}{\#define MLX5\_FPGA\_TRANSACTION\_SEND\_PAGE\_BITS 12}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00044}\mbox{\hyperlink{trans_8h_a1afba54e768e37759c00c92a83ee1789}{00044}} \textcolor{preprocessor}{\#define MLX5\_FPGA\_TID\_COUNT 256}}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00045}00045 }
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00046}\mbox{\hyperlink{trans_8h_a2b983dd7631b4ee8d4a7a91be097237a}{00046}} \textcolor{keyword}{enum} \mbox{\hyperlink{trans_8h_a2b983dd7631b4ee8d4a7a91be097237a}{mlx5\_fpga\_direction}} \{}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00047}\mbox{\hyperlink{trans_8h_a2b983dd7631b4ee8d4a7a91be097237aab83cee66a57cd5b46f508a5ae613422c}{00047}}         \mbox{\hyperlink{trans_8h_a2b983dd7631b4ee8d4a7a91be097237aab83cee66a57cd5b46f508a5ae613422c}{MLX5\_FPGA\_READ}},}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00048}\mbox{\hyperlink{trans_8h_a2b983dd7631b4ee8d4a7a91be097237aa1fee16057da5f5057bc0a72b1855999c}{00048}}         \mbox{\hyperlink{trans_8h_a2b983dd7631b4ee8d4a7a91be097237aa1fee16057da5f5057bc0a72b1855999c}{MLX5\_FPGA\_WRITE}},}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00049}00049 \};}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00050}00050 }
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00051}\mbox{\hyperlink{structmlx5__fpga__transaction}{00051}} \textcolor{keyword}{struct }\mbox{\hyperlink{structmlx5__fpga__transaction}{mlx5\_fpga\_transaction}} \{}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00052}\mbox{\hyperlink{structmlx5__fpga__transaction_ae45b280b54e61693ca56125139469750}{00052}}         \textcolor{keyword}{struct }\mbox{\hyperlink{structmlx5__fpga__conn}{mlx5\_fpga\_conn}} *\mbox{\hyperlink{structmlx5__fpga__transaction_ae45b280b54e61693ca56125139469750}{conn}};}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00053}\mbox{\hyperlink{structmlx5__fpga__transaction_ae7d717d89c01b279ea20a67cb6f604c7}{00053}}         \textcolor{keyword}{enum} \mbox{\hyperlink{trans_8h_a2b983dd7631b4ee8d4a7a91be097237a}{mlx5\_fpga\_direction}} \mbox{\hyperlink{structmlx5__fpga__transaction_ae7d717d89c01b279ea20a67cb6f604c7}{direction}};}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00054}\mbox{\hyperlink{structmlx5__fpga__transaction_a2954e84fc376c9210fb5d68f3c1f2f40}{00054}}         \textcolor{keywordtype}{size\_t} \mbox{\hyperlink{structmlx5__fpga__transaction_a2954e84fc376c9210fb5d68f3c1f2f40}{size}};}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00055}\mbox{\hyperlink{structmlx5__fpga__transaction_ab3e14bbae16391d014f78bc54835fdb5}{00055}}         u64 \mbox{\hyperlink{structmlx5__fpga__transaction_ab3e14bbae16391d014f78bc54835fdb5}{addr}};}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00056}\mbox{\hyperlink{structmlx5__fpga__transaction_aef5de6c3f31fc29e146b5fa9c96d6ec3}{00056}}         u8 *\mbox{\hyperlink{structmlx5__fpga__transaction_aef5de6c3f31fc29e146b5fa9c96d6ec3}{data}};}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00057}\mbox{\hyperlink{structmlx5__fpga__transaction_afb23da20b5ec2089fd89254202850e80}{00057}}         void (*\mbox{\hyperlink{structmlx5__fpga__transaction_afb23da20b5ec2089fd89254202850e80}{complete1}})(\textcolor{keyword}{const} \textcolor{keyword}{struct }\mbox{\hyperlink{structmlx5__fpga__transaction}{mlx5\_fpga\_transaction}} *complete,}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00058}00058                          u8 status);}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00059}00059 \};}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00060}00060 }
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00061}00061 \textcolor{keywordtype}{int} \mbox{\hyperlink{trans_8h_ae13a014b26163a451655dc60d864aeb4}{mlx5\_fpga\_trans\_device\_init}}(\textcolor{keyword}{struct} mlx5\_fpga\_device *fdev);}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00062}00062 \textcolor{keywordtype}{void} \mbox{\hyperlink{trans_8h_ad684faeee8b96af775d6082d8ed779fc}{mlx5\_fpga\_trans\_device\_cleanup}}(\textcolor{keyword}{struct} mlx5\_fpga\_device *fdev);}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00063}00063 \textcolor{keywordtype}{int} \mbox{\hyperlink{trans_8h_a5ab19e75b9ee247a0e1edf9878a61aad}{mlx5\_fpga\_trans\_exec}}(\textcolor{keyword}{const} \textcolor{keyword}{struct} \mbox{\hyperlink{structmlx5__fpga__transaction}{mlx5\_fpga\_transaction}} *trans);}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00064}00064 \textcolor{keywordtype}{void} \mbox{\hyperlink{trans_8h_a51ec92711d42a593954be18f06275d3a}{mlx5\_fpga\_trans\_recv}}(\textcolor{keywordtype}{void} *cb\_arg, \textcolor{keyword}{struct} \mbox{\hyperlink{structmlx5__fpga__dma__buf}{mlx5\_fpga\_dma\_buf}} *buf);}
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00065}00065 }
\DoxyCodeLine{\Hypertarget{trans_8h_source_l00066}00066 \textcolor{preprocessor}{\#endif }\textcolor{comment}{/* \_\_MLX\_FPGA\_TRANS\_H\_\_ */}\textcolor{preprocessor}{}}

\end{DoxyCode}
