\hypertarget{trans_8h}{}\doxysection{dev/mlx5/mlx5\+\_\+fpga/trans.h File Reference}
\label{trans_8h}\index{dev/mlx5/mlx5\_fpga/trans.h@{dev/mlx5/mlx5\_fpga/trans.h}}
{\ttfamily \#include $<$dev/mlx5/mlx5\+\_\+fpga/sdk.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/mlx5\+\_\+fpga/core.\+h$>$}\newline
Include dependency graph for trans.\+h\+:
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\begin{center}
\leavevmode
\includegraphics[width=350pt]{d6/dfe/trans_8h__incl}
\end{center}
\end{figure}
This graph shows which files directly or indirectly include this file\+:
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\begin{center}
\leavevmode
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\doxysubsection*{Data Structures}
\begin{DoxyCompactItemize}
\item 
struct \mbox{\hyperlink{structmlx5__fpga__transaction}{mlx5\+\_\+fpga\+\_\+transaction}}
\end{DoxyCompactItemize}
\doxysubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{trans_8h_a554ee58c41defe5b93f9843d48f42365}{MLX5\+\_\+\+FPGA\+\_\+\+TRANSACTION\+\_\+\+MAX\+\_\+\+SIZE}}~1008
\item 
\#define \mbox{\hyperlink{trans_8h_a1b58adbf91b112cc75974ae0672e0729}{MLX5\+\_\+\+FPGA\+\_\+\+TRANSACTION\+\_\+\+SEND\+\_\+\+ALIGN\+\_\+\+BITS}}~3
\item 
\#define \mbox{\hyperlink{trans_8h_a45ca64bf1bbf18bcac41cbcc178018fa}{MLX5\+\_\+\+FPGA\+\_\+\+TRANSACTION\+\_\+\+SEND\+\_\+\+PAGE\+\_\+\+BITS}}~12
\item 
\#define \mbox{\hyperlink{trans_8h_a1afba54e768e37759c00c92a83ee1789}{MLX5\+\_\+\+FPGA\+\_\+\+TID\+\_\+\+COUNT}}~256
\end{DoxyCompactItemize}
\doxysubsection*{Enumerations}
\begin{DoxyCompactItemize}
\item 
enum \mbox{\hyperlink{trans_8h_a2b983dd7631b4ee8d4a7a91be097237a}{mlx5\+\_\+fpga\+\_\+direction}} \{ \mbox{\hyperlink{trans_8h_a2b983dd7631b4ee8d4a7a91be097237aab83cee66a57cd5b46f508a5ae613422c}{MLX5\+\_\+\+FPGA\+\_\+\+READ}}
, \mbox{\hyperlink{trans_8h_a2b983dd7631b4ee8d4a7a91be097237aa1fee16057da5f5057bc0a72b1855999c}{MLX5\+\_\+\+FPGA\+\_\+\+WRITE}}
 \}
\end{DoxyCompactItemize}
\doxysubsection*{Functions}
\begin{DoxyCompactItemize}
\item 
int \mbox{\hyperlink{trans_8h_ae13a014b26163a451655dc60d864aeb4}{mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+init}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev)
\item 
void \mbox{\hyperlink{trans_8h_ad684faeee8b96af775d6082d8ed779fc}{mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+cleanup}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev)
\item 
int \mbox{\hyperlink{trans_8h_a5ab19e75b9ee247a0e1edf9878a61aad}{mlx5\+\_\+fpga\+\_\+trans\+\_\+exec}} (const struct \mbox{\hyperlink{structmlx5__fpga__transaction}{mlx5\+\_\+fpga\+\_\+transaction}} $\ast$trans)
\item 
void \mbox{\hyperlink{trans_8h_a51ec92711d42a593954be18f06275d3a}{mlx5\+\_\+fpga\+\_\+trans\+\_\+recv}} (void $\ast$cb\+\_\+arg, struct \mbox{\hyperlink{structmlx5__fpga__dma__buf}{mlx5\+\_\+fpga\+\_\+dma\+\_\+buf}} $\ast$buf)
\end{DoxyCompactItemize}


\doxysubsection{Macro Definition Documentation}
\mbox{\Hypertarget{trans_8h_a1afba54e768e37759c00c92a83ee1789}\label{trans_8h_a1afba54e768e37759c00c92a83ee1789}} 
\index{trans.h@{trans.h}!MLX5\_FPGA\_TID\_COUNT@{MLX5\_FPGA\_TID\_COUNT}}
\index{MLX5\_FPGA\_TID\_COUNT@{MLX5\_FPGA\_TID\_COUNT}!trans.h@{trans.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_TID\_COUNT}{MLX5\_FPGA\_TID\_COUNT}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+TID\+\_\+\+COUNT~256}



Definition at line \mbox{\hyperlink{trans_8h_source_l00044}{44}} of file \mbox{\hyperlink{trans_8h_source}{trans.\+h}}.

\mbox{\Hypertarget{trans_8h_a554ee58c41defe5b93f9843d48f42365}\label{trans_8h_a554ee58c41defe5b93f9843d48f42365}} 
\index{trans.h@{trans.h}!MLX5\_FPGA\_TRANSACTION\_MAX\_SIZE@{MLX5\_FPGA\_TRANSACTION\_MAX\_SIZE}}
\index{MLX5\_FPGA\_TRANSACTION\_MAX\_SIZE@{MLX5\_FPGA\_TRANSACTION\_MAX\_SIZE}!trans.h@{trans.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_TRANSACTION\_MAX\_SIZE}{MLX5\_FPGA\_TRANSACTION\_MAX\_SIZE}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+TRANSACTION\+\_\+\+MAX\+\_\+\+SIZE~1008}



Definition at line \mbox{\hyperlink{trans_8h_source_l00041}{41}} of file \mbox{\hyperlink{trans_8h_source}{trans.\+h}}.

\mbox{\Hypertarget{trans_8h_a1b58adbf91b112cc75974ae0672e0729}\label{trans_8h_a1b58adbf91b112cc75974ae0672e0729}} 
\index{trans.h@{trans.h}!MLX5\_FPGA\_TRANSACTION\_SEND\_ALIGN\_BITS@{MLX5\_FPGA\_TRANSACTION\_SEND\_ALIGN\_BITS}}
\index{MLX5\_FPGA\_TRANSACTION\_SEND\_ALIGN\_BITS@{MLX5\_FPGA\_TRANSACTION\_SEND\_ALIGN\_BITS}!trans.h@{trans.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_TRANSACTION\_SEND\_ALIGN\_BITS}{MLX5\_FPGA\_TRANSACTION\_SEND\_ALIGN\_BITS}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+TRANSACTION\+\_\+\+SEND\+\_\+\+ALIGN\+\_\+\+BITS~3}



Definition at line \mbox{\hyperlink{trans_8h_source_l00042}{42}} of file \mbox{\hyperlink{trans_8h_source}{trans.\+h}}.

\mbox{\Hypertarget{trans_8h_a45ca64bf1bbf18bcac41cbcc178018fa}\label{trans_8h_a45ca64bf1bbf18bcac41cbcc178018fa}} 
\index{trans.h@{trans.h}!MLX5\_FPGA\_TRANSACTION\_SEND\_PAGE\_BITS@{MLX5\_FPGA\_TRANSACTION\_SEND\_PAGE\_BITS}}
\index{MLX5\_FPGA\_TRANSACTION\_SEND\_PAGE\_BITS@{MLX5\_FPGA\_TRANSACTION\_SEND\_PAGE\_BITS}!trans.h@{trans.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_TRANSACTION\_SEND\_PAGE\_BITS}{MLX5\_FPGA\_TRANSACTION\_SEND\_PAGE\_BITS}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+TRANSACTION\+\_\+\+SEND\+\_\+\+PAGE\+\_\+\+BITS~12}



Definition at line \mbox{\hyperlink{trans_8h_source_l00043}{43}} of file \mbox{\hyperlink{trans_8h_source}{trans.\+h}}.



\doxysubsection{Enumeration Type Documentation}
\mbox{\Hypertarget{trans_8h_a2b983dd7631b4ee8d4a7a91be097237a}\label{trans_8h_a2b983dd7631b4ee8d4a7a91be097237a}} 
\index{trans.h@{trans.h}!mlx5\_fpga\_direction@{mlx5\_fpga\_direction}}
\index{mlx5\_fpga\_direction@{mlx5\_fpga\_direction}!trans.h@{trans.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_direction}{mlx5\_fpga\_direction}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{trans_8h_a2b983dd7631b4ee8d4a7a91be097237a}{mlx5\+\_\+fpga\+\_\+direction}}}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_READ@{MLX5\_FPGA\_READ}!trans.h@{trans.h}}\index{trans.h@{trans.h}!MLX5\_FPGA\_READ@{MLX5\_FPGA\_READ}}}\mbox{\Hypertarget{trans_8h_a2b983dd7631b4ee8d4a7a91be097237aab83cee66a57cd5b46f508a5ae613422c}\label{trans_8h_a2b983dd7631b4ee8d4a7a91be097237aab83cee66a57cd5b46f508a5ae613422c}} 
MLX5\+\_\+\+FPGA\+\_\+\+READ&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_WRITE@{MLX5\_FPGA\_WRITE}!trans.h@{trans.h}}\index{trans.h@{trans.h}!MLX5\_FPGA\_WRITE@{MLX5\_FPGA\_WRITE}}}\mbox{\Hypertarget{trans_8h_a2b983dd7631b4ee8d4a7a91be097237aa1fee16057da5f5057bc0a72b1855999c}\label{trans_8h_a2b983dd7631b4ee8d4a7a91be097237aa1fee16057da5f5057bc0a72b1855999c}} 
MLX5\+\_\+\+FPGA\+\_\+\+WRITE&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{trans_8h_source_l00046}{46}} of file \mbox{\hyperlink{trans_8h_source}{trans.\+h}}.



\doxysubsection{Function Documentation}
\mbox{\Hypertarget{trans_8h_ad684faeee8b96af775d6082d8ed779fc}\label{trans_8h_ad684faeee8b96af775d6082d8ed779fc}} 
\index{trans.h@{trans.h}!mlx5\_fpga\_trans\_device\_cleanup@{mlx5\_fpga\_trans\_device\_cleanup}}
\index{mlx5\_fpga\_trans\_device\_cleanup@{mlx5\_fpga\_trans\_device\_cleanup}!trans.h@{trans.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_trans\_device\_cleanup()}{mlx5\_fpga\_trans\_device\_cleanup()}}
{\footnotesize\ttfamily void mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+cleanup (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00332}{332}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00206}{mlx5\+\_\+fpga\+\_\+device\+\_\+start()}}, and \mbox{\hyperlink{mlx5fpga__core_8c_source_l00361}{mlx5\+\_\+fpga\+\_\+device\+\_\+stop()}}.

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\mbox{\Hypertarget{trans_8h_ae13a014b26163a451655dc60d864aeb4}\label{trans_8h_ae13a014b26163a451655dc60d864aeb4}} 
\index{trans.h@{trans.h}!mlx5\_fpga\_trans\_device\_init@{mlx5\_fpga\_trans\_device\_init}}
\index{mlx5\_fpga\_trans\_device\_init@{mlx5\_fpga\_trans\_device\_init}!trans.h@{trans.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_trans\_device\_init()}{mlx5\_fpga\_trans\_device\_init()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+init (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00308}{308}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



References \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00047}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::tid}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00206}{mlx5\+\_\+fpga\+\_\+device\+\_\+start()}}.

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\mbox{\Hypertarget{trans_8h_a5ab19e75b9ee247a0e1edf9878a61aad}\label{trans_8h_a5ab19e75b9ee247a0e1edf9878a61aad}} 
\index{trans.h@{trans.h}!mlx5\_fpga\_trans\_exec@{mlx5\_fpga\_trans\_exec}}
\index{mlx5\_fpga\_trans\_exec@{mlx5\_fpga\_trans\_exec}!trans.h@{trans.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_trans\_exec()}{mlx5\_fpga\_trans\_exec()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+trans\+\_\+exec (\begin{DoxyParamCaption}\item[{const struct \mbox{\hyperlink{structmlx5__fpga__transaction}{mlx5\+\_\+fpga\+\_\+transaction}} $\ast$}]{trans }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00184}{184}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



References \mbox{\hyperlink{trans_8h_source_l00055}{mlx5\+\_\+fpga\+\_\+transaction\+::addr}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00071}{alloc\+\_\+tid()}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00051}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::buf}}, \mbox{\hyperlink{sdk_8h_source_l00126}{mlx5\+\_\+fpga\+\_\+dma\+\_\+buf\+::complete}}, \mbox{\hyperlink{trans_8h_source_l00057}{mlx5\+\_\+fpga\+\_\+transaction\+::complete1}}, \mbox{\hyperlink{trans_8h_source_l00052}{mlx5\+\_\+fpga\+\_\+transaction\+::conn}}, \mbox{\hyperlink{sdk_8h_source_l00101}{mlx5\+\_\+fpga\+\_\+dma\+\_\+entry\+::data}}, \mbox{\hyperlink{trans_8h_source_l00056}{mlx5\+\_\+fpga\+\_\+transaction\+::data}}, \mbox{\hyperlink{trans_8h_source_l00053}{mlx5\+\_\+fpga\+\_\+transaction\+::direction}}, \mbox{\hyperlink{conn_8h_source_l00046}{mlx5\+\_\+fpga\+\_\+conn\+::fdev}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00094}{free\+\_\+tid()}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00050}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::header}}, \mbox{\hyperlink{mlx5fpga__conn_8c_source_l00175}{mlx5\+\_\+fpga\+\_\+conn\+\_\+send()}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00465}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+READ}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00466}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+WRITE}}, \mbox{\hyperlink{trans_8h_source_l00048}{MLX5\+\_\+\+FPGA\+\_\+\+WRITE}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, \mbox{\hyperlink{device_8h_source_l00106}{MLX5\+\_\+\+SET64}}, \mbox{\hyperlink{sdk_8h_source_l00116}{mlx5\+\_\+fpga\+\_\+dma\+\_\+buf\+::sg}}, \mbox{\hyperlink{sdk_8h_source_l00103}{mlx5\+\_\+fpga\+\_\+dma\+\_\+entry\+::size}}, \mbox{\hyperlink{trans_8h_source_l00054}{mlx5\+\_\+fpga\+\_\+transaction\+::size}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00048}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::state}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00047}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::tid}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00125}{trans\+\_\+send\+\_\+complete()}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00040}{TRANS\+\_\+\+STATE\+\_\+\+SEND}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00146}{trans\+\_\+validate()}}, and \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00046}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::user\+\_\+trans}}.



Referenced by \mbox{\hyperlink{mlx5fpga__xfer_8c_source_l00071}{exec\+\_\+more()}}.

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\mbox{\Hypertarget{trans_8h_a51ec92711d42a593954be18f06275d3a}\label{trans_8h_a51ec92711d42a593954be18f06275d3a}} 
\index{trans.h@{trans.h}!mlx5\_fpga\_trans\_recv@{mlx5\_fpga\_trans\_recv}}
\index{mlx5\_fpga\_trans\_recv@{mlx5\_fpga\_trans\_recv}!trans.h@{trans.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_trans\_recv()}{mlx5\_fpga\_trans\_recv()}}
{\footnotesize\ttfamily void mlx5\+\_\+fpga\+\_\+trans\+\_\+recv (\begin{DoxyParamCaption}\item[{void $\ast$}]{cb\+\_\+arg,  }\item[{struct \mbox{\hyperlink{structmlx5__fpga__dma__buf}{mlx5\+\_\+fpga\+\_\+dma\+\_\+buf}} $\ast$}]{buf }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00245}{245}} of file \mbox{\hyperlink{mlx5fpga__trans_8c_source}{mlx5fpga\+\_\+trans.\+c}}.



References \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00051}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::buf}}, \mbox{\hyperlink{mlx5__en__tx_8c_source_l00001}{data}}, \mbox{\hyperlink{sdk_8h_source_l00101}{mlx5\+\_\+fpga\+\_\+dma\+\_\+entry\+::data}}, \mbox{\hyperlink{trans_8h_source_l00056}{mlx5\+\_\+fpga\+\_\+transaction\+::data}}, \mbox{\hyperlink{trans_8h_source_l00053}{mlx5\+\_\+fpga\+\_\+transaction\+::direction}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00061}{find\+\_\+tid()}}, \mbox{\hyperlink{device_8h_source_l00070}{MLX5\+\_\+\+ADDR\+\_\+\+OF}}, \mbox{\hyperlink{trans_8h_source_l00047}{MLX5\+\_\+\+FPGA\+\_\+\+READ}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00467}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+READ\+\_\+\+RESPONSE}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00468}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+WRITE\+\_\+\+RESPONSE}}, \mbox{\hyperlink{trans_8h_source_l00048}{MLX5\+\_\+\+FPGA\+\_\+\+WRITE}}, \mbox{\hyperlink{device_8h_source_l00091}{MLX5\+\_\+\+GET}}, \mbox{\hyperlink{device_8h_source_l00064}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+BYTES}}, \mbox{\hyperlink{sdk_8h_source_l00116}{mlx5\+\_\+fpga\+\_\+dma\+\_\+buf\+::sg}}, \mbox{\hyperlink{sdk_8h_source_l00103}{mlx5\+\_\+fpga\+\_\+dma\+\_\+entry\+::size}}, \mbox{\hyperlink{trans_8h_source_l00054}{mlx5\+\_\+fpga\+\_\+transaction\+::size}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00049}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::status}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00047}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::tid}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00104}{trans\+\_\+complete()}}, and \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00046}{mlx5\+\_\+fpga\+\_\+trans\+\_\+priv\+::user\+\_\+trans}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00206}{mlx5\+\_\+fpga\+\_\+device\+\_\+start()}}.

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