\hypertarget{mlx5__ifc__fpga_8h}{}\doxysection{dev/mlx5/mlx5\+\_\+fpga/mlx5\+\_\+ifc\+\_\+fpga.h File Reference}
\label{mlx5__ifc__fpga_8h}\index{dev/mlx5/mlx5\_fpga/mlx5\_ifc\_fpga.h@{dev/mlx5/mlx5\_fpga/mlx5\_ifc\_fpga.h}}
This graph shows which files directly or indirectly include this file\+:
\nopagebreak
\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=350pt]{d0/de7/mlx5__ifc__fpga_8h__dep__incl}
\end{center}
\end{figure}
\doxysubsection*{Data Structures}
\begin{DoxyCompactItemize}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__shell__caps__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+shell\+\_\+caps\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__cap__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+cap\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__ctrl__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+ctrl\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__error__event__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+error\+\_\+event\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__access__reg__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+access\+\_\+reg\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__qpc__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+qpc\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__create__qp__in__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+create\+\_\+qp\+\_\+in\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__create__qp__out__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+create\+\_\+qp\+\_\+out\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__modify__qp__in__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+modify\+\_\+qp\+\_\+in\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__modify__qp__out__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+modify\+\_\+qp\+\_\+out\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__query__qp__in__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+query\+\_\+qp\+\_\+in\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__query__qp__out__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+query\+\_\+qp\+\_\+out\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__query__qp__counters__in__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+query\+\_\+qp\+\_\+counters\+\_\+in\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__query__qp__counters__out__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+query\+\_\+qp\+\_\+counters\+\_\+out\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__destroy__qp__in__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+destroy\+\_\+qp\+\_\+in\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__destroy__qp__out__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+destroy\+\_\+qp\+\_\+out\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__ipsec__extended__cap__bits}{mlx5\+\_\+ifc\+\_\+ipsec\+\_\+extended\+\_\+cap\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__ipsec__counters__bits}{mlx5\+\_\+ifc\+\_\+ipsec\+\_\+counters\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__shell__counters__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+shell\+\_\+counters\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__shell__qp__packet__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+shell\+\_\+qp\+\_\+packet\+\_\+bits}}
\item 
struct \mbox{\hyperlink{structmlx5__ifc__fpga__qp__error__event__bits}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+qp\+\_\+error\+\_\+event\+\_\+bits}}
\end{DoxyCompactItemize}
\doxysubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{mlx5__ifc__fpga_8h_a34cb2a3f683c647504e211ac762c4015}{MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+REG\+\_\+\+SIZE\+\_\+\+MAX}}~64
\end{DoxyCompactItemize}
\doxysubsection*{Enumerations}
\begin{DoxyCompactItemize}
\item 
enum \{ \mbox{\hyperlink{mlx5__ifc__fpga_8h_a52864abcf6ebd8d120995b36fe6ce06ea1148bf44292ecba6f2793381b5e36eb8}{MLX5\+\_\+\+FPGA\+\_\+\+CAP\+\_\+\+SANDBOX\+\_\+\+VENDOR\+\_\+\+ID\+\_\+\+MLNX}} = 0x2c9
 \}
\item 
enum \{ \mbox{\hyperlink{mlx5__ifc__fpga_8h_a4d29ca5db06e2ae647d1ec22548a9d2aa7408bc97676552704040d159f9d30534}{MLX5\+\_\+\+FPGA\+\_\+\+CAP\+\_\+\+SANDBOX\+\_\+\+PRODUCT\+\_\+\+ID\+\_\+\+EXAMPLE}} = 0x1
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_a4d29ca5db06e2ae647d1ec22548a9d2aa818877d54ae8fc769a77a1d1bfe70245}{MLX5\+\_\+\+FPGA\+\_\+\+CAP\+\_\+\+SANDBOX\+\_\+\+PRODUCT\+\_\+\+ID\+\_\+\+IPSEC}} = 0x2
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_a4d29ca5db06e2ae647d1ec22548a9d2aa899725a79a3f09d05b9128b5a376b71e}{MLX5\+\_\+\+FPGA\+\_\+\+CAP\+\_\+\+SANDBOX\+\_\+\+PRODUCT\+\_\+\+ID\+\_\+\+TLS}} = 0x3
 \}
\item 
enum \{ \mbox{\hyperlink{mlx5__ifc__fpga_8h_a592aba11ab30da4dbf57e9736c8387a1a41bb4c0b1880142a25f5ac4832b6d068}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+CAPS\+\_\+\+QP\+\_\+\+TYPE\+\_\+\+SHELL\+\_\+\+QP}} = 0x1
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_a592aba11ab30da4dbf57e9736c8387a1a779fb80178a35c40f81dcc5a2b3ad714}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+CAPS\+\_\+\+QP\+\_\+\+TYPE\+\_\+\+SANDBOX\+\_\+\+QP}} = 0x2
 \}
\item 
enum \{ \newline
\mbox{\hyperlink{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a6d3735ca4e22b6f07414dea5f711d1eb}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+LOAD}} = 0x1
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a630c4b0786e2b1a5165edb8782a97c8f}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+RESET}} = 0x2
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a776b2f7f1cc9f463de071c6e290f2baa}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+FLASH\+\_\+\+SELECT}} = 0x3
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a7825fc67041d9b907184fe5999371380}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+SANDBOX\+\_\+\+BYPASS\+\_\+\+ON}} = 0x4
, \newline
\mbox{\hyperlink{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748abd139c9a4aa00b85cca99594b9553e82}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+SANDBOX\+\_\+\+BYPASS\+\_\+\+OFF}} = 0x5
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748af596b727f39e977817208937bfa442a4}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+RESET\+\_\+\+SANDBOX}} = 0x6
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748aed7961256cb53e2a0d7d9dfb02aaedb0}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+DISCONNECT}} = 0x9
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748afac2d25cdccd9916bc430de3e04caf86}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+CONNECT}} = 0xA
, \newline
\mbox{\hyperlink{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a72e92d75b90775fad68995b6568a221f}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+RELOAD}} = 0xB
 \}
\item 
enum \{ \newline
\mbox{\hyperlink{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a244be7aea57ce4f7165b8cfec2cbd02f}{MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+CORRUPTED\+\_\+\+DDR}} = 0x1
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a79d5fb99dbe4a3aacfd96a14099df1d2}{MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+FLASH\+\_\+\+TIMEOUT}} = 0x2
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5aef5516e0a8e526f8f6fd7e5295af0134}{MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+INTERNAL\+\_\+\+LINK\+\_\+\+ERROR}} = 0x3
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a7cd6e9f498de17723459b761288aba7b}{MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+WATCHDOG\+\_\+\+FAILURE}} = 0x4
, \newline
\mbox{\hyperlink{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a586275d6c948ceb82cbc5c48808c1470}{MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+I2\+C\+\_\+\+FAILURE}} = 0x5
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a079068aa9bc6aae31a67bd325fdb30ef}{MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+IMAGE\+\_\+\+CHANGED}} = 0x6
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a2ed571e524c329b1b213783d4dc1ba05}{MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+TEMPERATURE\+\_\+\+CRITICAL}} = 0x7
 \}
\item 
enum \mbox{\hyperlink{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+qp\+\_\+state}} \{ \mbox{\hyperlink{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5a3568e0131117a62b4774e102c878b556}{MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+STATE\+\_\+\+INIT}} = 0x0
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5a947e9f28f30867f89573911006fb96e3}{MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+STATE\+\_\+\+ACTIVE}} = 0x1
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5ad1ebc1ae39205b05f73c9c0677516186}{MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+STATE\+\_\+\+ERROR}} = 0x2
 \}
\item 
enum \mbox{\hyperlink{mlx5__ifc__fpga_8h_a58f3b94a7634bd57550c109f15980f86}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+qp\+\_\+type}} \{ \mbox{\hyperlink{mlx5__ifc__fpga_8h_a58f3b94a7634bd57550c109f15980f86a6ada2db13d57e5ecf2d98e32e74ec903}{MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+QP\+\_\+\+TYPE\+\_\+\+SHELL\+\_\+\+QP}} = 0x0
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_a58f3b94a7634bd57550c109f15980f86a3bb0d594693ba4ebc1cc95c4ebb4ff04}{MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+QP\+\_\+\+TYPE\+\_\+\+SANDBOX\+\_\+\+QP}} = 0x1
 \}
\item 
enum \mbox{\hyperlink{mlx5__ifc__fpga_8h_a4b8c34a63f5369ac3d1ad60cb4282f27}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+qp\+\_\+service\+\_\+type}} \{ \mbox{\hyperlink{mlx5__ifc__fpga_8h_a4b8c34a63f5369ac3d1ad60cb4282f27a22390e7745f50db45494a4b8c9bdfbd9}{MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+ST\+\_\+\+RC}} = 0x0
 \}
\item 
enum \{ \mbox{\hyperlink{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8dea8a2e4bd44a0dfba8d264b5e4cac4ac1f}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+READ}} = 0x0
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8dea73371cf6a9ca46fbe072379d8be402b9}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+WRITE}} = 0x1
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8dea93f2bb2553028b86e2b7c672dbd01cd9}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+READ\+\_\+\+RESPONSE}} = 0x2
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8dea3d6d54f5cffaf74d153d9f202a90596a}{MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+WRITE\+\_\+\+RESPONSE}} = 0x3
 \}
\item 
enum \{ \mbox{\hyperlink{mlx5__ifc__fpga_8h_aaa91b962ffd8aca2f3c24e886a222419aab86bd93d5b8fb12a199401c7d03ef27}{MLX5\+\_\+\+FPGA\+\_\+\+QP\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+RETRY\+\_\+\+COUNTER\+\_\+\+EXPIRED}} = 0x1
, \mbox{\hyperlink{mlx5__ifc__fpga_8h_aaa91b962ffd8aca2f3c24e886a222419a4de7c7b538e72de955a76a8b53de8e65}{MLX5\+\_\+\+FPGA\+\_\+\+QP\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+RNR\+\_\+\+EXPIRED}} = 0x2
 \}
\end{DoxyCompactItemize}


\doxysubsection{Macro Definition Documentation}
\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a34cb2a3f683c647504e211ac762c4015}\label{mlx5__ifc__fpga_8h_a34cb2a3f683c647504e211ac762c4015}} 
\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_ACCESS\_REG\_SIZE\_MAX@{MLX5\_FPGA\_ACCESS\_REG\_SIZE\_MAX}}
\index{MLX5\_FPGA\_ACCESS\_REG\_SIZE\_MAX@{MLX5\_FPGA\_ACCESS\_REG\_SIZE\_MAX}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_ACCESS\_REG\_SIZE\_MAX}{MLX5\_FPGA\_ACCESS\_REG\_SIZE\_MAX}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+REG\+\_\+\+SIZE\+\_\+\+MAX~64}



Definition at line \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00174}{174}} of file \mbox{\hyperlink{mlx5__ifc__fpga_8h_source}{mlx5\+\_\+ifc\+\_\+fpga.\+h}}.



\doxysubsection{Enumeration Type Documentation}
\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a52864abcf6ebd8d120995b36fe6ce06e}\label{mlx5__ifc__fpga_8h_a52864abcf6ebd8d120995b36fe6ce06e}} 
\doxysubsubsection{\texorpdfstring{anonymous enum}{anonymous enum}}
{\footnotesize\ttfamily anonymous enum}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CAP\_SANDBOX\_VENDOR\_ID\_MLNX@{MLX5\_FPGA\_CAP\_SANDBOX\_VENDOR\_ID\_MLNX}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CAP\_SANDBOX\_VENDOR\_ID\_MLNX@{MLX5\_FPGA\_CAP\_SANDBOX\_VENDOR\_ID\_MLNX}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a52864abcf6ebd8d120995b36fe6ce06ea1148bf44292ecba6f2793381b5e36eb8}\label{mlx5__ifc__fpga_8h_a52864abcf6ebd8d120995b36fe6ce06ea1148bf44292ecba6f2793381b5e36eb8}} 
MLX5\+\_\+\+FPGA\+\_\+\+CAP\+\_\+\+SANDBOX\+\_\+\+VENDOR\+\_\+\+ID\+\_\+\+MLNX&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00038}{38}} of file \mbox{\hyperlink{mlx5__ifc__fpga_8h_source}{mlx5\+\_\+ifc\+\_\+fpga.\+h}}.

\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a4d29ca5db06e2ae647d1ec22548a9d2a}\label{mlx5__ifc__fpga_8h_a4d29ca5db06e2ae647d1ec22548a9d2a}} 
\doxysubsubsection{\texorpdfstring{anonymous enum}{anonymous enum}}
{\footnotesize\ttfamily anonymous enum}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CAP\_SANDBOX\_PRODUCT\_ID\_EXAMPLE@{MLX5\_FPGA\_CAP\_SANDBOX\_PRODUCT\_ID\_EXAMPLE}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CAP\_SANDBOX\_PRODUCT\_ID\_EXAMPLE@{MLX5\_FPGA\_CAP\_SANDBOX\_PRODUCT\_ID\_EXAMPLE}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a4d29ca5db06e2ae647d1ec22548a9d2aa7408bc97676552704040d159f9d30534}\label{mlx5__ifc__fpga_8h_a4d29ca5db06e2ae647d1ec22548a9d2aa7408bc97676552704040d159f9d30534}} 
MLX5\+\_\+\+FPGA\+\_\+\+CAP\+\_\+\+SANDBOX\+\_\+\+PRODUCT\+\_\+\+ID\+\_\+\+EXAMPLE&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CAP\_SANDBOX\_PRODUCT\_ID\_IPSEC@{MLX5\_FPGA\_CAP\_SANDBOX\_PRODUCT\_ID\_IPSEC}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CAP\_SANDBOX\_PRODUCT\_ID\_IPSEC@{MLX5\_FPGA\_CAP\_SANDBOX\_PRODUCT\_ID\_IPSEC}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a4d29ca5db06e2ae647d1ec22548a9d2aa818877d54ae8fc769a77a1d1bfe70245}\label{mlx5__ifc__fpga_8h_a4d29ca5db06e2ae647d1ec22548a9d2aa818877d54ae8fc769a77a1d1bfe70245}} 
MLX5\+\_\+\+FPGA\+\_\+\+CAP\+\_\+\+SANDBOX\+\_\+\+PRODUCT\+\_\+\+ID\+\_\+\+IPSEC&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CAP\_SANDBOX\_PRODUCT\_ID\_TLS@{MLX5\_FPGA\_CAP\_SANDBOX\_PRODUCT\_ID\_TLS}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CAP\_SANDBOX\_PRODUCT\_ID\_TLS@{MLX5\_FPGA\_CAP\_SANDBOX\_PRODUCT\_ID\_TLS}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a4d29ca5db06e2ae647d1ec22548a9d2aa899725a79a3f09d05b9128b5a376b71e}\label{mlx5__ifc__fpga_8h_a4d29ca5db06e2ae647d1ec22548a9d2aa899725a79a3f09d05b9128b5a376b71e}} 
MLX5\+\_\+\+FPGA\+\_\+\+CAP\+\_\+\+SANDBOX\+\_\+\+PRODUCT\+\_\+\+ID\+\_\+\+TLS&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00042}{42}} of file \mbox{\hyperlink{mlx5__ifc__fpga_8h_source}{mlx5\+\_\+ifc\+\_\+fpga.\+h}}.

\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a592aba11ab30da4dbf57e9736c8387a1}\label{mlx5__ifc__fpga_8h_a592aba11ab30da4dbf57e9736c8387a1}} 
\doxysubsubsection{\texorpdfstring{anonymous enum}{anonymous enum}}
{\footnotesize\ttfamily anonymous enum}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_SHELL\_CAPS\_QP\_TYPE\_SHELL\_QP@{MLX5\_FPGA\_SHELL\_CAPS\_QP\_TYPE\_SHELL\_QP}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_SHELL\_CAPS\_QP\_TYPE\_SHELL\_QP@{MLX5\_FPGA\_SHELL\_CAPS\_QP\_TYPE\_SHELL\_QP}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a592aba11ab30da4dbf57e9736c8387a1a41bb4c0b1880142a25f5ac4832b6d068}\label{mlx5__ifc__fpga_8h_a592aba11ab30da4dbf57e9736c8387a1a41bb4c0b1880142a25f5ac4832b6d068}} 
MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+CAPS\+\_\+\+QP\+\_\+\+TYPE\+\_\+\+SHELL\+\_\+\+QP&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_SHELL\_CAPS\_QP\_TYPE\_SANDBOX\_QP@{MLX5\_FPGA\_SHELL\_CAPS\_QP\_TYPE\_SANDBOX\_QP}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_SHELL\_CAPS\_QP\_TYPE\_SANDBOX\_QP@{MLX5\_FPGA\_SHELL\_CAPS\_QP\_TYPE\_SANDBOX\_QP}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a592aba11ab30da4dbf57e9736c8387a1a779fb80178a35c40f81dcc5a2b3ad714}\label{mlx5__ifc__fpga_8h_a592aba11ab30da4dbf57e9736c8387a1a779fb80178a35c40f81dcc5a2b3ad714}} 
MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+CAPS\+\_\+\+QP\+\_\+\+TYPE\+\_\+\+SANDBOX\+\_\+\+QP&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00048}{48}} of file \mbox{\hyperlink{mlx5__ifc__fpga_8h_source}{mlx5\+\_\+ifc\+\_\+fpga.\+h}}.

\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748}\label{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748}} 
\doxysubsubsection{\texorpdfstring{anonymous enum}{anonymous enum}}
{\footnotesize\ttfamily anonymous enum}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CTRL\_OPERATION\_LOAD@{MLX5\_FPGA\_CTRL\_OPERATION\_LOAD}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CTRL\_OPERATION\_LOAD@{MLX5\_FPGA\_CTRL\_OPERATION\_LOAD}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a6d3735ca4e22b6f07414dea5f711d1eb}\label{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a6d3735ca4e22b6f07414dea5f711d1eb}} 
MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+LOAD&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CTRL\_OPERATION\_RESET@{MLX5\_FPGA\_CTRL\_OPERATION\_RESET}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CTRL\_OPERATION\_RESET@{MLX5\_FPGA\_CTRL\_OPERATION\_RESET}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a630c4b0786e2b1a5165edb8782a97c8f}\label{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a630c4b0786e2b1a5165edb8782a97c8f}} 
MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+RESET&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CTRL\_OPERATION\_FLASH\_SELECT@{MLX5\_FPGA\_CTRL\_OPERATION\_FLASH\_SELECT}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CTRL\_OPERATION\_FLASH\_SELECT@{MLX5\_FPGA\_CTRL\_OPERATION\_FLASH\_SELECT}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a776b2f7f1cc9f463de071c6e290f2baa}\label{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a776b2f7f1cc9f463de071c6e290f2baa}} 
MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+FLASH\+\_\+\+SELECT&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CTRL\_OPERATION\_SANDBOX\_BYPASS\_ON@{MLX5\_FPGA\_CTRL\_OPERATION\_SANDBOX\_BYPASS\_ON}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CTRL\_OPERATION\_SANDBOX\_BYPASS\_ON@{MLX5\_FPGA\_CTRL\_OPERATION\_SANDBOX\_BYPASS\_ON}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a7825fc67041d9b907184fe5999371380}\label{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a7825fc67041d9b907184fe5999371380}} 
MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+SANDBOX\+\_\+\+BYPASS\+\_\+\+ON&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CTRL\_OPERATION\_SANDBOX\_BYPASS\_OFF@{MLX5\_FPGA\_CTRL\_OPERATION\_SANDBOX\_BYPASS\_OFF}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CTRL\_OPERATION\_SANDBOX\_BYPASS\_OFF@{MLX5\_FPGA\_CTRL\_OPERATION\_SANDBOX\_BYPASS\_OFF}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748abd139c9a4aa00b85cca99594b9553e82}\label{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748abd139c9a4aa00b85cca99594b9553e82}} 
MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+SANDBOX\+\_\+\+BYPASS\+\_\+\+OFF&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CTRL\_OPERATION\_RESET\_SANDBOX@{MLX5\_FPGA\_CTRL\_OPERATION\_RESET\_SANDBOX}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CTRL\_OPERATION\_RESET\_SANDBOX@{MLX5\_FPGA\_CTRL\_OPERATION\_RESET\_SANDBOX}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748af596b727f39e977817208937bfa442a4}\label{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748af596b727f39e977817208937bfa442a4}} 
MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+RESET\+\_\+\+SANDBOX&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CTRL\_OPERATION\_DISCONNECT@{MLX5\_FPGA\_CTRL\_OPERATION\_DISCONNECT}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CTRL\_OPERATION\_DISCONNECT@{MLX5\_FPGA\_CTRL\_OPERATION\_DISCONNECT}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748aed7961256cb53e2a0d7d9dfb02aaedb0}\label{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748aed7961256cb53e2a0d7d9dfb02aaedb0}} 
MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+DISCONNECT&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CTRL\_OPERATION\_CONNECT@{MLX5\_FPGA\_CTRL\_OPERATION\_CONNECT}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CTRL\_OPERATION\_CONNECT@{MLX5\_FPGA\_CTRL\_OPERATION\_CONNECT}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748afac2d25cdccd9916bc430de3e04caf86}\label{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748afac2d25cdccd9916bc430de3e04caf86}} 
MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+CONNECT&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_CTRL\_OPERATION\_RELOAD@{MLX5\_FPGA\_CTRL\_OPERATION\_RELOAD}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_CTRL\_OPERATION\_RELOAD@{MLX5\_FPGA\_CTRL\_OPERATION\_RELOAD}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a72e92d75b90775fad68995b6568a221f}\label{mlx5__ifc__fpga_8h_aad1afd468cb4339144d0997ddcf04748a72e92d75b90775fad68995b6568a221f}} 
MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+RELOAD&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00129}{129}} of file \mbox{\hyperlink{mlx5__ifc__fpga_8h_source}{mlx5\+\_\+ifc\+\_\+fpga.\+h}}.

\mbox{\Hypertarget{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5}\label{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5}} 
\doxysubsubsection{\texorpdfstring{anonymous enum}{anonymous enum}}
{\footnotesize\ttfamily anonymous enum}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_CORRUPTED\_DDR@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_CORRUPTED\_DDR}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_CORRUPTED\_DDR@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_CORRUPTED\_DDR}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a244be7aea57ce4f7165b8cfec2cbd02f}\label{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a244be7aea57ce4f7165b8cfec2cbd02f}} 
MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+CORRUPTED\+\_\+\+DDR&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_FLASH\_TIMEOUT@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_FLASH\_TIMEOUT}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_FLASH\_TIMEOUT@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_FLASH\_TIMEOUT}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a79d5fb99dbe4a3aacfd96a14099df1d2}\label{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a79d5fb99dbe4a3aacfd96a14099df1d2}} 
MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+FLASH\+\_\+\+TIMEOUT&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_INTERNAL\_LINK\_ERROR@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_INTERNAL\_LINK\_ERROR}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_INTERNAL\_LINK\_ERROR@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_INTERNAL\_LINK\_ERROR}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5aef5516e0a8e526f8f6fd7e5295af0134}\label{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5aef5516e0a8e526f8f6fd7e5295af0134}} 
MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+INTERNAL\+\_\+\+LINK\+\_\+\+ERROR&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_WATCHDOG\_FAILURE@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_WATCHDOG\_FAILURE}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_WATCHDOG\_FAILURE@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_WATCHDOG\_FAILURE}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a7cd6e9f498de17723459b761288aba7b}\label{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a7cd6e9f498de17723459b761288aba7b}} 
MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+WATCHDOG\+\_\+\+FAILURE&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_I2C\_FAILURE@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_I2C\_FAILURE}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_I2C\_FAILURE@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_I2C\_FAILURE}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a586275d6c948ceb82cbc5c48808c1470}\label{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a586275d6c948ceb82cbc5c48808c1470}} 
MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+I2\+C\+\_\+\+FAILURE&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_IMAGE\_CHANGED@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_IMAGE\_CHANGED}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_IMAGE\_CHANGED@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_IMAGE\_CHANGED}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a079068aa9bc6aae31a67bd325fdb30ef}\label{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a079068aa9bc6aae31a67bd325fdb30ef}} 
MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+IMAGE\+\_\+\+CHANGED&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_TEMPERATURE\_CRITICAL@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_TEMPERATURE\_CRITICAL}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_TEMPERATURE\_CRITICAL@{MLX5\_FPGA\_ERROR\_EVENT\_SYNDROME\_TEMPERATURE\_CRITICAL}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a2ed571e524c329b1b213783d4dc1ba05}\label{mlx5__ifc__fpga_8h_abc3975f01f66a098a347a8262ff103e5a2ed571e524c329b1b213783d4dc1ba05}} 
MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+TEMPERATURE\+\_\+\+CRITICAL&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00155}{155}} of file \mbox{\hyperlink{mlx5__ifc__fpga_8h_source}{mlx5\+\_\+ifc\+\_\+fpga.\+h}}.

\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8de}\label{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8de}} 
\doxysubsubsection{\texorpdfstring{anonymous enum}{anonymous enum}}
{\footnotesize\ttfamily anonymous enum}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_READ@{MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_READ}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_READ@{MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_READ}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8dea8a2e4bd44a0dfba8d264b5e4cac4ac1f}\label{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8dea8a2e4bd44a0dfba8d264b5e4cac4ac1f}} 
MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+READ&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_WRITE@{MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_WRITE}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_WRITE@{MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_WRITE}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8dea73371cf6a9ca46fbe072379d8be402b9}\label{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8dea73371cf6a9ca46fbe072379d8be402b9}} 
MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+WRITE&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_READ\_RESPONSE@{MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_READ\_RESPONSE}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_READ\_RESPONSE@{MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_READ\_RESPONSE}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8dea93f2bb2553028b86e2b7c672dbd01cd9}\label{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8dea93f2bb2553028b86e2b7c672dbd01cd9}} 
MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+READ\+\_\+\+RESPONSE&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_WRITE\_RESPONSE@{MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_WRITE\_RESPONSE}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_WRITE\_RESPONSE@{MLX5\_FPGA\_SHELL\_QP\_PACKET\_TYPE\_DDR\_WRITE\_RESPONSE}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8dea3d6d54f5cffaf74d153d9f202a90596a}\label{mlx5__ifc__fpga_8h_a5e8ce9967db697e85d5528dafee6b8dea3d6d54f5cffaf74d153d9f202a90596a}} 
MLX5\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+QP\+\_\+\+PACKET\+\_\+\+TYPE\+\_\+\+DDR\+\_\+\+WRITE\+\_\+\+RESPONSE&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00464}{464}} of file \mbox{\hyperlink{mlx5__ifc__fpga_8h_source}{mlx5\+\_\+ifc\+\_\+fpga.\+h}}.

\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aaa91b962ffd8aca2f3c24e886a222419}\label{mlx5__ifc__fpga_8h_aaa91b962ffd8aca2f3c24e886a222419}} 
\doxysubsubsection{\texorpdfstring{anonymous enum}{anonymous enum}}
{\footnotesize\ttfamily anonymous enum}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_QP\_ERROR\_EVENT\_SYNDROME\_RETRY\_COUNTER\_EXPIRED@{MLX5\_FPGA\_QP\_ERROR\_EVENT\_SYNDROME\_RETRY\_COUNTER\_EXPIRED}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_QP\_ERROR\_EVENT\_SYNDROME\_RETRY\_COUNTER\_EXPIRED@{MLX5\_FPGA\_QP\_ERROR\_EVENT\_SYNDROME\_RETRY\_COUNTER\_EXPIRED}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aaa91b962ffd8aca2f3c24e886a222419aab86bd93d5b8fb12a199401c7d03ef27}\label{mlx5__ifc__fpga_8h_aaa91b962ffd8aca2f3c24e886a222419aab86bd93d5b8fb12a199401c7d03ef27}} 
MLX5\+\_\+\+FPGA\+\_\+\+QP\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+RETRY\+\_\+\+COUNTER\+\_\+\+EXPIRED&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_QP\_ERROR\_EVENT\_SYNDROME\_RNR\_EXPIRED@{MLX5\_FPGA\_QP\_ERROR\_EVENT\_SYNDROME\_RNR\_EXPIRED}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_QP\_ERROR\_EVENT\_SYNDROME\_RNR\_EXPIRED@{MLX5\_FPGA\_QP\_ERROR\_EVENT\_SYNDROME\_RNR\_EXPIRED}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_aaa91b962ffd8aca2f3c24e886a222419a4de7c7b538e72de955a76a8b53de8e65}\label{mlx5__ifc__fpga_8h_aaa91b962ffd8aca2f3c24e886a222419a4de7c7b538e72de955a76a8b53de8e65}} 
MLX5\+\_\+\+FPGA\+\_\+\+QP\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+RNR\+\_\+\+EXPIRED&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00486}{486}} of file \mbox{\hyperlink{mlx5__ifc__fpga_8h_source}{mlx5\+\_\+ifc\+\_\+fpga.\+h}}.

\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a4b8c34a63f5369ac3d1ad60cb4282f27}\label{mlx5__ifc__fpga_8h_a4b8c34a63f5369ac3d1ad60cb4282f27}} 
\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!mlx5\_ifc\_fpga\_qp\_service\_type@{mlx5\_ifc\_fpga\_qp\_service\_type}}
\index{mlx5\_ifc\_fpga\_qp\_service\_type@{mlx5\_ifc\_fpga\_qp\_service\_type}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_ifc\_fpga\_qp\_service\_type}{mlx5\_ifc\_fpga\_qp\_service\_type}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{mlx5__ifc__fpga_8h_a4b8c34a63f5369ac3d1ad60cb4282f27}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+qp\+\_\+service\+\_\+type}}}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_QPC\_ST\_RC@{MLX5\_FPGA\_QPC\_ST\_RC}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_QPC\_ST\_RC@{MLX5\_FPGA\_QPC\_ST\_RC}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a4b8c34a63f5369ac3d1ad60cb4282f27a22390e7745f50db45494a4b8c9bdfbd9}\label{mlx5__ifc__fpga_8h_a4b8c34a63f5369ac3d1ad60cb4282f27a22390e7745f50db45494a4b8c9bdfbd9}} 
MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+ST\+\_\+\+RC&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00198}{198}} of file \mbox{\hyperlink{mlx5__ifc__fpga_8h_source}{mlx5\+\_\+ifc\+\_\+fpga.\+h}}.

\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5}\label{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5}} 
\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!mlx5\_ifc\_fpga\_qp\_state@{mlx5\_ifc\_fpga\_qp\_state}}
\index{mlx5\_ifc\_fpga\_qp\_state@{mlx5\_ifc\_fpga\_qp\_state}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_ifc\_fpga\_qp\_state}{mlx5\_ifc\_fpga\_qp\_state}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+qp\+\_\+state}}}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_QPC\_STATE\_INIT@{MLX5\_FPGA\_QPC\_STATE\_INIT}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_QPC\_STATE\_INIT@{MLX5\_FPGA\_QPC\_STATE\_INIT}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5a3568e0131117a62b4774e102c878b556}\label{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5a3568e0131117a62b4774e102c878b556}} 
MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+STATE\+\_\+\+INIT&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_QPC\_STATE\_ACTIVE@{MLX5\_FPGA\_QPC\_STATE\_ACTIVE}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_QPC\_STATE\_ACTIVE@{MLX5\_FPGA\_QPC\_STATE\_ACTIVE}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5a947e9f28f30867f89573911006fb96e3}\label{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5a947e9f28f30867f89573911006fb96e3}} 
MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+STATE\+\_\+\+ACTIVE&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_QPC\_STATE\_ERROR@{MLX5\_FPGA\_QPC\_STATE\_ERROR}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_QPC\_STATE\_ERROR@{MLX5\_FPGA\_QPC\_STATE\_ERROR}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5ad1ebc1ae39205b05f73c9c0677516186}\label{mlx5__ifc__fpga_8h_a0a7450a1bc555944d413c0b4375268c5ad1ebc1ae39205b05f73c9c0677516186}} 
MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+STATE\+\_\+\+ERROR&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00187}{187}} of file \mbox{\hyperlink{mlx5__ifc__fpga_8h_source}{mlx5\+\_\+ifc\+\_\+fpga.\+h}}.

\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a58f3b94a7634bd57550c109f15980f86}\label{mlx5__ifc__fpga_8h_a58f3b94a7634bd57550c109f15980f86}} 
\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!mlx5\_ifc\_fpga\_qp\_type@{mlx5\_ifc\_fpga\_qp\_type}}
\index{mlx5\_ifc\_fpga\_qp\_type@{mlx5\_ifc\_fpga\_qp\_type}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}
\doxysubsubsection{\texorpdfstring{mlx5\_ifc\_fpga\_qp\_type}{mlx5\_ifc\_fpga\_qp\_type}}
{\footnotesize\ttfamily enum \mbox{\hyperlink{mlx5__ifc__fpga_8h_a58f3b94a7634bd57550c109f15980f86}{mlx5\+\_\+ifc\+\_\+fpga\+\_\+qp\+\_\+type}}}

\begin{DoxyEnumFields}{Enumerator}
\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_QPC\_QP\_TYPE\_SHELL\_QP@{MLX5\_FPGA\_QPC\_QP\_TYPE\_SHELL\_QP}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_QPC\_QP\_TYPE\_SHELL\_QP@{MLX5\_FPGA\_QPC\_QP\_TYPE\_SHELL\_QP}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a58f3b94a7634bd57550c109f15980f86a6ada2db13d57e5ecf2d98e32e74ec903}\label{mlx5__ifc__fpga_8h_a58f3b94a7634bd57550c109f15980f86a6ada2db13d57e5ecf2d98e32e74ec903}} 
MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+QP\+\_\+\+TYPE\+\_\+\+SHELL\+\_\+\+QP&\\
\hline

\raisebox{\heightof{T}}[0pt][0pt]{\index{MLX5\_FPGA\_QPC\_QP\_TYPE\_SANDBOX\_QP@{MLX5\_FPGA\_QPC\_QP\_TYPE\_SANDBOX\_QP}!mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}}\index{mlx5\_ifc\_fpga.h@{mlx5\_ifc\_fpga.h}!MLX5\_FPGA\_QPC\_QP\_TYPE\_SANDBOX\_QP@{MLX5\_FPGA\_QPC\_QP\_TYPE\_SANDBOX\_QP}}}\mbox{\Hypertarget{mlx5__ifc__fpga_8h_a58f3b94a7634bd57550c109f15980f86a3bb0d594693ba4ebc1cc95c4ebb4ff04}\label{mlx5__ifc__fpga_8h_a58f3b94a7634bd57550c109f15980f86a3bb0d594693ba4ebc1cc95c4ebb4ff04}} 
MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+QP\+\_\+\+TYPE\+\_\+\+SANDBOX\+\_\+\+QP&\\
\hline

\end{DoxyEnumFields}


Definition at line \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00193}{193}} of file \mbox{\hyperlink{mlx5__ifc__fpga_8h_source}{mlx5\+\_\+ifc\+\_\+fpga.\+h}}.

