\hypertarget{mlx5fpga__cmd_8c}{}\doxysection{dev/mlx5/mlx5\+\_\+fpga/mlx5fpga\+\_\+cmd.c File Reference}
\label{mlx5fpga__cmd_8c}\index{dev/mlx5/mlx5\_fpga/mlx5fpga\_cmd.c@{dev/mlx5/mlx5\_fpga/mlx5fpga\_cmd.c}}
{\ttfamily \#include $<$dev/mlx5/cmd.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/driver.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/device.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/mlx5\+\_\+core/mlx5\+\_\+core.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/mlx5\+\_\+fpga/cmd.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/mlx5\+\_\+fpga/core.\+h$>$}\newline
Include dependency graph for mlx5fpga\+\_\+cmd.\+c\+:
\nopagebreak
\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=350pt]{db/d05/mlx5fpga__cmd_8c__incl}
\end{center}
\end{figure}
\doxysubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{mlx5fpga__cmd_8c_a1ae97d4e2bc2370ea587988f6358a287}{MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+REG\+\_\+\+SZ}}
\end{DoxyCompactItemize}
\doxysubsection*{Functions}
\begin{DoxyCompactItemize}
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_ae2ff9b44fa3b641e3a255ced1c3c1bed}{mlx5\+\_\+fpga\+\_\+access\+\_\+reg}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, u8 size, u64 addr, void $\ast$buf, bool write)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_abe27dc3314064a8a67ea6544ec11dece}{mlx5\+\_\+fpga\+\_\+caps}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_ac5914a8fb156377905c3fe00c280069c}{mlx5\+\_\+fpga\+\_\+ctrl\+\_\+op}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, u8 op)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_a4b62e2d576dc537a2089eae832981110}{mlx5\+\_\+fpga\+\_\+sbu\+\_\+caps}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, void $\ast$caps, int size)
\item 
static int \mbox{\hyperlink{mlx5fpga__cmd_8c_ae33458d106a7694758cd78b7f4fe4bf3}{mlx5\+\_\+fpga\+\_\+ctrl\+\_\+write}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, u8 op, enum \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303}{mlx5\+\_\+fpga\+\_\+image}} image)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_a9b6af8b6874442e0bf7d501dbb976448}{mlx5\+\_\+fpga\+\_\+load}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, enum \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303}{mlx5\+\_\+fpga\+\_\+image}} image)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_a3b055802d9d35028a02ee2a5328cee3d}{mlx5\+\_\+fpga\+\_\+image\+\_\+select}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, enum \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303}{mlx5\+\_\+fpga\+\_\+image}} image)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_a6a612eb1cafc5a073c0c552a66cf6c51}{mlx5\+\_\+fpga\+\_\+query}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, struct \mbox{\hyperlink{structmlx5__fpga__query}{mlx5\+\_\+fpga\+\_\+query}} $\ast$query)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_a3391932be83b029924c8d0cb18058d6f}{mlx5\+\_\+fpga\+\_\+ctrl\+\_\+connect}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, enum \mbox{\hyperlink{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4}{mlx5\+\_\+fpga\+\_\+connect}} $\ast$connect)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_a5b5d5204b5552f7e0d9d5dc4292181b6}{mlx5\+\_\+fpga\+\_\+query\+\_\+mtmp}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, struct \mbox{\hyperlink{structmlx5__fpga__temperature}{mlx5\+\_\+fpga\+\_\+temperature}} $\ast$temp)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_aaa2d172446e7ef267e0d5cf6461465d6}{mlx5\+\_\+fpga\+\_\+create\+\_\+qp}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, void $\ast$fpga\+\_\+qpc, u32 $\ast$fpga\+\_\+qpn)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_a2a7138b86f2643d49bd1bc9be5857a1b}{mlx5\+\_\+fpga\+\_\+modify\+\_\+qp}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, u32 fpga\+\_\+qpn, enum \mbox{\hyperlink{mlx5__fpga_2cmd_8h_a0b6133228fc055b3a2957f68bea1b949}{mlx5\+\_\+fpga\+\_\+qpc\+\_\+field\+\_\+select}} fields, void $\ast$fpga\+\_\+qpc)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_a4da1fca380abaca20b92556da92227fa}{mlx5\+\_\+fpga\+\_\+query\+\_\+qp}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, u32 fpga\+\_\+qpn, void $\ast$fpga\+\_\+qpc)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_ad4455b1959566ce7ad0f79c357d8dc39}{mlx5\+\_\+fpga\+\_\+destroy\+\_\+qp}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, u32 fpga\+\_\+qpn)
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_ac562ef5c6060349e6e106701552c8a66}{mlx5\+\_\+fpga\+\_\+query\+\_\+qp\+\_\+counters}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, u32 fpga\+\_\+qpn, bool clear, struct \mbox{\hyperlink{structmlx5__fpga__qp__counters}{mlx5\+\_\+fpga\+\_\+qp\+\_\+counters}} $\ast$\mbox{\hyperlink{mlx5__en__tx_8c_af943c26117683b64b9cd6943e2c496e5}{data}})
\item 
int \mbox{\hyperlink{mlx5fpga__cmd_8c_a303ce41e7282b4f9ec50a8fc1563f070}{mlx5\+\_\+fpga\+\_\+shell\+\_\+counters}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$dev, bool clear, struct \mbox{\hyperlink{structmlx5__fpga__shell__counters}{mlx5\+\_\+fpga\+\_\+shell\+\_\+counters}} $\ast$\mbox{\hyperlink{mlx5__en__tx_8c_af943c26117683b64b9cd6943e2c496e5}{data}})
\end{DoxyCompactItemize}


\doxysubsection{Macro Definition Documentation}
\mbox{\Hypertarget{mlx5fpga__cmd_8c_a1ae97d4e2bc2370ea587988f6358a287}\label{mlx5fpga__cmd_8c_a1ae97d4e2bc2370ea587988f6358a287}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!MLX5\_FPGA\_ACCESS\_REG\_SZ@{MLX5\_FPGA\_ACCESS\_REG\_SZ}}
\index{MLX5\_FPGA\_ACCESS\_REG\_SZ@{MLX5\_FPGA\_ACCESS\_REG\_SZ}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{MLX5\_FPGA\_ACCESS\_REG\_SZ}{MLX5\_FPGA\_ACCESS\_REG\_SZ}}
{\footnotesize\ttfamily \#define MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+REG\+\_\+\+SZ}

{\bfseries Value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{                                 (\mbox{\hyperlink{device_8h_a2bdfa104f3d7c0635b984382d1562741}{MLX5\_ST\_SZ\_DW}}(fpga\_access\_reg) + \(\backslash\)}
\DoxyCodeLine{                                 MLX5\_FPGA\_ACCESS\_REG\_SIZE\_MAX)}

\end{DoxyCode}


Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00042}{42}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



\doxysubsection{Function Documentation}
\mbox{\Hypertarget{mlx5fpga__cmd_8c_ae2ff9b44fa3b641e3a255ced1c3c1bed}\label{mlx5fpga__cmd_8c_ae2ff9b44fa3b641e3a255ced1c3c1bed}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_access\_reg@{mlx5\_fpga\_access\_reg}}
\index{mlx5\_fpga\_access\_reg@{mlx5\_fpga\_access\_reg}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_access\_reg()}{mlx5\_fpga\_access\_reg()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+access\+\_\+reg (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{u8}]{size,  }\item[{u64}]{addr,  }\item[{void $\ast$}]{buf,  }\item[{bool}]{write }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00045}{45}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{mlx5__en__tx_8c_source_l00001}{data}}, \mbox{\hyperlink{device_8h_source_l00070}{MLX5\+\_\+\+ADDR\+\_\+\+OF}}, \mbox{\hyperlink{mlx5__port_8c_source_l00035}{mlx5\+\_\+core\+\_\+access\+\_\+reg()}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00174}{MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+REG\+\_\+\+SIZE\+\_\+\+MAX}}, \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00042}{MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+REG\+\_\+\+SZ}}, \mbox{\hyperlink{driver_8h_source_l00134}{MLX5\+\_\+\+REG\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+REG}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, and \mbox{\hyperlink{device_8h_source_l00106}{MLX5\+\_\+\+SET64}}.



Referenced by \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00132}{mlx5\+\_\+fpga\+\_\+mem\+\_\+read\+\_\+i2c()}}, \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00164}{mlx5\+\_\+fpga\+\_\+mem\+\_\+write\+\_\+i2c()}}, and \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00095}{mlx5\+\_\+fpga\+\_\+sbu\+\_\+caps()}}.

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\mbox{\Hypertarget{mlx5fpga__cmd_8c_abe27dc3314064a8a67ea6544ec11dece}\label{mlx5fpga__cmd_8c_abe27dc3314064a8a67ea6544ec11dece}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_caps@{mlx5\_fpga\_caps}}
\index{mlx5\_fpga\_caps@{mlx5\_fpga\_caps}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_caps()}{mlx5\_fpga\_caps()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+caps (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00075}{75}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{structmlx5__core__dev_a7ce7a5d3a6d209167e4948732818ce6d}{mlx5\+\_\+core\+\_\+dev\+::caps}}, \mbox{\hyperlink{driver_8h_source_l00670}{mlx5\+\_\+core\+\_\+dev\+::fpga}}, \mbox{\hyperlink{mlx5__port_8c_source_l00035}{mlx5\+\_\+core\+\_\+access\+\_\+reg()}}, \mbox{\hyperlink{driver_8h_source_l00132}{MLX5\+\_\+\+REG\+\_\+\+FPGA\+\_\+\+CAP}}, \mbox{\hyperlink{device_8h_source_l00064}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+BYTES}}, and \mbox{\hyperlink{device_8h_source_l00065}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+DW}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00206}{mlx5\+\_\+fpga\+\_\+device\+\_\+start()}}.

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\mbox{\Hypertarget{mlx5fpga__cmd_8c_aaa2d172446e7ef267e0d5cf6461465d6}\label{mlx5fpga__cmd_8c_aaa2d172446e7ef267e0d5cf6461465d6}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_create\_qp@{mlx5\_fpga\_create\_qp}}
\index{mlx5\_fpga\_create\_qp@{mlx5\_fpga\_create\_qp}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_create\_qp()}{mlx5\_fpga\_create\_qp()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+create\+\_\+qp (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{void $\ast$}]{fpga\+\_\+qpc,  }\item[{u32 $\ast$}]{fpga\+\_\+qpn }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00227}{227}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{device_8h_source_l00070}{MLX5\+\_\+\+ADDR\+\_\+\+OF}}, \mbox{\hyperlink{mlx5__cmd_8c_source_l01347}{mlx5\+\_\+cmd\+\_\+exec()}}, \mbox{\hyperlink{mlx5__ifc_8h_source_l00285}{MLX5\+\_\+\+CMD\+\_\+\+OP\+\_\+\+FPGA\+\_\+\+CREATE\+\_\+\+QP}}, \mbox{\hyperlink{device_8h_source_l00063}{MLX5\+\_\+\+FLD\+\_\+\+SZ\+\_\+\+BYTES}}, \mbox{\hyperlink{device_8h_source_l00091}{MLX5\+\_\+\+GET}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, and \mbox{\hyperlink{device_8h_source_l00065}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+DW}}.



Referenced by \mbox{\hyperlink{mlx5fpga__conn_8c_source_l00844}{mlx5\+\_\+fpga\+\_\+conn\+\_\+create()}}.

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\mbox{\Hypertarget{mlx5fpga__cmd_8c_a3391932be83b029924c8d0cb18058d6f}\label{mlx5fpga__cmd_8c_a3391932be83b029924c8d0cb18058d6f}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_ctrl\_connect@{mlx5\_fpga\_ctrl\_connect}}
\index{mlx5\_fpga\_ctrl\_connect@{mlx5\_fpga\_ctrl\_connect}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_ctrl\_connect()}{mlx5\_fpga\_ctrl\_connect()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+ctrl\+\_\+connect (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{enum \mbox{\hyperlink{mlx5io_8h_ac573a5194065f34c0973d752102e6dd4}{mlx5\+\_\+fpga\+\_\+connect}} $\ast$}]{connect }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00168}{168}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{mlx5__port_8c_source_l00035}{mlx5\+\_\+core\+\_\+access\+\_\+reg()}}, \mbox{\hyperlink{mlx5io_8h_source_l00113}{MLX5\+\_\+\+FPGA\+\_\+\+CONNECT\+\_\+\+CONNECT}}, \mbox{\hyperlink{mlx5io_8h_source_l00112}{MLX5\+\_\+\+FPGA\+\_\+\+CONNECT\+\_\+\+DISCONNECT}}, \mbox{\hyperlink{mlx5io_8h_source_l00111}{MLX5\+\_\+\+FPGA\+\_\+\+CONNECT\+\_\+\+QUERY}}, \mbox{\hyperlink{device_8h_source_l00091}{MLX5\+\_\+\+GET}}, \mbox{\hyperlink{driver_8h_source_l00133}{MLX5\+\_\+\+REG\+\_\+\+FPGA\+\_\+\+CTRL}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, and \mbox{\hyperlink{device_8h_source_l00065}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+DW}}.



Referenced by \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00496}{mlx5\+\_\+fpga\+\_\+connectdisconnect()}}.

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\mbox{\Hypertarget{mlx5fpga__cmd_8c_ac5914a8fb156377905c3fe00c280069c}\label{mlx5fpga__cmd_8c_ac5914a8fb156377905c3fe00c280069c}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_ctrl\_op@{mlx5\_fpga\_ctrl\_op}}
\index{mlx5\_fpga\_ctrl\_op@{mlx5\_fpga\_ctrl\_op}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_ctrl\_op()}{mlx5\_fpga\_ctrl\_op()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+ctrl\+\_\+op (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{u8}]{op }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00084}{84}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{mlx5__port_8c_source_l00035}{mlx5\+\_\+core\+\_\+access\+\_\+reg()}}, \mbox{\hyperlink{driver_8h_source_l00133}{MLX5\+\_\+\+REG\+\_\+\+FPGA\+\_\+\+CTRL}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, and \mbox{\hyperlink{device_8h_source_l00065}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+DW}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00183}{mlx5\+\_\+fpga\+\_\+device\+\_\+brb()}}, \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00366}{mlx5\+\_\+fpga\+\_\+device\+\_\+reload()}}, \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00327}{mlx5\+\_\+fpga\+\_\+device\+\_\+reload\+\_\+cmd()}}, and \mbox{\hyperlink{mlx5fpga__core_8c_source_l00361}{mlx5\+\_\+fpga\+\_\+device\+\_\+stop()}}.

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\mbox{\Hypertarget{mlx5fpga__cmd_8c_ae33458d106a7694758cd78b7f4fe4bf3}\label{mlx5fpga__cmd_8c_ae33458d106a7694758cd78b7f4fe4bf3}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_ctrl\_write@{mlx5\_fpga\_ctrl\_write}}
\index{mlx5\_fpga\_ctrl\_write@{mlx5\_fpga\_ctrl\_write}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_ctrl\_write()}{mlx5\_fpga\_ctrl\_write()}}
{\footnotesize\ttfamily static int mlx5\+\_\+fpga\+\_\+ctrl\+\_\+write (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{u8}]{op,  }\item[{enum \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303}{mlx5\+\_\+fpga\+\_\+image}}}]{image }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00127}{127}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{mlx5__port_8c_source_l00035}{mlx5\+\_\+core\+\_\+access\+\_\+reg()}}, \mbox{\hyperlink{driver_8h_source_l00133}{MLX5\+\_\+\+REG\+\_\+\+FPGA\+\_\+\+CTRL}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, and \mbox{\hyperlink{device_8h_source_l00065}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+DW}}.



Referenced by \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00145}{mlx5\+\_\+fpga\+\_\+image\+\_\+select()}}, and \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00140}{mlx5\+\_\+fpga\+\_\+load()}}.

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\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_ae33458d106a7694758cd78b7f4fe4bf3_cgraph}
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\mbox{\Hypertarget{mlx5fpga__cmd_8c_ad4455b1959566ce7ad0f79c357d8dc39}\label{mlx5fpga__cmd_8c_ad4455b1959566ce7ad0f79c357d8dc39}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_destroy\_qp@{mlx5\_fpga\_destroy\_qp}}
\index{mlx5\_fpga\_destroy\_qp@{mlx5\_fpga\_destroy\_qp}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_destroy\_qp()}{mlx5\_fpga\_destroy\_qp()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+destroy\+\_\+qp (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{u32}]{fpga\+\_\+qpn }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00283}{283}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{mlx5__cmd_8c_source_l01347}{mlx5\+\_\+cmd\+\_\+exec()}}, \mbox{\hyperlink{mlx5__ifc_8h_source_l00288}{MLX5\+\_\+\+CMD\+\_\+\+OP\+\_\+\+FPGA\+\_\+\+DESTROY\+\_\+\+QP}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, and \mbox{\hyperlink{device_8h_source_l00065}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+DW}}.



Referenced by \mbox{\hyperlink{mlx5fpga__conn_8c_source_l00844}{mlx5\+\_\+fpga\+\_\+conn\+\_\+create()}}, and \mbox{\hyperlink{mlx5fpga__conn_8c_source_l00966}{mlx5\+\_\+fpga\+\_\+conn\+\_\+destroy()}}.

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\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_ad4455b1959566ce7ad0f79c357d8dc39_cgraph}
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\end{center}
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\mbox{\Hypertarget{mlx5fpga__cmd_8c_a3b055802d9d35028a02ee2a5328cee3d}\label{mlx5fpga__cmd_8c_a3b055802d9d35028a02ee2a5328cee3d}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_image\_select@{mlx5\_fpga\_image\_select}}
\index{mlx5\_fpga\_image\_select@{mlx5\_fpga\_image\_select}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_image\_select()}{mlx5\_fpga\_image\_select()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+image\+\_\+select (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{enum \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303}{mlx5\+\_\+fpga\+\_\+image}}}]{image }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00145}{145}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00132}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+FLASH\+\_\+\+SELECT}}, and \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00127}{mlx5\+\_\+fpga\+\_\+ctrl\+\_\+write()}}.



Referenced by \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00468}{mlx5\+\_\+fpga\+\_\+flash\+\_\+select()}}.

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\begin{center}
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\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_a3b055802d9d35028a02ee2a5328cee3d_icgraph}
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\mbox{\Hypertarget{mlx5fpga__cmd_8c_a9b6af8b6874442e0bf7d501dbb976448}\label{mlx5fpga__cmd_8c_a9b6af8b6874442e0bf7d501dbb976448}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_load@{mlx5\_fpga\_load}}
\index{mlx5\_fpga\_load@{mlx5\_fpga\_load}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_load()}{mlx5\_fpga\_load()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+load (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{enum \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303}{mlx5\+\_\+fpga\+\_\+image}}}]{image }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00140}{140}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00130}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+LOAD}}, and \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00127}{mlx5\+\_\+fpga\+\_\+ctrl\+\_\+write()}}.



Referenced by \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00366}{mlx5\+\_\+fpga\+\_\+device\+\_\+reload()}}.

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\mbox{\Hypertarget{mlx5fpga__cmd_8c_a2a7138b86f2643d49bd1bc9be5857a1b}\label{mlx5fpga__cmd_8c_a2a7138b86f2643d49bd1bc9be5857a1b}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_modify\_qp@{mlx5\_fpga\_modify\_qp}}
\index{mlx5\_fpga\_modify\_qp@{mlx5\_fpga\_modify\_qp}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_modify\_qp()}{mlx5\_fpga\_modify\_qp()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+modify\+\_\+qp (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{u32}]{fpga\+\_\+qpn,  }\item[{enum \mbox{\hyperlink{mlx5__fpga_2cmd_8h_a0b6133228fc055b3a2957f68bea1b949}{mlx5\+\_\+fpga\+\_\+qpc\+\_\+field\+\_\+select}}}]{fields,  }\item[{void $\ast$}]{fpga\+\_\+qpc }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00248}{248}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{device_8h_source_l00070}{MLX5\+\_\+\+ADDR\+\_\+\+OF}}, \mbox{\hyperlink{mlx5__cmd_8c_source_l01347}{mlx5\+\_\+cmd\+\_\+exec()}}, \mbox{\hyperlink{mlx5__ifc_8h_source_l00286}{MLX5\+\_\+\+CMD\+\_\+\+OP\+\_\+\+FPGA\+\_\+\+MODIFY\+\_\+\+QP}}, \mbox{\hyperlink{device_8h_source_l00063}{MLX5\+\_\+\+FLD\+\_\+\+SZ\+\_\+\+BYTES}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, and \mbox{\hyperlink{device_8h_source_l00065}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+DW}}.



Referenced by \mbox{\hyperlink{mlx5fpga__conn_8c_source_l00791}{mlx5\+\_\+fpga\+\_\+conn\+\_\+connect()}}.

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\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_a2a7138b86f2643d49bd1bc9be5857a1b_cgraph}
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\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_a2a7138b86f2643d49bd1bc9be5857a1b_icgraph}
\end{center}
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\mbox{\Hypertarget{mlx5fpga__cmd_8c_a6a612eb1cafc5a073c0c552a66cf6c51}\label{mlx5fpga__cmd_8c_a6a612eb1cafc5a073c0c552a66cf6c51}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_query@{mlx5\_fpga\_query}}
\index{mlx5\_fpga\_query@{mlx5\_fpga\_query}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_query()}{mlx5\_fpga\_query()}}
{\footnotesize\ttfamily int \mbox{\hyperlink{structmlx5__fpga__query}{mlx5\+\_\+fpga\+\_\+query}} (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{struct \mbox{\hyperlink{structmlx5__fpga__query}{mlx5\+\_\+fpga\+\_\+query}} $\ast$}]{query }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00151}{151}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{mlx5io_8h_source_l00099}{mlx5\+\_\+fpga\+\_\+query\+::admin\+\_\+image}}, \mbox{\hyperlink{mlx5io_8h_source_l00101}{mlx5\+\_\+fpga\+\_\+query\+::image\+\_\+status}}, \mbox{\hyperlink{mlx5__port_8c_source_l00035}{mlx5\+\_\+core\+\_\+access\+\_\+reg()}}, \mbox{\hyperlink{device_8h_source_l00091}{MLX5\+\_\+\+GET}}, \mbox{\hyperlink{driver_8h_source_l00133}{MLX5\+\_\+\+REG\+\_\+\+FPGA\+\_\+\+CTRL}}, \mbox{\hyperlink{device_8h_source_l00065}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+DW}}, and \mbox{\hyperlink{mlx5io_8h_source_l00100}{mlx5\+\_\+fpga\+\_\+query\+::oper\+\_\+image}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00149}{mlx5\+\_\+fpga\+\_\+device\+\_\+load\+\_\+check()}}.

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\leavevmode
\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_a6a612eb1cafc5a073c0c552a66cf6c51_cgraph}
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\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_a6a612eb1cafc5a073c0c552a66cf6c51_icgraph}
\end{center}
\end{figure}
\mbox{\Hypertarget{mlx5fpga__cmd_8c_a5b5d5204b5552f7e0d9d5dc4292181b6}\label{mlx5fpga__cmd_8c_a5b5d5204b5552f7e0d9d5dc4292181b6}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_query\_mtmp@{mlx5\_fpga\_query\_mtmp}}
\index{mlx5\_fpga\_query\_mtmp@{mlx5\_fpga\_query\_mtmp}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_query\_mtmp()}{mlx5\_fpga\_query\_mtmp()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+query\+\_\+mtmp (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{struct \mbox{\hyperlink{structmlx5__fpga__temperature}{mlx5\+\_\+fpga\+\_\+temperature}} $\ast$}]{temp }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00195}{195}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{mlx5io_8h_source_l00135}{mlx5\+\_\+fpga\+\_\+temperature\+::index}}, \mbox{\hyperlink{mlx5io_8h_source_l00137}{mlx5\+\_\+fpga\+\_\+temperature\+::max\+\_\+temperature}}, \mbox{\hyperlink{device_8h_source_l00070}{MLX5\+\_\+\+ADDR\+\_\+\+OF}}, \mbox{\hyperlink{mlx5__port_8c_source_l00035}{mlx5\+\_\+core\+\_\+access\+\_\+reg()}}, \mbox{\hyperlink{device_8h_source_l00063}{MLX5\+\_\+\+FLD\+\_\+\+SZ\+\_\+\+BYTES}}, \mbox{\hyperlink{mlx5io_8h_source_l00131}{MLX5\+\_\+\+FPGA\+\_\+\+INTERNAL\+\_\+\+SENSORS\+\_\+\+HIGH}}, \mbox{\hyperlink{mlx5io_8h_source_l00130}{MLX5\+\_\+\+FPGA\+\_\+\+INTERNAL\+\_\+\+SENSORS\+\_\+\+LOW}}, \mbox{\hyperlink{device_8h_source_l00091}{MLX5\+\_\+\+GET}}, \mbox{\hyperlink{driver_8h_source_l00156}{MLX5\+\_\+\+REG\+\_\+\+MTMP}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, \mbox{\hyperlink{device_8h_source_l00065}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+DW}}, \mbox{\hyperlink{mlx5io_8h_source_l00140}{mlx5\+\_\+fpga\+\_\+temperature\+::mte}}, \mbox{\hyperlink{mlx5io_8h_source_l00142}{mlx5\+\_\+fpga\+\_\+temperature\+::sensor\+\_\+name}}, \mbox{\hyperlink{mlx5io_8h_source_l00136}{mlx5\+\_\+fpga\+\_\+temperature\+::tee}}, \mbox{\hyperlink{mlx5io_8h_source_l00134}{mlx5\+\_\+fpga\+\_\+temperature\+::temperature}}, \mbox{\hyperlink{mlx5io_8h_source_l00138}{mlx5\+\_\+fpga\+\_\+temperature\+::temperature\+\_\+threshold\+\_\+hi}}, and \mbox{\hyperlink{mlx5io_8h_source_l00139}{mlx5\+\_\+fpga\+\_\+temperature\+::temperature\+\_\+threshold\+\_\+lo}}.



Referenced by \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00522}{mlx5\+\_\+fpga\+\_\+temperature()}}.

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\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_a5b5d5204b5552f7e0d9d5dc4292181b6_cgraph}
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\end{center}
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\mbox{\Hypertarget{mlx5fpga__cmd_8c_a4da1fca380abaca20b92556da92227fa}\label{mlx5fpga__cmd_8c_a4da1fca380abaca20b92556da92227fa}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_query\_qp@{mlx5\_fpga\_query\_qp}}
\index{mlx5\_fpga\_query\_qp@{mlx5\_fpga\_query\_qp}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_query\_qp()}{mlx5\_fpga\_query\_qp()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+query\+\_\+qp (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{u32}]{fpga\+\_\+qpn,  }\item[{void $\ast$}]{fpga\+\_\+qpc }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00264}{264}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{device_8h_source_l00070}{MLX5\+\_\+\+ADDR\+\_\+\+OF}}, \mbox{\hyperlink{mlx5__cmd_8c_source_l01347}{mlx5\+\_\+cmd\+\_\+exec()}}, \mbox{\hyperlink{mlx5__ifc_8h_source_l00287}{MLX5\+\_\+\+CMD\+\_\+\+OP\+\_\+\+FPGA\+\_\+\+QUERY\+\_\+\+QP}}, \mbox{\hyperlink{device_8h_source_l00063}{MLX5\+\_\+\+FLD\+\_\+\+SZ\+\_\+\+BYTES}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, and \mbox{\hyperlink{device_8h_source_l00065}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+DW}}.

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\begin{center}
\leavevmode
\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_a4da1fca380abaca20b92556da92227fa_cgraph}
\end{center}
\end{figure}
\mbox{\Hypertarget{mlx5fpga__cmd_8c_ac562ef5c6060349e6e106701552c8a66}\label{mlx5fpga__cmd_8c_ac562ef5c6060349e6e106701552c8a66}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_query\_qp\_counters@{mlx5\_fpga\_query\_qp\_counters}}
\index{mlx5\_fpga\_query\_qp\_counters@{mlx5\_fpga\_query\_qp\_counters}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_query\_qp\_counters()}{mlx5\_fpga\_query\_qp\_counters()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+query\+\_\+qp\+\_\+counters (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{u32}]{fpga\+\_\+qpn,  }\item[{bool}]{clear,  }\item[{struct \mbox{\hyperlink{structmlx5__fpga__qp__counters}{mlx5\+\_\+fpga\+\_\+qp\+\_\+counters}} $\ast$}]{data }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00294}{294}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{mlx5__en__tx_8c_source_l00001}{data}}, \mbox{\hyperlink{mlx5__cmd_8c_source_l01347}{mlx5\+\_\+cmd\+\_\+exec()}}, \mbox{\hyperlink{mlx5__ifc_8h_source_l00289}{MLX5\+\_\+\+CMD\+\_\+\+OP\+\_\+\+FPGA\+\_\+\+QUERY\+\_\+\+QP\+\_\+\+COUNTERS}}, \mbox{\hyperlink{device_8h_source_l00116}{MLX5\+\_\+\+GET64}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, and \mbox{\hyperlink{device_8h_source_l00065}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+DW}}.

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\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_ac562ef5c6060349e6e106701552c8a66_cgraph}
\end{center}
\end{figure}
\mbox{\Hypertarget{mlx5fpga__cmd_8c_a4b62e2d576dc537a2089eae832981110}\label{mlx5fpga__cmd_8c_a4b62e2d576dc537a2089eae832981110}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_sbu\_caps@{mlx5\_fpga\_sbu\_caps}}
\index{mlx5\_fpga\_sbu\_caps@{mlx5\_fpga\_sbu\_caps}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_sbu\_caps()}{mlx5\_fpga\_sbu\_caps()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+sbu\+\_\+caps (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{void $\ast$}]{caps,  }\item[{int}]{size }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00095}{95}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{device_8h_source_l01161}{MLX5\+\_\+\+CAP64\+\_\+\+FPGA}}, \mbox{\hyperlink{device_8h_source_l01158}{MLX5\+\_\+\+CAP\+\_\+\+FPGA}}, \mbox{\hyperlink{mlx5__core_8h_source_l00061}{mlx5\+\_\+core\+\_\+warn}}, \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00045}{mlx5\+\_\+fpga\+\_\+access\+\_\+reg()}}, and \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00174}{MLX5\+\_\+\+FPGA\+\_\+\+ACCESS\+\_\+\+REG\+\_\+\+SIZE\+\_\+\+MAX}}.



Referenced by \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00261}{mlx5\+\_\+fpga\+\_\+get\+\_\+sbu\+\_\+caps()}}.

Here is the call graph for this function\+:
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\begin{center}
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\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_a4b62e2d576dc537a2089eae832981110_cgraph}
\end{center}
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Here is the caller graph for this function\+:
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\begin{center}
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\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_a4b62e2d576dc537a2089eae832981110_icgraph}
\end{center}
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\mbox{\Hypertarget{mlx5fpga__cmd_8c_a303ce41e7282b4f9ec50a8fc1563f070}\label{mlx5fpga__cmd_8c_a303ce41e7282b4f9ec50a8fc1563f070}} 
\index{mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}!mlx5\_fpga\_shell\_counters@{mlx5\_fpga\_shell\_counters}}
\index{mlx5\_fpga\_shell\_counters@{mlx5\_fpga\_shell\_counters}!mlx5fpga\_cmd.c@{mlx5fpga\_cmd.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_shell\_counters()}{mlx5\_fpga\_shell\_counters()}}
{\footnotesize\ttfamily int \mbox{\hyperlink{structmlx5__fpga__shell__counters}{mlx5\+\_\+fpga\+\_\+shell\+\_\+counters}} (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{dev,  }\item[{bool}]{clear,  }\item[{struct \mbox{\hyperlink{structmlx5__fpga__shell__counters}{mlx5\+\_\+fpga\+\_\+shell\+\_\+counters}} $\ast$}]{data }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00324}{324}} of file \mbox{\hyperlink{mlx5fpga__cmd_8c_source}{mlx5fpga\+\_\+cmd.\+c}}.



References \mbox{\hyperlink{mlx5__en__tx_8c_source_l00001}{data}}, \mbox{\hyperlink{mlx5__port_8c_source_l00035}{mlx5\+\_\+core\+\_\+access\+\_\+reg()}}, \mbox{\hyperlink{device_8h_source_l00116}{MLX5\+\_\+\+GET64}}, \mbox{\hyperlink{driver_8h_source_l00135}{MLX5\+\_\+\+REG\+\_\+\+FPGA\+\_\+\+SHELL\+\_\+\+CNTR}}, \mbox{\hyperlink{device_8h_source_l00073}{MLX5\+\_\+\+SET}}, and \mbox{\hyperlink{device_8h_source_l00065}{MLX5\+\_\+\+ST\+\_\+\+SZ\+\_\+\+DW}}.

Here is the call graph for this function\+:
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\begin{center}
\leavevmode
\includegraphics[width=350pt]{d1/d5b/mlx5fpga__cmd_8c_a303ce41e7282b4f9ec50a8fc1563f070_cgraph}
\end{center}
\end{figure}
