\hypertarget{mlx5fpga__core_8c_source}{}\doxysection{mlx5fpga\+\_\+core.\+c}
\label{mlx5fpga__core_8c_source}\index{dev/mlx5/mlx5\_fpga/mlx5fpga\_core.c@{dev/mlx5/mlx5\_fpga/mlx5fpga\_core.c}}
\mbox{\hyperlink{mlx5fpga__core_8c}{Go to the documentation of this file.}}
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\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00002}00002 \textcolor{comment}{ * Copyright (c) 2017, Mellanox Technologies. All rights reserved.}}
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\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00230}00230         fpga\_id = \mbox{\hyperlink{device_8h_ac7dc30f0629f44ba36e9d709cbeebd35}{MLX5\_CAP\_FPGA}}(\mbox{\hyperlink{structmlx5__fpga__conn_a14fa437bcda564ce45f1a9cf2de195bc}{fdev}}-\/>mdev, fpga\_id);}
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00231}00231         mlx5\_fpga\_info(\mbox{\hyperlink{structmlx5__fpga__conn_a14fa437bcda564ce45f1a9cf2de195bc}{fdev}}, \textcolor{stringliteral}{"{}FPGA card \%s\(\backslash\)n"{}}, \mbox{\hyperlink{mlx5fpga__core_8c_a5ce39b9eda48c1cb615c0df76ab552a9}{mlx5\_fpga\_name}}(fpga\_id));}
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\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00236}00236         mlx5\_fpga\_info(\mbox{\hyperlink{structmlx5__fpga__conn_a14fa437bcda564ce45f1a9cf2de195bc}{fdev}}, \textcolor{stringliteral}{"{}\%s(\%d) image, version \%u; SBU \%06x:\%04x version \%d\(\backslash\)n"{}},}
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00237}00237                        \mbox{\hyperlink{mlx5fpga__core_8c_a3a0d25f677c9c7a97f10ed67e06266e5}{mlx5\_fpga\_image\_name}}(\mbox{\hyperlink{structmlx5__fpga__conn_a14fa437bcda564ce45f1a9cf2de195bc}{fdev}}-\/>last\_oper\_image),}
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\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00242}00242                        \mbox{\hyperlink{device_8h_ac7dc30f0629f44ba36e9d709cbeebd35}{MLX5\_CAP\_FPGA}}(\mbox{\hyperlink{structmlx5__fpga__conn_a14fa437bcda564ce45f1a9cf2de195bc}{fdev}}-\/>mdev, sandbox\_product\_version));}
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\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00247}00247                 \textcolor{keywordflow}{goto} out;}
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00248}00248 }
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\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00257}00257 }
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00258}00258         err = \mbox{\hyperlink{mlx5fpga__trans_8c_ae13a014b26163a451655dc60d864aeb4}{mlx5\_fpga\_trans\_device\_init}}(\mbox{\hyperlink{structmlx5__fpga__conn_a14fa437bcda564ce45f1a9cf2de195bc}{fdev}});}
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\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00359}00359 \}}
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00360}00360 }
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\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00362}00362 \{}
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\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00372}00372 }
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00373}00373         fpga\_id = \mbox{\hyperlink{device_8h_ac7dc30f0629f44ba36e9d709cbeebd35}{MLX5\_CAP\_FPGA}}(mdev, fpga\_id);}
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\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00375}00375                 \textcolor{keywordflow}{return};}
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00376}00376 }
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00377}00377         spin\_lock\_irqsave(\&fdev-\/>state\_lock, flags);}
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00378}00378 }
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00379}00379         \textcolor{keywordflow}{if} (fdev-\/>fdev\_state != MLX5\_FDEV\_STATE\_SUCCESS) \{}
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\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00381}00381                 \textcolor{keywordflow}{return};}
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00382}00382         \}}
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00383}00383         fdev-\/>fdev\_state = MLX5\_FDEV\_STATE\_NONE;}
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00384}00384         spin\_unlock\_irqrestore(\&fdev-\/>state\_lock, flags);}
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00385}00385 }
\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00386}00386         \textcolor{keywordflow}{if} (fdev-\/>last\_oper\_image == \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303a252b496c89a9e3e05c0ce1a23e906e2f}{MLX5\_FPGA\_IMAGE\_USER}}) \{}
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\DoxyCodeLine{\Hypertarget{mlx5fpga__core_8c_source_l00400}00400         mutex\_unlock(\&mlx5\_fpga\_mutex);}
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