\hypertarget{mlx5fpga__core_8c}{}\doxysection{dev/mlx5/mlx5\+\_\+fpga/mlx5fpga\+\_\+core.c File Reference}
\label{mlx5fpga__core_8c}\index{dev/mlx5/mlx5\_fpga/mlx5fpga\_core.c@{dev/mlx5/mlx5\_fpga/mlx5fpga\_core.c}}
{\ttfamily \#include $<$linux/module.\+h$>$}\newline
{\ttfamily \#include $<$linux/etherdevice.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/driver.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/mlx5\+\_\+core/mlx5\+\_\+core.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/mlx5\+\_\+lib/mlx5.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/mlx5\+\_\+fpga/core.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/mlx5\+\_\+fpga/conn.\+h$>$}\newline
{\ttfamily \#include $<$dev/mlx5/mlx5\+\_\+fpga/trans.\+h$>$}\newline
Include dependency graph for mlx5fpga\+\_\+core.\+c\+:
\nopagebreak
\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=350pt]{dd/d5d/mlx5fpga__core_8c__incl}
\end{center}
\end{figure}
\doxysubsection*{Functions}
\begin{DoxyCompactItemize}
\item 
static \mbox{\hyperlink{mlx5fpga__core_8c_ab053fbb838d2d88133c0d4b5469e8984}{LIST\+\_\+\+HEAD}} (mlx5\+\_\+fpga\+\_\+devices)
\item 
static \mbox{\hyperlink{mlx5fpga__core_8c_aa9d3a2c4dd94196630512d800e34dd4d}{LIST\+\_\+\+HEAD}} (mlx5\+\_\+fpga\+\_\+clients)
\item 
static \mbox{\hyperlink{mlx5fpga__core_8c_a5c9182a9e2672cdd28bc73f1fc8250f6}{DEFINE\+\_\+\+MUTEX}} (mlx5\+\_\+fpga\+\_\+mutex)
\item 
static void \mbox{\hyperlink{mlx5fpga__core_8c_aaec7f22375d6ef5df787d1fbfa9f7901}{client\+\_\+context\+\_\+destroy}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev, struct mlx5\+\_\+fpga\+\_\+client\+\_\+data $\ast$context)
\item 
static int \mbox{\hyperlink{mlx5fpga__core_8c_a9dfd61401e9663fd2d55b375560ef1b1}{client\+\_\+context\+\_\+create}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev, struct \mbox{\hyperlink{structmlx5__fpga__client}{mlx5\+\_\+fpga\+\_\+client}} $\ast$client, struct mlx5\+\_\+fpga\+\_\+client\+\_\+data $\ast$$\ast$pctx)
\item 
static struct mlx5\+\_\+fpga\+\_\+device $\ast$ \mbox{\hyperlink{mlx5fpga__core_8c_ab39214501cab61757485e78305f880c1}{mlx5\+\_\+fpga\+\_\+device\+\_\+alloc}} (void)
\item 
static const char $\ast$ \mbox{\hyperlink{mlx5fpga__core_8c_a3a0d25f677c9c7a97f10ed67e06266e5}{mlx5\+\_\+fpga\+\_\+image\+\_\+name}} (enum \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303}{mlx5\+\_\+fpga\+\_\+image}} image)
\item 
static const char $\ast$ \mbox{\hyperlink{mlx5fpga__core_8c_a5ce39b9eda48c1cb615c0df76ab552a9}{mlx5\+\_\+fpga\+\_\+name}} (u32 fpga\+\_\+id)
\item 
static int \mbox{\hyperlink{mlx5fpga__core_8c_a2626d510b71bc7fe69fda5f5cc5e13b8}{mlx5\+\_\+fpga\+\_\+device\+\_\+load\+\_\+check}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev)
\item 
static int \mbox{\hyperlink{mlx5fpga__core_8c_ab4ed01984c3cae90135b2d7ba9215fca}{mlx5\+\_\+fpga\+\_\+device\+\_\+brb}} (struct mlx5\+\_\+fpga\+\_\+device $\ast$fdev)
\item 
int \mbox{\hyperlink{mlx5fpga__core_8c_a8886feccc56646d230e8988127c262eb}{mlx5\+\_\+fpga\+\_\+device\+\_\+start}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$mdev)
\item 
int \mbox{\hyperlink{mlx5fpga__core_8c_a9d7ab99958d10ee555818f2a59c6bd5a}{mlx5\+\_\+fpga\+\_\+init}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$mdev)
\item 
void \mbox{\hyperlink{mlx5fpga__core_8c_abf23345b773352ccf0a2b234bdf45bde}{mlx5\+\_\+fpga\+\_\+device\+\_\+stop}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$mdev)
\item 
void \mbox{\hyperlink{mlx5fpga__core_8c_a49a3eff4bbee6fb57569a40e1f99e515}{mlx5\+\_\+fpga\+\_\+cleanup}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$mdev)
\item 
static const char $\ast$ \mbox{\hyperlink{mlx5fpga__core_8c_af82fad5ef524463d68565be4fe334c91}{mlx5\+\_\+fpga\+\_\+syndrome\+\_\+to\+\_\+string}} (u8 syndrome)
\item 
static const char $\ast$ \mbox{\hyperlink{mlx5fpga__core_8c_af0ea1abf4e2393e85fad3c387297b904}{mlx5\+\_\+fpga\+\_\+qp\+\_\+syndrome\+\_\+to\+\_\+string}} (u8 syndrome)
\item 
void \mbox{\hyperlink{mlx5fpga__core_8c_ac3de9a8d23b331cb5b18af8fc134a7be}{mlx5\+\_\+fpga\+\_\+event}} (struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$mdev, u8 event, void $\ast$\mbox{\hyperlink{mlx5__en__tx_8c_af943c26117683b64b9cd6943e2c496e5}{data}})
\item 
void \mbox{\hyperlink{mlx5fpga__core_8c_ae51eae27ad348ffebb68719be9f5fb7e}{mlx5\+\_\+fpga\+\_\+client\+\_\+register}} (struct \mbox{\hyperlink{structmlx5__fpga__client}{mlx5\+\_\+fpga\+\_\+client}} $\ast$client)
\item 
\mbox{\hyperlink{mlx5fpga__core_8c_a67116086ae3d8755c816a978fd9ed350}{EXPORT\+\_\+\+SYMBOL}} (\mbox{\hyperlink{sdk_8h_ae51eae27ad348ffebb68719be9f5fb7e}{mlx5\+\_\+fpga\+\_\+client\+\_\+register}})
\item 
void \mbox{\hyperlink{mlx5fpga__core_8c_a894ca632c7439cf1a3fbb660aaf7082c}{mlx5\+\_\+fpga\+\_\+client\+\_\+unregister}} (struct \mbox{\hyperlink{structmlx5__fpga__client}{mlx5\+\_\+fpga\+\_\+client}} $\ast$client)
\item 
\mbox{\hyperlink{mlx5fpga__core_8c_a0bf49ddfbecbd19e1a96d3066d01ca98}{EXPORT\+\_\+\+SYMBOL}} (\mbox{\hyperlink{sdk_8h_a894ca632c7439cf1a3fbb660aaf7082c}{mlx5\+\_\+fpga\+\_\+client\+\_\+unregister}})
\item 
\mbox{\hyperlink{mlx5fpga__core_8c_ac3bb79d9a2f1463df40e405a6a1277ec}{MODULE\+\_\+\+DEPEND}} (mlx5fpga, mlx5, 1, 1, 1)
\item 
\mbox{\hyperlink{mlx5fpga__core_8c_ac3410a6a1d3ea67ff52b06d0e2f08c80}{MODULE\+\_\+\+VERSION}} (mlx5fpga, 1)
\end{DoxyCompactItemize}
\doxysubsection*{Variables}
\begin{DoxyCompactItemize}
\item 
static const char $\ast$const \mbox{\hyperlink{mlx5fpga__core_8c_af228d7227ea6e34103c149c4f87851a6}{mlx5\+\_\+fpga\+\_\+error\+\_\+strings}} \mbox{[}$\,$\mbox{]}
\item 
static const char $\ast$const \mbox{\hyperlink{mlx5fpga__core_8c_a22b1ac2776b0cf5b7a58ee2db9547f94}{mlx5\+\_\+fpga\+\_\+qp\+\_\+error\+\_\+strings}} \mbox{[}$\,$\mbox{]}
\end{DoxyCompactItemize}


\doxysubsection{Function Documentation}
\mbox{\Hypertarget{mlx5fpga__core_8c_a9dfd61401e9663fd2d55b375560ef1b1}\label{mlx5fpga__core_8c_a9dfd61401e9663fd2d55b375560ef1b1}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!client\_context\_create@{client\_context\_create}}
\index{client\_context\_create@{client\_context\_create}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{client\_context\_create()}{client\_context\_create()}}
{\footnotesize\ttfamily static int client\+\_\+context\+\_\+create (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev,  }\item[{struct \mbox{\hyperlink{structmlx5__fpga__client}{mlx5\+\_\+fpga\+\_\+client}} $\ast$}]{client,  }\item[{struct mlx5\+\_\+fpga\+\_\+client\+\_\+data $\ast$$\ast$}]{pctx }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00077}{77}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{sdk_8h_source_l00066}{mlx5\+\_\+fpga\+\_\+client\+::create}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00507}{mlx5\+\_\+fpga\+\_\+client\+\_\+register()}}, and \mbox{\hyperlink{mlx5fpga__core_8c_source_l00332}{mlx5\+\_\+fpga\+\_\+init()}}.

Here is the caller graph for this function\+:
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\begin{center}
\leavevmode
\includegraphics[width=350pt]{d0/d88/mlx5fpga__core_8c_a9dfd61401e9663fd2d55b375560ef1b1_icgraph}
\end{center}
\end{figure}
\mbox{\Hypertarget{mlx5fpga__core_8c_aaec7f22375d6ef5df787d1fbfa9f7901}\label{mlx5fpga__core_8c_aaec7f22375d6ef5df787d1fbfa9f7901}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!client\_context\_destroy@{client\_context\_destroy}}
\index{client\_context\_destroy@{client\_context\_destroy}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{client\_context\_destroy()}{client\_context\_destroy()}}
{\footnotesize\ttfamily static void client\+\_\+context\+\_\+destroy (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev,  }\item[{struct mlx5\+\_\+fpga\+\_\+client\+\_\+data $\ast$}]{context }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00066}{66}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00418}{mlx5\+\_\+fpga\+\_\+cleanup()}}, and \mbox{\hyperlink{mlx5fpga__core_8c_source_l00544}{mlx5\+\_\+fpga\+\_\+client\+\_\+unregister()}}.

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\begin{center}
\leavevmode
\includegraphics[width=350pt]{d0/d88/mlx5fpga__core_8c_aaec7f22375d6ef5df787d1fbfa9f7901_icgraph}
\end{center}
\end{figure}
\mbox{\Hypertarget{mlx5fpga__core_8c_a5c9182a9e2672cdd28bc73f1fc8250f6}\label{mlx5fpga__core_8c_a5c9182a9e2672cdd28bc73f1fc8250f6}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!DEFINE\_MUTEX@{DEFINE\_MUTEX}}
\index{DEFINE\_MUTEX@{DEFINE\_MUTEX}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{DEFINE\_MUTEX()}{DEFINE\_MUTEX()}}
{\footnotesize\ttfamily static DEFINE\+\_\+\+MUTEX (\begin{DoxyParamCaption}\item[{mlx5\+\_\+fpga\+\_\+mutex}]{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}

\mbox{\Hypertarget{mlx5fpga__core_8c_a67116086ae3d8755c816a978fd9ed350}\label{mlx5fpga__core_8c_a67116086ae3d8755c816a978fd9ed350}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!EXPORT\_SYMBOL@{EXPORT\_SYMBOL}}
\index{EXPORT\_SYMBOL@{EXPORT\_SYMBOL}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{EXPORT\_SYMBOL()}{EXPORT\_SYMBOL()}\hspace{0.1cm}{\footnotesize\ttfamily [1/2]}}
{\footnotesize\ttfamily EXPORT\+\_\+\+SYMBOL (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{sdk_8h_ae51eae27ad348ffebb68719be9f5fb7e}{mlx5\+\_\+fpga\+\_\+client\+\_\+register}}}]{ }\end{DoxyParamCaption})}

\mbox{\Hypertarget{mlx5fpga__core_8c_a0bf49ddfbecbd19e1a96d3066d01ca98}\label{mlx5fpga__core_8c_a0bf49ddfbecbd19e1a96d3066d01ca98}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!EXPORT\_SYMBOL@{EXPORT\_SYMBOL}}
\index{EXPORT\_SYMBOL@{EXPORT\_SYMBOL}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{EXPORT\_SYMBOL()}{EXPORT\_SYMBOL()}\hspace{0.1cm}{\footnotesize\ttfamily [2/2]}}
{\footnotesize\ttfamily EXPORT\+\_\+\+SYMBOL (\begin{DoxyParamCaption}\item[{\mbox{\hyperlink{sdk_8h_a894ca632c7439cf1a3fbb660aaf7082c}{mlx5\+\_\+fpga\+\_\+client\+\_\+unregister}}}]{ }\end{DoxyParamCaption})}

\mbox{\Hypertarget{mlx5fpga__core_8c_aa9d3a2c4dd94196630512d800e34dd4d}\label{mlx5fpga__core_8c_aa9d3a2c4dd94196630512d800e34dd4d}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!LIST\_HEAD@{LIST\_HEAD}}
\index{LIST\_HEAD@{LIST\_HEAD}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{LIST\_HEAD()}{LIST\_HEAD()}\hspace{0.1cm}{\footnotesize\ttfamily [1/2]}}
{\footnotesize\ttfamily static LIST\+\_\+\+HEAD (\begin{DoxyParamCaption}\item[{mlx5\+\_\+fpga\+\_\+clients}]{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}

\mbox{\Hypertarget{mlx5fpga__core_8c_ab053fbb838d2d88133c0d4b5469e8984}\label{mlx5fpga__core_8c_ab053fbb838d2d88133c0d4b5469e8984}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!LIST\_HEAD@{LIST\_HEAD}}
\index{LIST\_HEAD@{LIST\_HEAD}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{LIST\_HEAD()}{LIST\_HEAD()}\hspace{0.1cm}{\footnotesize\ttfamily [2/2]}}
{\footnotesize\ttfamily static LIST\+\_\+\+HEAD (\begin{DoxyParamCaption}\item[{mlx5\+\_\+fpga\+\_\+devices}]{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}

\mbox{\Hypertarget{mlx5fpga__core_8c_a49a3eff4bbee6fb57569a40e1f99e515}\label{mlx5fpga__core_8c_a49a3eff4bbee6fb57569a40e1f99e515}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_cleanup@{mlx5\_fpga\_cleanup}}
\index{mlx5\_fpga\_cleanup@{mlx5\_fpga\_cleanup}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_cleanup()}{mlx5\_fpga\_cleanup()}}
{\footnotesize\ttfamily void mlx5\+\_\+fpga\+\_\+cleanup (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{mdev }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00418}{418}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{mlx5fpga__core_8c_source_l00066}{client\+\_\+context\+\_\+destroy()}}, \mbox{\hyperlink{driver_8h_source_l00670}{mlx5\+\_\+core\+\_\+dev\+::fpga}}, and \mbox{\hyperlink{mlx5fpga__core_8c_source_l00361}{mlx5\+\_\+fpga\+\_\+device\+\_\+stop()}}.



Referenced by \mbox{\hyperlink{mlx5__main_8c_source_l01021}{mlx5\+\_\+cleanup\+\_\+once()}}.

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\mbox{\Hypertarget{mlx5fpga__core_8c_ae51eae27ad348ffebb68719be9f5fb7e}\label{mlx5fpga__core_8c_ae51eae27ad348ffebb68719be9f5fb7e}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_client\_register@{mlx5\_fpga\_client\_register}}
\index{mlx5\_fpga\_client\_register@{mlx5\_fpga\_client\_register}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_client\_register()}{mlx5\_fpga\_client\_register()}}
{\footnotesize\ttfamily void mlx5\+\_\+fpga\+\_\+client\+\_\+register (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__fpga__client}{mlx5\+\_\+fpga\+\_\+client}} $\ast$}]{client }\end{DoxyParamCaption})}

\mbox{\hyperlink{sdk_8h_ae51eae27ad348ffebb68719be9f5fb7e}{mlx5\+\_\+fpga\+\_\+client\+\_\+register()}} -\/ Register a client driver @client\+: The properties of the client driver

Should be called from a client driver\textquotesingle{}s module init routine. Note\+: The core will immediately callback create() and add() for any existing devices in the system, as well as new ones added later on. 

Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00507}{507}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{sdk_8h_source_l00075}{mlx5\+\_\+fpga\+\_\+client\+::add}}, \mbox{\hyperlink{mlx5fpga__core_8c_source_l00077}{client\+\_\+context\+\_\+create()}}, \mbox{\hyperlink{sdk_8h_source_l00093}{mlx5\+\_\+fpga\+\_\+client\+::list}}, \mbox{\hyperlink{device_8h_source_l01158}{MLX5\+\_\+\+CAP\+\_\+\+FPGA}}, and \mbox{\hyperlink{sdk_8h_source_l00091}{mlx5\+\_\+fpga\+\_\+client\+::name}}.



Referenced by \mbox{\hyperlink{mlx5fpga__tools__main_8c_source_l00126}{mlx5\+\_\+fpga\+\_\+tools\+\_\+init()}}.

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\mbox{\Hypertarget{mlx5fpga__core_8c_a894ca632c7439cf1a3fbb660aaf7082c}\label{mlx5fpga__core_8c_a894ca632c7439cf1a3fbb660aaf7082c}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_client\_unregister@{mlx5\_fpga\_client\_unregister}}
\index{mlx5\_fpga\_client\_unregister@{mlx5\_fpga\_client\_unregister}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_client\_unregister()}{mlx5\_fpga\_client\_unregister()}}
{\footnotesize\ttfamily void mlx5\+\_\+fpga\+\_\+client\+\_\+unregister (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__fpga__client}{mlx5\+\_\+fpga\+\_\+client}} $\ast$}]{client }\end{DoxyParamCaption})}

\mbox{\hyperlink{sdk_8h_a894ca632c7439cf1a3fbb660aaf7082c}{mlx5\+\_\+fpga\+\_\+client\+\_\+unregister()}} -\/ Unregister a client driver @client\+: The client driver to unregister

Should be called from a client driver\textquotesingle{}s module exit routine. Note\+: The core will immediately callback delete() and destroy() for any created/added devices in the system, to clean up their state. 

Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00544}{544}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{mlx5fpga__core_8c_source_l00066}{client\+\_\+context\+\_\+destroy()}}, \mbox{\hyperlink{sdk_8h_source_l00093}{mlx5\+\_\+fpga\+\_\+client\+::list}}, \mbox{\hyperlink{sdk_8h_source_l00091}{mlx5\+\_\+fpga\+\_\+client\+::name}}, and \mbox{\hyperlink{sdk_8h_source_l00083}{mlx5\+\_\+fpga\+\_\+client\+::remove}}.



Referenced by \mbox{\hyperlink{mlx5fpga__tools__main_8c_source_l00136}{mlx5\+\_\+fpga\+\_\+tools\+\_\+exit()}}.

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\mbox{\Hypertarget{mlx5fpga__core_8c_ab39214501cab61757485e78305f880c1}\label{mlx5fpga__core_8c_ab39214501cab61757485e78305f880c1}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_device\_alloc@{mlx5\_fpga\_device\_alloc}}
\index{mlx5\_fpga\_device\_alloc@{mlx5\_fpga\_device\_alloc}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_device\_alloc()}{mlx5\_fpga\_device\_alloc()}}
{\footnotesize\ttfamily static struct mlx5\+\_\+fpga\+\_\+device $\ast$ mlx5\+\_\+fpga\+\_\+device\+\_\+alloc (\begin{DoxyParamCaption}\item[{void}]{ }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00103}{103}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00332}{mlx5\+\_\+fpga\+\_\+init()}}.

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\mbox{\Hypertarget{mlx5fpga__core_8c_ab4ed01984c3cae90135b2d7ba9215fca}\label{mlx5fpga__core_8c_ab4ed01984c3cae90135b2d7ba9215fca}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_device\_brb@{mlx5\_fpga\_device\_brb}}
\index{mlx5\_fpga\_device\_brb@{mlx5\_fpga\_device\_brb}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_device\_brb()}{mlx5\_fpga\_device\_brb()}}
{\footnotesize\ttfamily static int mlx5\+\_\+fpga\+\_\+device\+\_\+brb (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00183}{183}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00084}{mlx5\+\_\+fpga\+\_\+ctrl\+\_\+op()}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00135}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+RESET\+\_\+\+SANDBOX}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00134}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+SANDBOX\+\_\+\+BYPASS\+\_\+\+OFF}}, and \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00133}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+SANDBOX\+\_\+\+BYPASS\+\_\+\+ON}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00206}{mlx5\+\_\+fpga\+\_\+device\+\_\+start()}}.

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\includegraphics[width=350pt]{d0/d88/mlx5fpga__core_8c_ab4ed01984c3cae90135b2d7ba9215fca_cgraph}
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\mbox{\Hypertarget{mlx5fpga__core_8c_a2626d510b71bc7fe69fda5f5cc5e13b8}\label{mlx5fpga__core_8c_a2626d510b71bc7fe69fda5f5cc5e13b8}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_device\_load\_check@{mlx5\_fpga\_device\_load\_check}}
\index{mlx5\_fpga\_device\_load\_check@{mlx5\_fpga\_device\_load\_check}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_device\_load\_check()}{mlx5\_fpga\_device\_load\_check()}}
{\footnotesize\ttfamily static int mlx5\+\_\+fpga\+\_\+device\+\_\+load\+\_\+check (\begin{DoxyParamCaption}\item[{struct mlx5\+\_\+fpga\+\_\+device $\ast$}]{fdev }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00149}{149}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{mlx5io_8h_source_l00099}{mlx5\+\_\+fpga\+\_\+query\+::admin\+\_\+image}}, \mbox{\hyperlink{mlx5io_8h_source_l00101}{mlx5\+\_\+fpga\+\_\+query\+::image\+\_\+status}}, \mbox{\hyperlink{device_8h_source_l01158}{MLX5\+\_\+\+CAP\+\_\+\+FPGA}}, \mbox{\hyperlink{mlx5fpga__core_8c_source_l00118}{mlx5\+\_\+fpga\+\_\+image\+\_\+name()}}, \mbox{\hyperlink{mlx5io_8h_source_l00079}{MLX5\+\_\+\+FPGA\+\_\+\+MORSE}}, \mbox{\hyperlink{mlx5io_8h_source_l00080}{MLX5\+\_\+\+FPGA\+\_\+\+MORSEQ}}, \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00151}{mlx5\+\_\+fpga\+\_\+query()}}, \mbox{\hyperlink{mlx5io_8h_source_l00092}{MLX5\+\_\+\+FPGA\+\_\+\+STATUS\+\_\+\+SUCCESS}}, and \mbox{\hyperlink{mlx5io_8h_source_l00100}{mlx5\+\_\+fpga\+\_\+query\+::oper\+\_\+image}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00206}{mlx5\+\_\+fpga\+\_\+device\+\_\+start()}}.

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\includegraphics[width=350pt]{d0/d88/mlx5fpga__core_8c_a2626d510b71bc7fe69fda5f5cc5e13b8_cgraph}
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\begin{center}
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\includegraphics[width=350pt]{d0/d88/mlx5fpga__core_8c_a2626d510b71bc7fe69fda5f5cc5e13b8_icgraph}
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\end{figure}
\mbox{\Hypertarget{mlx5fpga__core_8c_a8886feccc56646d230e8988127c262eb}\label{mlx5fpga__core_8c_a8886feccc56646d230e8988127c262eb}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_device\_start@{mlx5\_fpga\_device\_start}}
\index{mlx5\_fpga\_device\_start@{mlx5\_fpga\_device\_start}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_device\_start()}{mlx5\_fpga\_device\_start()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+device\+\_\+start (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{mdev }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00206}{206}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{sdk_8h_source_l00151}{mlx5\+\_\+fpga\+\_\+conn\+\_\+attr\+::cb\+\_\+arg}}, \mbox{\hyperlink{conn_8h_source_l00046}{mlx5\+\_\+fpga\+\_\+conn\+::fdev}}, \mbox{\hyperlink{driver_8h_source_l00670}{mlx5\+\_\+core\+\_\+dev\+::fpga}}, \mbox{\hyperlink{device_8h_source_l01158}{MLX5\+\_\+\+CAP\+\_\+\+FPGA}}, \mbox{\hyperlink{mlx5__gid_8c_source_l00057}{mlx5\+\_\+core\+\_\+reserve\+\_\+gids()}}, \mbox{\hyperlink{mlx5__gid_8c_source_l00081}{mlx5\+\_\+core\+\_\+unreserve\+\_\+gids()}}, \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00075}{mlx5\+\_\+fpga\+\_\+caps()}}, \mbox{\hyperlink{mlx5fpga__conn_8c_source_l00844}{mlx5\+\_\+fpga\+\_\+conn\+\_\+create()}}, \mbox{\hyperlink{mlx5fpga__conn_8c_source_l00966}{mlx5\+\_\+fpga\+\_\+conn\+\_\+destroy()}}, \mbox{\hyperlink{mlx5fpga__conn_8c_source_l01036}{mlx5\+\_\+fpga\+\_\+conn\+\_\+device\+\_\+cleanup()}}, \mbox{\hyperlink{mlx5fpga__conn_8c_source_l00990}{mlx5\+\_\+fpga\+\_\+conn\+\_\+device\+\_\+init()}}, \mbox{\hyperlink{mlx5fpga__core_8c_source_l00183}{mlx5\+\_\+fpga\+\_\+device\+\_\+brb()}}, \mbox{\hyperlink{mlx5fpga__core_8c_source_l00149}{mlx5\+\_\+fpga\+\_\+device\+\_\+load\+\_\+check()}}, \mbox{\hyperlink{mlx5fpga__core_8c_source_l00118}{mlx5\+\_\+fpga\+\_\+image\+\_\+name()}}, \mbox{\hyperlink{mlx5io_8h_source_l00084}{MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+USER}}, \mbox{\hyperlink{mlx5io_8h_source_l00079}{MLX5\+\_\+\+FPGA\+\_\+\+MORSE}}, \mbox{\hyperlink{mlx5io_8h_source_l00080}{MLX5\+\_\+\+FPGA\+\_\+\+MORSEQ}}, \mbox{\hyperlink{mlx5fpga__core_8c_source_l00130}{mlx5\+\_\+fpga\+\_\+name()}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00194}{MLX5\+\_\+\+FPGA\+\_\+\+QPC\+\_\+\+QP\+\_\+\+TYPE\+\_\+\+SHELL\+\_\+\+QP}}, \mbox{\hyperlink{trans_8h_source_l00044}{MLX5\+\_\+\+FPGA\+\_\+\+TID\+\_\+\+COUNT}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00332}{mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+cleanup()}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00308}{mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+init()}}, \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00245}{mlx5\+\_\+fpga\+\_\+trans\+\_\+recv()}}, \mbox{\hyperlink{sdk_8h_source_l00150}{mlx5\+\_\+fpga\+\_\+conn\+\_\+attr\+::recv\+\_\+cb}}, \mbox{\hyperlink{sdk_8h_source_l00139}{mlx5\+\_\+fpga\+\_\+conn\+\_\+attr\+::rx\+\_\+size}}, and \mbox{\hyperlink{sdk_8h_source_l00137}{mlx5\+\_\+fpga\+\_\+conn\+\_\+attr\+::tx\+\_\+size}}.



Referenced by \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00366}{mlx5\+\_\+fpga\+\_\+device\+\_\+reload()}}, \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00327}{mlx5\+\_\+fpga\+\_\+device\+\_\+reload\+\_\+cmd()}}, and \mbox{\hyperlink{mlx5__main_8c_source_l01035}{mlx5\+\_\+load\+\_\+one()}}.

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\mbox{\Hypertarget{mlx5fpga__core_8c_abf23345b773352ccf0a2b234bdf45bde}\label{mlx5fpga__core_8c_abf23345b773352ccf0a2b234bdf45bde}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_device\_stop@{mlx5\_fpga\_device\_stop}}
\index{mlx5\_fpga\_device\_stop@{mlx5\_fpga\_device\_stop}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_device\_stop()}{mlx5\_fpga\_device\_stop()}}
{\footnotesize\ttfamily void mlx5\+\_\+fpga\+\_\+device\+\_\+stop (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{mdev }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00361}{361}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{driver_8h_source_l00670}{mlx5\+\_\+core\+\_\+dev\+::fpga}}, \mbox{\hyperlink{device_8h_source_l01158}{MLX5\+\_\+\+CAP\+\_\+\+FPGA}}, \mbox{\hyperlink{mlx5__gid_8c_source_l00081}{mlx5\+\_\+core\+\_\+unreserve\+\_\+gids()}}, \mbox{\hyperlink{mlx5fpga__conn_8c_source_l00966}{mlx5\+\_\+fpga\+\_\+conn\+\_\+destroy()}}, \mbox{\hyperlink{mlx5fpga__conn_8c_source_l01036}{mlx5\+\_\+fpga\+\_\+conn\+\_\+device\+\_\+cleanup()}}, \mbox{\hyperlink{mlx5fpga__cmd_8c_source_l00084}{mlx5\+\_\+fpga\+\_\+ctrl\+\_\+op()}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00133}{MLX5\+\_\+\+FPGA\+\_\+\+CTRL\+\_\+\+OPERATION\+\_\+\+SANDBOX\+\_\+\+BYPASS\+\_\+\+ON}}, \mbox{\hyperlink{mlx5io_8h_source_l00084}{MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+USER}}, \mbox{\hyperlink{mlx5io_8h_source_l00079}{MLX5\+\_\+\+FPGA\+\_\+\+MORSE}}, \mbox{\hyperlink{mlx5io_8h_source_l00080}{MLX5\+\_\+\+FPGA\+\_\+\+MORSEQ}}, and \mbox{\hyperlink{mlx5fpga__trans_8c_source_l00332}{mlx5\+\_\+fpga\+\_\+trans\+\_\+device\+\_\+cleanup()}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00418}{mlx5\+\_\+fpga\+\_\+cleanup()}}, \mbox{\hyperlink{mlx5fpga__sdk_8c_source_l00366}{mlx5\+\_\+fpga\+\_\+device\+\_\+reload()}}, \mbox{\hyperlink{mlx5__main_8c_source_l01035}{mlx5\+\_\+load\+\_\+one()}}, and \mbox{\hyperlink{mlx5__main_8c_source_l01256}{mlx5\+\_\+unload\+\_\+one()}}.

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\includegraphics[width=350pt]{d0/d88/mlx5fpga__core_8c_abf23345b773352ccf0a2b234bdf45bde_cgraph}
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\mbox{\Hypertarget{mlx5fpga__core_8c_ac3de9a8d23b331cb5b18af8fc134a7be}\label{mlx5fpga__core_8c_ac3de9a8d23b331cb5b18af8fc134a7be}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_event@{mlx5\_fpga\_event}}
\index{mlx5\_fpga\_event@{mlx5\_fpga\_event}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_event()}{mlx5\_fpga\_event()}}
{\footnotesize\ttfamily void mlx5\+\_\+fpga\+\_\+event (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{mdev,  }\item[{u8}]{event,  }\item[{void $\ast$}]{data }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00454}{454}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{mlx5__en__tx_8c_source_l00001}{data}}, \mbox{\hyperlink{driver_8h_source_l00670}{mlx5\+\_\+core\+\_\+dev\+::fpga}}, \mbox{\hyperlink{mlx5__ifc_8h_source_l00066}{MLX5\+\_\+\+EVENT\+\_\+\+TYPE\+\_\+\+FPGA\+\_\+\+ERROR}}, \mbox{\hyperlink{mlx5__ifc_8h_source_l00067}{MLX5\+\_\+\+EVENT\+\_\+\+TYPE\+\_\+\+FPGA\+\_\+\+QP\+\_\+\+ERROR}}, \mbox{\hyperlink{mlx5__ifc__fpga_8h_source_l00161}{MLX5\+\_\+\+FPGA\+\_\+\+ERROR\+\_\+\+EVENT\+\_\+\+SYNDROME\+\_\+\+IMAGE\+\_\+\+CHANGED}}, \mbox{\hyperlink{mlx5fpga__core_8c_source_l00447}{mlx5\+\_\+fpga\+\_\+qp\+\_\+syndrome\+\_\+to\+\_\+string()}}, \mbox{\hyperlink{mlx5fpga__core_8c_source_l00440}{mlx5\+\_\+fpga\+\_\+syndrome\+\_\+to\+\_\+string()}}, \mbox{\hyperlink{device_8h_source_l00091}{MLX5\+\_\+\+GET}}, and \mbox{\hyperlink{mlx5__health_8c_source_l00461}{mlx5\+\_\+trigger\+\_\+health\+\_\+work()}}.



Referenced by \mbox{\hyperlink{mlx5__eq_8c_source_l00230}{mlx5\+\_\+eq\+\_\+int()}}.

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\includegraphics[width=350pt]{d0/d88/mlx5fpga__core_8c_ac3de9a8d23b331cb5b18af8fc134a7be_cgraph}
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\includegraphics[width=350pt]{d0/d88/mlx5fpga__core_8c_ac3de9a8d23b331cb5b18af8fc134a7be_icgraph}
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\end{figure}
\mbox{\Hypertarget{mlx5fpga__core_8c_a3a0d25f677c9c7a97f10ed67e06266e5}\label{mlx5fpga__core_8c_a3a0d25f677c9c7a97f10ed67e06266e5}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_image\_name@{mlx5\_fpga\_image\_name}}
\index{mlx5\_fpga\_image\_name@{mlx5\_fpga\_image\_name}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_image\_name()}{mlx5\_fpga\_image\_name()}}
{\footnotesize\ttfamily static const char $\ast$ mlx5\+\_\+fpga\+\_\+image\+\_\+name (\begin{DoxyParamCaption}\item[{enum \mbox{\hyperlink{mlx5io_8h_abd09d1f785591c0ccc8fe9e49fd49303}{mlx5\+\_\+fpga\+\_\+image}}}]{image }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00118}{118}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{mlx5io_8h_source_l00085}{MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+FACTORY}}, and \mbox{\hyperlink{mlx5io_8h_source_l00084}{MLX5\+\_\+\+FPGA\+\_\+\+IMAGE\+\_\+\+USER}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00149}{mlx5\+\_\+fpga\+\_\+device\+\_\+load\+\_\+check()}}, and \mbox{\hyperlink{mlx5fpga__core_8c_source_l00206}{mlx5\+\_\+fpga\+\_\+device\+\_\+start()}}.

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\includegraphics[width=350pt]{d0/d88/mlx5fpga__core_8c_a3a0d25f677c9c7a97f10ed67e06266e5_icgraph}
\end{center}
\end{figure}
\mbox{\Hypertarget{mlx5fpga__core_8c_a9d7ab99958d10ee555818f2a59c6bd5a}\label{mlx5fpga__core_8c_a9d7ab99958d10ee555818f2a59c6bd5a}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_init@{mlx5\_fpga\_init}}
\index{mlx5\_fpga\_init@{mlx5\_fpga\_init}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_init()}{mlx5\_fpga\_init()}}
{\footnotesize\ttfamily int mlx5\+\_\+fpga\+\_\+init (\begin{DoxyParamCaption}\item[{struct \mbox{\hyperlink{structmlx5__core__dev}{mlx5\+\_\+core\+\_\+dev}} $\ast$}]{mdev }\end{DoxyParamCaption})}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00332}{332}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{mlx5fpga__core_8c_source_l00077}{client\+\_\+context\+\_\+create()}}, \mbox{\hyperlink{driver_8h_source_l00670}{mlx5\+\_\+core\+\_\+dev\+::fpga}}, \mbox{\hyperlink{sdk_8h_source_l00093}{mlx5\+\_\+fpga\+\_\+client\+::list}}, \mbox{\hyperlink{device_8h_source_l01027}{MLX5\+\_\+\+CAP\+\_\+\+GEN}}, \mbox{\hyperlink{mlx5__core_8h_source_l00045}{mlx5\+\_\+core\+\_\+dbg}}, and \mbox{\hyperlink{mlx5fpga__core_8c_source_l00103}{mlx5\+\_\+fpga\+\_\+device\+\_\+alloc()}}.



Referenced by \mbox{\hyperlink{mlx5__main_8c_source_l00956}{mlx5\+\_\+init\+\_\+once()}}.

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\includegraphics[width=339pt]{d0/d88/mlx5fpga__core_8c_a9d7ab99958d10ee555818f2a59c6bd5a_cgraph}
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\includegraphics[width=350pt]{d0/d88/mlx5fpga__core_8c_a9d7ab99958d10ee555818f2a59c6bd5a_icgraph}
\end{center}
\end{figure}
\mbox{\Hypertarget{mlx5fpga__core_8c_a5ce39b9eda48c1cb615c0df76ab552a9}\label{mlx5fpga__core_8c_a5ce39b9eda48c1cb615c0df76ab552a9}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_name@{mlx5\_fpga\_name}}
\index{mlx5\_fpga\_name@{mlx5\_fpga\_name}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_name()}{mlx5\_fpga\_name()}}
{\footnotesize\ttfamily static const char $\ast$ mlx5\+\_\+fpga\+\_\+name (\begin{DoxyParamCaption}\item[{u32}]{fpga\+\_\+id }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00130}{130}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{mlx5io_8h_source_l00078}{MLX5\+\_\+\+FPGA\+\_\+\+EDISON}}, \mbox{\hyperlink{mlx5io_8h_source_l00079}{MLX5\+\_\+\+FPGA\+\_\+\+MORSE}}, \mbox{\hyperlink{mlx5io_8h_source_l00080}{MLX5\+\_\+\+FPGA\+\_\+\+MORSEQ}}, and \mbox{\hyperlink{mlx5io_8h_source_l00077}{MLX5\+\_\+\+FPGA\+\_\+\+NEWTON}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00206}{mlx5\+\_\+fpga\+\_\+device\+\_\+start()}}.

Here is the caller graph for this function\+:
\nopagebreak
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\begin{center}
\leavevmode
\includegraphics[width=350pt]{d0/d88/mlx5fpga__core_8c_a5ce39b9eda48c1cb615c0df76ab552a9_icgraph}
\end{center}
\end{figure}
\mbox{\Hypertarget{mlx5fpga__core_8c_af0ea1abf4e2393e85fad3c387297b904}\label{mlx5fpga__core_8c_af0ea1abf4e2393e85fad3c387297b904}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_qp\_syndrome\_to\_string@{mlx5\_fpga\_qp\_syndrome\_to\_string}}
\index{mlx5\_fpga\_qp\_syndrome\_to\_string@{mlx5\_fpga\_qp\_syndrome\_to\_string}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_qp\_syndrome\_to\_string()}{mlx5\_fpga\_qp\_syndrome\_to\_string()}}
{\footnotesize\ttfamily static const char $\ast$ mlx5\+\_\+fpga\+\_\+qp\+\_\+syndrome\+\_\+to\+\_\+string (\begin{DoxyParamCaption}\item[{u8}]{syndrome }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00447}{447}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{mlx5fpga__core_8c_source_l00060}{mlx5\+\_\+fpga\+\_\+qp\+\_\+error\+\_\+strings}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00454}{mlx5\+\_\+fpga\+\_\+event()}}.

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\end{figure}
\mbox{\Hypertarget{mlx5fpga__core_8c_af82fad5ef524463d68565be4fe334c91}\label{mlx5fpga__core_8c_af82fad5ef524463d68565be4fe334c91}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_syndrome\_to\_string@{mlx5\_fpga\_syndrome\_to\_string}}
\index{mlx5\_fpga\_syndrome\_to\_string@{mlx5\_fpga\_syndrome\_to\_string}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_syndrome\_to\_string()}{mlx5\_fpga\_syndrome\_to\_string()}}
{\footnotesize\ttfamily static const char $\ast$ mlx5\+\_\+fpga\+\_\+syndrome\+\_\+to\+\_\+string (\begin{DoxyParamCaption}\item[{u8}]{syndrome }\end{DoxyParamCaption})\hspace{0.3cm}{\ttfamily [static]}}



Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00440}{440}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



References \mbox{\hyperlink{mlx5fpga__core_8c_source_l00049}{mlx5\+\_\+fpga\+\_\+error\+\_\+strings}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00454}{mlx5\+\_\+fpga\+\_\+event()}}.

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\includegraphics[width=350pt]{d0/d88/mlx5fpga__core_8c_af82fad5ef524463d68565be4fe334c91_icgraph}
\end{center}
\end{figure}
\mbox{\Hypertarget{mlx5fpga__core_8c_ac3bb79d9a2f1463df40e405a6a1277ec}\label{mlx5fpga__core_8c_ac3bb79d9a2f1463df40e405a6a1277ec}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!MODULE\_DEPEND@{MODULE\_DEPEND}}
\index{MODULE\_DEPEND@{MODULE\_DEPEND}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{MODULE\_DEPEND()}{MODULE\_DEPEND()}}
{\footnotesize\ttfamily MODULE\+\_\+\+DEPEND (\begin{DoxyParamCaption}\item[{mlx5fpga}]{,  }\item[{mlx5}]{,  }\item[{1}]{,  }\item[{1}]{,  }\item[{1}]{ }\end{DoxyParamCaption})}

\mbox{\Hypertarget{mlx5fpga__core_8c_ac3410a6a1d3ea67ff52b06d0e2f08c80}\label{mlx5fpga__core_8c_ac3410a6a1d3ea67ff52b06d0e2f08c80}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!MODULE\_VERSION@{MODULE\_VERSION}}
\index{MODULE\_VERSION@{MODULE\_VERSION}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{MODULE\_VERSION()}{MODULE\_VERSION()}}
{\footnotesize\ttfamily MODULE\+\_\+\+VERSION (\begin{DoxyParamCaption}\item[{mlx5fpga}]{,  }\item[{1}]{ }\end{DoxyParamCaption})}



\doxysubsection{Variable Documentation}
\mbox{\Hypertarget{mlx5fpga__core_8c_af228d7227ea6e34103c149c4f87851a6}\label{mlx5fpga__core_8c_af228d7227ea6e34103c149c4f87851a6}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_error\_strings@{mlx5\_fpga\_error\_strings}}
\index{mlx5\_fpga\_error\_strings@{mlx5\_fpga\_error\_strings}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_error\_strings}{mlx5\_fpga\_error\_strings}}
{\footnotesize\ttfamily const char$\ast$ const mlx5\+\_\+fpga\+\_\+error\+\_\+strings\mbox{[}$\,$\mbox{]}\hspace{0.3cm}{\ttfamily [static]}}

{\bfseries Initial value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{= \{}
\DoxyCodeLine{        \textcolor{stringliteral}{"{}Null Syndrome"{}},}
\DoxyCodeLine{        \textcolor{stringliteral}{"{}Corrupted DDR"{}},}
\DoxyCodeLine{        \textcolor{stringliteral}{"{}Flash Timeout"{}},}
\DoxyCodeLine{        \textcolor{stringliteral}{"{}Internal Link Error"{}},}
\DoxyCodeLine{        \textcolor{stringliteral}{"{}Watchdog HW Failure"{}},}
\DoxyCodeLine{        \textcolor{stringliteral}{"{}I2C Failure"{}},}
\DoxyCodeLine{        \textcolor{stringliteral}{"{}Image Changed"{}},}
\DoxyCodeLine{        \textcolor{stringliteral}{"{}Temperature Critical"{}},}
\DoxyCodeLine{\}}

\end{DoxyCode}


Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00049}{49}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00440}{mlx5\+\_\+fpga\+\_\+syndrome\+\_\+to\+\_\+string()}}.

\mbox{\Hypertarget{mlx5fpga__core_8c_a22b1ac2776b0cf5b7a58ee2db9547f94}\label{mlx5fpga__core_8c_a22b1ac2776b0cf5b7a58ee2db9547f94}} 
\index{mlx5fpga\_core.c@{mlx5fpga\_core.c}!mlx5\_fpga\_qp\_error\_strings@{mlx5\_fpga\_qp\_error\_strings}}
\index{mlx5\_fpga\_qp\_error\_strings@{mlx5\_fpga\_qp\_error\_strings}!mlx5fpga\_core.c@{mlx5fpga\_core.c}}
\doxysubsubsection{\texorpdfstring{mlx5\_fpga\_qp\_error\_strings}{mlx5\_fpga\_qp\_error\_strings}}
{\footnotesize\ttfamily const char$\ast$ const mlx5\+\_\+fpga\+\_\+qp\+\_\+error\+\_\+strings\mbox{[}$\,$\mbox{]}\hspace{0.3cm}{\ttfamily [static]}}

{\bfseries Initial value\+:}
\begin{DoxyCode}{0}
\DoxyCodeLine{= \{}
\DoxyCodeLine{        \textcolor{stringliteral}{"{}Null Syndrome"{}},}
\DoxyCodeLine{        \textcolor{stringliteral}{"{}Retry Counter Expired"{}},}
\DoxyCodeLine{        \textcolor{stringliteral}{"{}RNR Expired"{}},}
\DoxyCodeLine{\}}

\end{DoxyCode}


Definition at line \mbox{\hyperlink{mlx5fpga__core_8c_source_l00060}{60}} of file \mbox{\hyperlink{mlx5fpga__core_8c_source}{mlx5fpga\+\_\+core.\+c}}.



Referenced by \mbox{\hyperlink{mlx5fpga__core_8c_source_l00447}{mlx5\+\_\+fpga\+\_\+qp\+\_\+syndrome\+\_\+to\+\_\+string()}}.

