\hypertarget{lxtphyreg_8h}{}\doxysection{dev/mii/lxtphyreg.h File Reference}
\label{lxtphyreg_8h}\index{dev/mii/lxtphyreg.h@{dev/mii/lxtphyreg.h}}
This graph shows which files directly or indirectly include this file\+:
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\begin{figure}[H]
\begin{center}
\leavevmode
\includegraphics[width=192pt]{d6/d41/lxtphyreg_8h__dep__incl}
\end{center}
\end{figure}
\doxysubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_abcbb774f2c00adb55dc58cabcfdba355}{MII\+\_\+\+LXTPHY\+\_\+\+MIRROR}}~0x10 /$\ast$ Mirror register $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a0093c80420ee3e9b0bef20bab35a2692}{MII\+\_\+\+LXTPHY\+\_\+\+IER}}~0x11 /$\ast$ Interrupt Enable Register $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_acdf17101db781b4b3588e79aedfcc05d}{IER\+\_\+\+MIIDRVLVL}}~0x0008 /$\ast$ Rediced MII driver levels $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_ab99807472dc72d12bf53e0fa0637171e}{IER\+\_\+\+LNK\+\_\+\+CRITERIA}}~0x0004 /$\ast$ Enhanced Link Loss Criteria $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_aec24dc69078e5c54365c35013c7ea8a3}{IER\+\_\+\+INTEN}}~0x0002 /$\ast$ Interrupt Enable $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a2b7452859006cbaaeba913fcfb11e5c4}{IER\+\_\+\+TINT}}~0x0001 /$\ast$ Force Interrupt $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a737d21111a0121124474ae2d023bfc09}{MII\+\_\+\+LXTPHY\+\_\+\+ISR}}~0x12 /$\ast$ Interrupt Status Register $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_ada01d4f52eb2b980d547eba00f35f404}{ISR\+\_\+\+MINT}}~0x8000 /$\ast$ MII Interrupt Pending $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_af20621420d1461f1c70f256e8f7b5daf}{ISR\+\_\+\+XTALOK}}~0x4000 /$\ast$ Clocks OK $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a79a0ecfa68fb4a8ffb6d9fbd7ba5993d}{MII\+\_\+\+LXTPHY\+\_\+\+CONFIG}}~0x13 /$\ast$ Configuration Register $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a20bacab53a9293fbde93a077e6c7b1b0}{CONFIG\+\_\+\+TXMIT\+\_\+\+TEST}}~0x4000 /$\ast$ 100base-\/T Transmit Test $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a268a10df903aa62182f10c96fea3bdeb}{CONFIG\+\_\+\+REPEATER}}~0x2000 /$\ast$ Repeater Mode $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_ac839ed4ef795877c0cfd4fb68b1ee53b}{CONFIG\+\_\+\+MDIO\+\_\+\+INT}}~0x1000 /$\ast$ Enable intr signalling on MDIO $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a0306aba5e57d49fb8be4d910223a9c26}{CONFIG\+\_\+\+TPLOOP}}~0x0800 /$\ast$ Disable 10base-\/T Loopback $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a1e0186d96d36933f7f9d9678c85e0457}{CONFIG\+\_\+\+SQE}}~0x0400 /$\ast$ Enable SQE $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a1b3025e3a27b112181668dc9bf4669f4}{CONFIG\+\_\+\+DISJABBER}}~0x0200 /$\ast$ Disable Jabber $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a33aabb2bf1f84c201f2a530b90fb0d23}{CONFIG\+\_\+\+DISLINKTEST}}~0x0100 /$\ast$ Disable Link Test $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_ab9916d29f7f3c0ce61e03993c3427a18}{CONFIG\+\_\+\+LEDC1}}~0x0080 /$\ast$ LEDC configuration $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_ac9243cd5917bfb1298c999015f27735a}{CONFIG\+\_\+\+LEDC0}}~0x0040 /$\ast$ ... $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a8bb04637edd20caffd6d2549d1bbf514}{CONFIG\+\_\+\+ADVTXCLK}}~0x0020 /$\ast$ Advance TX clock $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a2f9e59007a6d07cba6d17d6d9fd77929}{CONFIG\+\_\+5\+BSYMBOL}}~0x0010 /$\ast$ 5-\/bit Symbol mode $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a2cc0dac1833de325d06b5c3b564e5b3c}{CONFIG\+\_\+\+SCRAMBLER}}~0x0008 /$\ast$ Bypass scrambler $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a23d310dd56410ff56a857d5ddfd573f4}{CONFIG\+\_\+100\+BASEFX}}~0x0004 /$\ast$ 100base-\/FX $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_ad98f41c7dfeb481efc37a3306b60711f}{CONFIG\+\_\+\+TXDISCON}}~0x0001 /$\ast$ Disconnect TP transmitter $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_aebbbaa387a7511507dc51703294a6b67}{MII\+\_\+\+LXTPHY\+\_\+\+CSR}}~0x14 /$\ast$ Chip Status Register $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a51c29dd356cee9fc63f86e7e319c54a5}{CSR\+\_\+\+LINK}}~0x2000 /$\ast$ Link is up $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_aa458953e69deb60c28f7e7837e28b528}{CSR\+\_\+\+DUPLEX}}~0x1000 /$\ast$ Full-\/duplex $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a930c7e7182537108a448ceb230d3111c}{CSR\+\_\+\+SPEED}}~0x0800 /$\ast$ 100\+Mbps $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a834e3d398b9ef5955493636d3f498ca6}{CSR\+\_\+\+ACOMP}}~0x0400 /$\ast$ Autonegotiation complete $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a14ec600cbcd321f3108b189506226f69}{CSR\+\_\+\+PAGERCVD}}~0x0200 /$\ast$ Link page received $\ast$/
\item 
\#define \mbox{\hyperlink{lxtphyreg_8h_a80d776be70ee75949932b8dfe689afbf}{CSR\+\_\+\+LOWVCC}}~0x0004 /$\ast$ Low Voltage Fault $\ast$/
\end{DoxyCompactItemize}


\doxysubsection{Macro Definition Documentation}
\mbox{\Hypertarget{lxtphyreg_8h_a23d310dd56410ff56a857d5ddfd573f4}\label{lxtphyreg_8h_a23d310dd56410ff56a857d5ddfd573f4}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_100BASEFX@{CONFIG\_100BASEFX}}
\index{CONFIG\_100BASEFX@{CONFIG\_100BASEFX}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_100BASEFX}{CONFIG\_100BASEFX}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+100\+BASEFX~0x0004 /$\ast$ 100base-\/FX $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00074}{74}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a2f9e59007a6d07cba6d17d6d9fd77929}\label{lxtphyreg_8h_a2f9e59007a6d07cba6d17d6d9fd77929}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_5BSYMBOL@{CONFIG\_5BSYMBOL}}
\index{CONFIG\_5BSYMBOL@{CONFIG\_5BSYMBOL}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_5BSYMBOL}{CONFIG\_5BSYMBOL}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+5\+BSYMBOL~0x0010 /$\ast$ 5-\/bit Symbol mode $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00072}{72}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a8bb04637edd20caffd6d2549d1bbf514}\label{lxtphyreg_8h_a8bb04637edd20caffd6d2549d1bbf514}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_ADVTXCLK@{CONFIG\_ADVTXCLK}}
\index{CONFIG\_ADVTXCLK@{CONFIG\_ADVTXCLK}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_ADVTXCLK}{CONFIG\_ADVTXCLK}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+\+ADVTXCLK~0x0020 /$\ast$ Advance TX clock $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00071}{71}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a1b3025e3a27b112181668dc9bf4669f4}\label{lxtphyreg_8h_a1b3025e3a27b112181668dc9bf4669f4}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_DISJABBER@{CONFIG\_DISJABBER}}
\index{CONFIG\_DISJABBER@{CONFIG\_DISJABBER}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_DISJABBER}{CONFIG\_DISJABBER}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+\+DISJABBER~0x0200 /$\ast$ Disable Jabber $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00063}{63}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a33aabb2bf1f84c201f2a530b90fb0d23}\label{lxtphyreg_8h_a33aabb2bf1f84c201f2a530b90fb0d23}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_DISLINKTEST@{CONFIG\_DISLINKTEST}}
\index{CONFIG\_DISLINKTEST@{CONFIG\_DISLINKTEST}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_DISLINKTEST}{CONFIG\_DISLINKTEST}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+\+DISLINKTEST~0x0100 /$\ast$ Disable Link Test $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00064}{64}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_ac9243cd5917bfb1298c999015f27735a}\label{lxtphyreg_8h_ac9243cd5917bfb1298c999015f27735a}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_LEDC0@{CONFIG\_LEDC0}}
\index{CONFIG\_LEDC0@{CONFIG\_LEDC0}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_LEDC0}{CONFIG\_LEDC0}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+\+LEDC0~0x0040 /$\ast$ ... $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00066}{66}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_ab9916d29f7f3c0ce61e03993c3427a18}\label{lxtphyreg_8h_ab9916d29f7f3c0ce61e03993c3427a18}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_LEDC1@{CONFIG\_LEDC1}}
\index{CONFIG\_LEDC1@{CONFIG\_LEDC1}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_LEDC1}{CONFIG\_LEDC1}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+\+LEDC1~0x0080 /$\ast$ LEDC configuration $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00065}{65}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_ac839ed4ef795877c0cfd4fb68b1ee53b}\label{lxtphyreg_8h_ac839ed4ef795877c0cfd4fb68b1ee53b}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_MDIO\_INT@{CONFIG\_MDIO\_INT}}
\index{CONFIG\_MDIO\_INT@{CONFIG\_MDIO\_INT}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_MDIO\_INT}{CONFIG\_MDIO\_INT}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+\+MDIO\+\_\+\+INT~0x1000 /$\ast$ Enable intr signalling on MDIO $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00060}{60}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a268a10df903aa62182f10c96fea3bdeb}\label{lxtphyreg_8h_a268a10df903aa62182f10c96fea3bdeb}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_REPEATER@{CONFIG\_REPEATER}}
\index{CONFIG\_REPEATER@{CONFIG\_REPEATER}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_REPEATER}{CONFIG\_REPEATER}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+\+REPEATER~0x2000 /$\ast$ Repeater Mode $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00059}{59}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a2cc0dac1833de325d06b5c3b564e5b3c}\label{lxtphyreg_8h_a2cc0dac1833de325d06b5c3b564e5b3c}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_SCRAMBLER@{CONFIG\_SCRAMBLER}}
\index{CONFIG\_SCRAMBLER@{CONFIG\_SCRAMBLER}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_SCRAMBLER}{CONFIG\_SCRAMBLER}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+\+SCRAMBLER~0x0008 /$\ast$ Bypass scrambler $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00073}{73}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a1e0186d96d36933f7f9d9678c85e0457}\label{lxtphyreg_8h_a1e0186d96d36933f7f9d9678c85e0457}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_SQE@{CONFIG\_SQE}}
\index{CONFIG\_SQE@{CONFIG\_SQE}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_SQE}{CONFIG\_SQE}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+\+SQE~0x0400 /$\ast$ Enable SQE $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00062}{62}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a0306aba5e57d49fb8be4d910223a9c26}\label{lxtphyreg_8h_a0306aba5e57d49fb8be4d910223a9c26}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_TPLOOP@{CONFIG\_TPLOOP}}
\index{CONFIG\_TPLOOP@{CONFIG\_TPLOOP}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_TPLOOP}{CONFIG\_TPLOOP}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+\+TPLOOP~0x0800 /$\ast$ Disable 10base-\/T Loopback $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00061}{61}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_ad98f41c7dfeb481efc37a3306b60711f}\label{lxtphyreg_8h_ad98f41c7dfeb481efc37a3306b60711f}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_TXDISCON@{CONFIG\_TXDISCON}}
\index{CONFIG\_TXDISCON@{CONFIG\_TXDISCON}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_TXDISCON}{CONFIG\_TXDISCON}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+\+TXDISCON~0x0001 /$\ast$ Disconnect TP transmitter $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00075}{75}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a20bacab53a9293fbde93a077e6c7b1b0}\label{lxtphyreg_8h_a20bacab53a9293fbde93a077e6c7b1b0}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CONFIG\_TXMIT\_TEST@{CONFIG\_TXMIT\_TEST}}
\index{CONFIG\_TXMIT\_TEST@{CONFIG\_TXMIT\_TEST}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CONFIG\_TXMIT\_TEST}{CONFIG\_TXMIT\_TEST}}
{\footnotesize\ttfamily \#define CONFIG\+\_\+\+TXMIT\+\_\+\+TEST~0x4000 /$\ast$ 100base-\/T Transmit Test $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00058}{58}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a834e3d398b9ef5955493636d3f498ca6}\label{lxtphyreg_8h_a834e3d398b9ef5955493636d3f498ca6}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CSR\_ACOMP@{CSR\_ACOMP}}
\index{CSR\_ACOMP@{CSR\_ACOMP}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CSR\_ACOMP}{CSR\_ACOMP}}
{\footnotesize\ttfamily \#define CSR\+\_\+\+ACOMP~0x0400 /$\ast$ Autonegotiation complete $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00081}{81}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_aa458953e69deb60c28f7e7837e28b528}\label{lxtphyreg_8h_aa458953e69deb60c28f7e7837e28b528}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CSR\_DUPLEX@{CSR\_DUPLEX}}
\index{CSR\_DUPLEX@{CSR\_DUPLEX}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CSR\_DUPLEX}{CSR\_DUPLEX}}
{\footnotesize\ttfamily \#define CSR\+\_\+\+DUPLEX~0x1000 /$\ast$ Full-\/duplex $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00079}{79}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a51c29dd356cee9fc63f86e7e319c54a5}\label{lxtphyreg_8h_a51c29dd356cee9fc63f86e7e319c54a5}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CSR\_LINK@{CSR\_LINK}}
\index{CSR\_LINK@{CSR\_LINK}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CSR\_LINK}{CSR\_LINK}}
{\footnotesize\ttfamily \#define CSR\+\_\+\+LINK~0x2000 /$\ast$ Link is up $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00078}{78}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a80d776be70ee75949932b8dfe689afbf}\label{lxtphyreg_8h_a80d776be70ee75949932b8dfe689afbf}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CSR\_LOWVCC@{CSR\_LOWVCC}}
\index{CSR\_LOWVCC@{CSR\_LOWVCC}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CSR\_LOWVCC}{CSR\_LOWVCC}}
{\footnotesize\ttfamily \#define CSR\+\_\+\+LOWVCC~0x0004 /$\ast$ Low Voltage Fault $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00083}{83}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a14ec600cbcd321f3108b189506226f69}\label{lxtphyreg_8h_a14ec600cbcd321f3108b189506226f69}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CSR\_PAGERCVD@{CSR\_PAGERCVD}}
\index{CSR\_PAGERCVD@{CSR\_PAGERCVD}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CSR\_PAGERCVD}{CSR\_PAGERCVD}}
{\footnotesize\ttfamily \#define CSR\+\_\+\+PAGERCVD~0x0200 /$\ast$ Link page received $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00082}{82}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a930c7e7182537108a448ceb230d3111c}\label{lxtphyreg_8h_a930c7e7182537108a448ceb230d3111c}} 
\index{lxtphyreg.h@{lxtphyreg.h}!CSR\_SPEED@{CSR\_SPEED}}
\index{CSR\_SPEED@{CSR\_SPEED}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{CSR\_SPEED}{CSR\_SPEED}}
{\footnotesize\ttfamily \#define CSR\+\_\+\+SPEED~0x0800 /$\ast$ 100\+Mbps $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00080}{80}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_aec24dc69078e5c54365c35013c7ea8a3}\label{lxtphyreg_8h_aec24dc69078e5c54365c35013c7ea8a3}} 
\index{lxtphyreg.h@{lxtphyreg.h}!IER\_INTEN@{IER\_INTEN}}
\index{IER\_INTEN@{IER\_INTEN}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{IER\_INTEN}{IER\_INTEN}}
{\footnotesize\ttfamily \#define IER\+\_\+\+INTEN~0x0002 /$\ast$ Interrupt Enable $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00050}{50}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_ab99807472dc72d12bf53e0fa0637171e}\label{lxtphyreg_8h_ab99807472dc72d12bf53e0fa0637171e}} 
\index{lxtphyreg.h@{lxtphyreg.h}!IER\_LNK\_CRITERIA@{IER\_LNK\_CRITERIA}}
\index{IER\_LNK\_CRITERIA@{IER\_LNK\_CRITERIA}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{IER\_LNK\_CRITERIA}{IER\_LNK\_CRITERIA}}
{\footnotesize\ttfamily \#define IER\+\_\+\+LNK\+\_\+\+CRITERIA~0x0004 /$\ast$ Enhanced Link Loss Criteria $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00049}{49}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_acdf17101db781b4b3588e79aedfcc05d}\label{lxtphyreg_8h_acdf17101db781b4b3588e79aedfcc05d}} 
\index{lxtphyreg.h@{lxtphyreg.h}!IER\_MIIDRVLVL@{IER\_MIIDRVLVL}}
\index{IER\_MIIDRVLVL@{IER\_MIIDRVLVL}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{IER\_MIIDRVLVL}{IER\_MIIDRVLVL}}
{\footnotesize\ttfamily \#define IER\+\_\+\+MIIDRVLVL~0x0008 /$\ast$ Rediced MII driver levels $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00048}{48}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a2b7452859006cbaaeba913fcfb11e5c4}\label{lxtphyreg_8h_a2b7452859006cbaaeba913fcfb11e5c4}} 
\index{lxtphyreg.h@{lxtphyreg.h}!IER\_TINT@{IER\_TINT}}
\index{IER\_TINT@{IER\_TINT}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{IER\_TINT}{IER\_TINT}}
{\footnotesize\ttfamily \#define IER\+\_\+\+TINT~0x0001 /$\ast$ Force Interrupt $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00051}{51}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_ada01d4f52eb2b980d547eba00f35f404}\label{lxtphyreg_8h_ada01d4f52eb2b980d547eba00f35f404}} 
\index{lxtphyreg.h@{lxtphyreg.h}!ISR\_MINT@{ISR\_MINT}}
\index{ISR\_MINT@{ISR\_MINT}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{ISR\_MINT}{ISR\_MINT}}
{\footnotesize\ttfamily \#define ISR\+\_\+\+MINT~0x8000 /$\ast$ MII Interrupt Pending $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00054}{54}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_af20621420d1461f1c70f256e8f7b5daf}\label{lxtphyreg_8h_af20621420d1461f1c70f256e8f7b5daf}} 
\index{lxtphyreg.h@{lxtphyreg.h}!ISR\_XTALOK@{ISR\_XTALOK}}
\index{ISR\_XTALOK@{ISR\_XTALOK}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{ISR\_XTALOK}{ISR\_XTALOK}}
{\footnotesize\ttfamily \#define ISR\+\_\+\+XTALOK~0x4000 /$\ast$ Clocks OK $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00055}{55}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a79a0ecfa68fb4a8ffb6d9fbd7ba5993d}\label{lxtphyreg_8h_a79a0ecfa68fb4a8ffb6d9fbd7ba5993d}} 
\index{lxtphyreg.h@{lxtphyreg.h}!MII\_LXTPHY\_CONFIG@{MII\_LXTPHY\_CONFIG}}
\index{MII\_LXTPHY\_CONFIG@{MII\_LXTPHY\_CONFIG}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{MII\_LXTPHY\_CONFIG}{MII\_LXTPHY\_CONFIG}}
{\footnotesize\ttfamily \#define MII\+\_\+\+LXTPHY\+\_\+\+CONFIG~0x13 /$\ast$ Configuration Register $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00057}{57}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_aebbbaa387a7511507dc51703294a6b67}\label{lxtphyreg_8h_aebbbaa387a7511507dc51703294a6b67}} 
\index{lxtphyreg.h@{lxtphyreg.h}!MII\_LXTPHY\_CSR@{MII\_LXTPHY\_CSR}}
\index{MII\_LXTPHY\_CSR@{MII\_LXTPHY\_CSR}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{MII\_LXTPHY\_CSR}{MII\_LXTPHY\_CSR}}
{\footnotesize\ttfamily \#define MII\+\_\+\+LXTPHY\+\_\+\+CSR~0x14 /$\ast$ Chip Status Register $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00077}{77}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a0093c80420ee3e9b0bef20bab35a2692}\label{lxtphyreg_8h_a0093c80420ee3e9b0bef20bab35a2692}} 
\index{lxtphyreg.h@{lxtphyreg.h}!MII\_LXTPHY\_IER@{MII\_LXTPHY\_IER}}
\index{MII\_LXTPHY\_IER@{MII\_LXTPHY\_IER}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{MII\_LXTPHY\_IER}{MII\_LXTPHY\_IER}}
{\footnotesize\ttfamily \#define MII\+\_\+\+LXTPHY\+\_\+\+IER~0x11 /$\ast$ Interrupt Enable Register $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00047}{47}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_a737d21111a0121124474ae2d023bfc09}\label{lxtphyreg_8h_a737d21111a0121124474ae2d023bfc09}} 
\index{lxtphyreg.h@{lxtphyreg.h}!MII\_LXTPHY\_ISR@{MII\_LXTPHY\_ISR}}
\index{MII\_LXTPHY\_ISR@{MII\_LXTPHY\_ISR}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{MII\_LXTPHY\_ISR}{MII\_LXTPHY\_ISR}}
{\footnotesize\ttfamily \#define MII\+\_\+\+LXTPHY\+\_\+\+ISR~0x12 /$\ast$ Interrupt Status Register $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00053}{53}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

\mbox{\Hypertarget{lxtphyreg_8h_abcbb774f2c00adb55dc58cabcfdba355}\label{lxtphyreg_8h_abcbb774f2c00adb55dc58cabcfdba355}} 
\index{lxtphyreg.h@{lxtphyreg.h}!MII\_LXTPHY\_MIRROR@{MII\_LXTPHY\_MIRROR}}
\index{MII\_LXTPHY\_MIRROR@{MII\_LXTPHY\_MIRROR}!lxtphyreg.h@{lxtphyreg.h}}
\doxysubsubsection{\texorpdfstring{MII\_LXTPHY\_MIRROR}{MII\_LXTPHY\_MIRROR}}
{\footnotesize\ttfamily \#define MII\+\_\+\+LXTPHY\+\_\+\+MIRROR~0x10 /$\ast$ Mirror register $\ast$/}



Definition at line \mbox{\hyperlink{lxtphyreg_8h_source_l00044}{44}} of file \mbox{\hyperlink{lxtphyreg_8h_source}{lxtphyreg.\+h}}.

