\hypertarget{lio__mem__ops_8h_source}{}\doxysection{lio\+\_\+mem\+\_\+ops.\+h}
\label{lio__mem__ops_8h_source}\index{dev/liquidio/base/lio\_mem\_ops.h@{dev/liquidio/base/lio\_mem\_ops.h}}
\mbox{\hyperlink{lio__mem__ops_8h}{Go to the documentation of this file.}}
\begin{DoxyCode}{0}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00001}00001 \textcolor{comment}{/*}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00002}00002 \textcolor{comment}{ *   BSD LICENSE}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00003}00003 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00004}00004 \textcolor{comment}{ *   Copyright(c) 2017 Cavium, Inc.. All rights reserved.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00005}00005 \textcolor{comment}{ *   All rights reserved.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00006}00006 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00007}00007 \textcolor{comment}{ *   Redistribution and use in source and binary forms, with or without}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00008}00008 \textcolor{comment}{ *   modification, are permitted provided that the following conditions}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00009}00009 \textcolor{comment}{ *   are met:}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00010}00010 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00011}00011 \textcolor{comment}{ *     * Redistributions of source code must retain the above copyright}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00012}00012 \textcolor{comment}{ *       notice, this list of conditions and the following disclaimer.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00013}00013 \textcolor{comment}{ *     * Redistributions in binary form must reproduce the above copyright}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00014}00014 \textcolor{comment}{ *       notice, this list of conditions and the following disclaimer in}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00015}00015 \textcolor{comment}{ *       the documentation and/or other materials provided with the}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00016}00016 \textcolor{comment}{ *       distribution.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00017}00017 \textcolor{comment}{ *     * Neither the name of Cavium, Inc. nor the names of its}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00018}00018 \textcolor{comment}{ *       contributors may be used to endorse or promote products derived}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00019}00019 \textcolor{comment}{ *       from this software without specific prior written permission.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00020}00020 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00021}00021 \textcolor{comment}{ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00022}00022 \textcolor{comment}{ *   "{}AS IS"{} AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00023}00023 \textcolor{comment}{ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00024}00024 \textcolor{comment}{ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00025}00025 \textcolor{comment}{ *   OWNER(S) OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00026}00026 \textcolor{comment}{ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00027}00027 \textcolor{comment}{ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00028}00028 \textcolor{comment}{ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00029}00029 \textcolor{comment}{ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00030}00030 \textcolor{comment}{ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00031}00031 \textcolor{comment}{ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00032}00032 \textcolor{comment}{ */}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00033}00033 \textcolor{comment}{/*\$FreeBSD\$*/}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00034}00034 }
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00035}00035 \textcolor{comment}{/*}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00036}00036 \textcolor{comment}{ *   \(\backslash\)file lio\_mem\_ops.h}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00037}00037 \textcolor{comment}{ *   \(\backslash\)brief Host Driver: Routines used to read/write Octeon memory.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00038}00038 \textcolor{comment}{ */}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00039}00039 }
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00040}00040 \textcolor{preprocessor}{\#ifndef \_\_LIO\_MEM\_OPS\_H\_\_}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00041}00041 \textcolor{preprocessor}{\#define \_\_LIO\_MEM\_OPS\_H\_\_}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00042}00042 }
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00043}00043 \textcolor{comment}{/*}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00044}00044 \textcolor{comment}{ *   Read a 64-\/bit value from a BAR1 mapped core memory address.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00045}00045 \textcolor{comment}{ *   @param  oct        -\/  pointer to the octeon device.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00046}00046 \textcolor{comment}{ *   @param  core\_addr  -\/  the address to read from.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00047}00047 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00048}00048 \textcolor{comment}{ *   The range\_idx gives the BAR1 index register for the range of address}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00049}00049 \textcolor{comment}{ *   in which core\_addr is mapped.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00050}00050 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00051}00051 \textcolor{comment}{ *   @return  64-\/bit value read from Core memory}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00052}00052 \textcolor{comment}{ */}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00053}00053 uint64\_t        \mbox{\hyperlink{lio__mem__ops_8h_a815b6f0310e3ff761a1e98a54fd090e2}{lio\_read\_device\_mem64}}(\textcolor{keyword}{struct} \mbox{\hyperlink{structocteon__device}{octeon\_device}} *oct,}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00054}00054                                       uint64\_t core\_addr);}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00055}00055 }
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00056}00056 \textcolor{comment}{/*}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00057}00057 \textcolor{comment}{ *   Read a 32-\/bit value from a BAR1 mapped core memory address.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00058}00058 \textcolor{comment}{ *   @param  oct        -\/  pointer to the octeon device.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00059}00059 \textcolor{comment}{ *   @param  core\_addr  -\/  the address to read from.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00060}00060 \textcolor{comment}{ *}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00061}00061 \textcolor{comment}{ *   @return  32-\/bit value read from Core memory}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00062}00062 \textcolor{comment}{ */}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00063}00063 uint32\_t        \mbox{\hyperlink{lio__mem__ops_8h_aaa0f8d2779a286ac5ced0de1182781c8}{lio\_read\_device\_mem32}}(\textcolor{keyword}{struct} \mbox{\hyperlink{structocteon__device}{octeon\_device}} *oct,}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00064}00064                                       uint64\_t core\_addr);}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00065}00065 }
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00066}00066 \textcolor{comment}{/*}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00067}00067 \textcolor{comment}{ *   Write a 32-\/bit value to a BAR1 mapped core memory address.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00068}00068 \textcolor{comment}{ *   @param  oct        -\/  pointer to the octeon device.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00069}00069 \textcolor{comment}{ *   @param  core\_addr  -\/  the address to write to.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00070}00070 \textcolor{comment}{ *   @param  val        -\/  32-\/bit value to write.}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00071}00071 \textcolor{comment}{ */}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00072}00072 \textcolor{keywordtype}{void}            \mbox{\hyperlink{lio__mem__ops_8h_ac80a89e6f4560ce7e9815750bd54c7eb}{lio\_write\_device\_mem32}}(\textcolor{keyword}{struct} \mbox{\hyperlink{structocteon__device}{octeon\_device}} *oct,}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00073}00073                                        uint64\_t core\_addr, uint32\_t val);}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00074}00074 }
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00075}00075 \textcolor{comment}{/* Read multiple bytes from Octeon memory. */}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00076}00076 \textcolor{keywordtype}{void}            \mbox{\hyperlink{lio__mem__ops_8h_a45994a9251fc63e2f51c86b503773cce}{lio\_pci\_read\_core\_mem}}(\textcolor{keyword}{struct} \mbox{\hyperlink{structocteon__device}{octeon\_device}} *oct,}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00077}00077                                       uint64\_t coreaddr, uint8\_t *buf,}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00078}00078                                       uint32\_t len);}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00079}00079 }
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00080}00080 \textcolor{comment}{/* Write multiple bytes into Octeon memory. */}}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00081}00081 \textcolor{keywordtype}{void}            \mbox{\hyperlink{lio__mem__ops_8h_a1369fd16acd4008689763e9a39154db3}{lio\_pci\_write\_core\_mem}}(\textcolor{keyword}{struct} \mbox{\hyperlink{structocteon__device}{octeon\_device}} *oct,}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00082}00082                                        uint64\_t coreaddr, uint8\_t *buf,}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00083}00083                                        uint32\_t len);}
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00084}00084 }
\DoxyCodeLine{\Hypertarget{lio__mem__ops_8h_source_l00085}00085 \textcolor{preprocessor}{\#endif  }\textcolor{comment}{/* \_\_LIO\_MEM\_OPS\_H\_\_ */}\textcolor{preprocessor}{}}

\end{DoxyCode}
